CN1260795C - 半导体装置及其制造方法、电路板以及电子机器 - Google Patents
半导体装置及其制造方法、电路板以及电子机器 Download PDFInfo
- Publication number
- CN1260795C CN1260795C CNB031037763A CN03103776A CN1260795C CN 1260795 C CN1260795 C CN 1260795C CN B031037763 A CNB031037763 A CN B031037763A CN 03103776 A CN03103776 A CN 03103776A CN 1260795 C CN1260795 C CN 1260795C
- Authority
- CN
- China
- Prior art keywords
- wire
- salient point
- lead
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
- B23K20/004—Wire welding
- B23K20/005—Capillary welding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
- B23K20/004—Wire welding
- B23K20/005—Capillary welding
- B23K20/007—Ball bonding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/10—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating making use of vibrations, e.g. ultrasonic welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/42—Printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
- H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
- H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
- H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
- H01L2224/48499—Material of the auxiliary connecting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48647—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Mechanical Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
一种半导体装置的制造方法,通过工具(130),将引线(120)的前端部(122)焊接在第1电极(52)上。将引线(120)从第1电极(52)引出到第2电极(12)上的凸点(40)。通过工具(130)中在引线(120)的引出方向的第1电极(52)侧的部分,将引线(120)的一部分焊接在凸点40的引线(120)的引出方向的中心或越过中心的部分上。从而实现将引线以可靠并且稳定的状态焊接在凸点上的目的。
Description
技术领域
本发明涉及一种半导体装置及其制造方法、电路板以及电子机器
背景技术
在半导体装置的制造中,周知的有在电极上的凸点上进行引线的二次焊接的技术。根据这种技术,可以降低引线的环高度,从而可以制造薄型半导体装置。另一方面,将引线连接到凸点上时,确保大的引线与凸点的接合区域和以可靠稳定的状态接合二者是很重要的。
发明内容
本发明的目的在于可以在可靠并且稳定的状态下将引线焊接在凸点上。
(1)本发明的半导体装置的制造方法,包括
(a)通过工具将引线的前端部焊接在第1电极上的工艺、
(b)将所述引线从所述第1电极引出到第2电极上的凸点的工艺、以及
(c)利用所述工具中的所述第1电极侧的部分,将所述引线的一部分焊接在所述凸点的中心或沿所述引线的引出方向越过所述中心的部分上的工艺。
依据本发明,由于是将引线的一部分焊接在凸点上的引线的引出方向的中心或越过它的部分上,所以可以避免例如工具对引线中从凸点伸到第1电极侧的部分的挤压。因而,可以防止引线的下垂。因此,可以将引线以可靠并且稳定的状态焊接在凸点上。
(2)在该半导体装置的制造方法中,也可以在所述(c)工艺中,通过所述工具,将所述凸点的一部分压扁。
这样,可以以凸点中没有被压扁的部分为支点,将引线向与电极相反的方向(上方)拉起。因此,可以防止引线与形成有电极的部件接触。
(3)在该半导体装置的制造方法中,也可以在所述(c)工艺中,在通过加压而压扁所述引线的同时,使所述工具在所述凸点上沿所述凸点的宽度方向移动。
这样,由于是在加压时使工具沿引线的前端部的宽度方向移动,所以可以形成最佳形状的凸点。
(4)在该半导体装置的制造方法中,也可以在所述(c)工艺中,使所述工具在所述凸点上沿所述引线的引出方向移动。
这样,例如可以使凸点在所述引线的引出方向变宽或沿引线的引出方向逐渐降低。
(5)在该半导体装置的制造方法中,也可以在所述(c)工艺中,使形成的所述凸点在所述引线的引出方向变宽。
这样,例如,可以有利于将其它引线焊接在凸点上。
(6)在该半导体装置的制造方法中,也可以在所述(c)工序中,使形成的所述凸点,从所述引线开始沿其引出方向离开越远则越低。
这样,例如,可以有利于将其它引线焊接在凸点上。
(7)在该半导体装置的制造方法中,也可以在实施所述(c)工艺时,同时对所述凸点施加超声波振动。
这样,可以稳定引线的连续加工性。
(8)在该半导体装置的制造方法中,也可以使所述工具具有能够贯穿所述引线的孔;在所述(c)工艺中,通过所述孔的开口端部上的所述第1电极侧的部分,进行焊接。
这样,可以以凸点中没有被压扁的部分作为支点将第1引线向与第2电极相反的方向(上方)提升。为此,可以防止第1引线和形成第2电极的部件之间的接触。
(9)在该半导体装置的制造方法中,也可以在所述(a)工艺之前,还包括
(e)将在第2引线上的形成球状的前端部焊接在所述第2电极上的工艺、
(f)将所述第2引线的一部分从焊接后的所述前端部引出的工艺、
(g)将所述第2引线中与所述前端部连接的部分在所述前端部上压扁后在所述第2电极上形成所述凸点的工艺、以及
(h)在所述第2电极上留下所述凸点并将所述第2引线切断的工艺。
这样,可以在电极上容易地形成大致呈平坦面的凸点。
(10)在该半导体装置的制造方法中,也可以在所述(g)工艺中,将所述凸点形成为具有连接在所述第2电极上的下端部、和大致呈平坦面的上端部。
(11)在该半导体装置的制造方法中,也可以在所述(g)工艺中,将所述凸点的所述上端部,在与所述凸点连接的所述第1引线的向所述凸点引出的方向上加宽形成。
这样,有利于将第1引线焊接在凸点的上端部。
(12)在该半导体装置的制造方法中,也可以在所述(g)工艺中,使所述凸点的所述上端部沿向外的方向逐渐降低。
这样,有利于将第1引线焊接在凸点的上端部。
(13)本发明的半导体装置,由所述方法而制造。
(14)本发明的半导体装置,包括:具有成为第1电极的部分的引出脚;具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的半导体芯片;具有第1及第2端部、所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在所述引线的向所述凸点的引出方向变宽,且从所述引线开始沿其引出方向离开越远则越低,
所述引线的所述第2端部连接在所述凸点的中心或沿所述引线的所述引出方向越过所述中心的部分。
依据本发明,由于是所述凸点的所述上端部,在所述引线的向所述凸点的引出方向变宽,且沿引线的向凸点的引出方向逐渐降低,所以有利于将引线焊接在凸点的上端部,并且二者的电连接可靠性高。
另外,由于是所述引线的所述第2端部连接在所述凸点的中心或沿所述引线的所述引出方向越过所述中心的部分,所以可以防止引线中从凸点伸出电极侧的部分的下垂。因此,可以以可靠且稳定的状态,将引线与凸点电连接。
(15)本发明的半导体装置,包括具有集成电路及第1电极的半导体芯片;具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的另一半导体芯片;具有第1及第2端部,所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在所述引线的向所述凸点的引出方向变宽,且从所述引线开始沿其引出方向离开越远则越低,
所述引线的所述第2端部焊接在所述凸点的中心或沿所述引线的所述引出方向越过所述中心的部分。
依据本发明,由于是所述凸点的所述上端部,在所述引线的向所述凸点的引出方向变宽,且沿引线的向凸点的引出方向逐渐降低,所以有利于将引线焊接在凸点的上端部,并且二者的电连接可靠性高。
另外,由于是所述引线的所述第2端部连接在所述凸点的中心或沿所述引线的所述引出方向越过所述中心的部分,所以可以防止引线中从凸点伸出电极侧的部分的下垂。因此,可以以可靠且稳定的状态,将引线与凸点电连接。
(16)在该半导体装置中,也可以将所述凸点的一部分压扁。
这样,可以以凸点中没有被压扁的部分为支点,将引线向与电极相反的方向(上方)拉起。因此,可以防止引线与半导体芯片接触。
(17)本发明的电路板,安装了上述半导体装置。
(18)本发明的电子机器,具有上述半导体装置。
附图说明
图1A~图1C表示有关本发明第1实施方案的凸点的形成方法以及带凸点的半导体元件的制造方法。
图2A以及图2B表示有关本发明第1实施方案的凸点的形成方法以及带凸点的半导体元件的制造方法。
图3表示有关本发明第1实施方案的带凸点的半导体元件及其制造方法。
图4表示图3的IV-IV线的截面图。
图5表示有关本发明第1实施方案的带凸点的半导体元件及其制造方法。
图6表示有关本发明第1实施方案的带凸点的半导体元件及其制造方法。
图7表示有关本发明第1实施方案的带凸点的半导体元件及其制造方法。
图8表示图7的VIII-VIII线的截面图。
图9表示有关本发明第2实施方案的半导体装置的制造方法。
图10表示有关本发明第2实施方案的半导体装置及其制造方法。
图11表示有关本发明第2实施方案的半导体装置及其制造方法。
图12表示有关本发明第2实施方案的半导体装置及其制造方法。
图13A以及图13B表示有关本发明第2实施方案的变形例的半导体装置及其制造方法。
图14表示有关本发明第2实施方案的半导体装置。
图15A以及图15B表示有关本发明第3实施方案的半导体装置及其制造方法。
图16表示图15的部分放大图。
图17表示有关本发明第3实施方案的半导体装置及其制造方法。
图18表示有关本发明第3实施方案的半导体装置及其制造方法。
图19表示有关本发明第3实施方案的半导体装置。
图20表示有关本发明第3实施方案的半导体装置。
图21表示有关本发明的实施方案的电路板。
图22表示有关本发明的实施方案的电子机器。
图23表示有关本发明的实施方案的电子机器。
具体实施方式
以下参照附图说明本发明的实施方案。但是,本发明并不限定于以下的实施方案。
(第1实施方案)
图1A~图8表示本实施方案的带凸点的半导体元件的制造方法。在本实施方案中,在半导体元件10的电极12上形成凸点40。凸点40,通过使用工具30将引线20焊接在电极12上形成。凸点40作为引线键合用的端子使用。
此外,本实施方案的带凸点的半导体元件的制造方法,包括图1A~图2B所示的凸点的形成方法。
首先,如图1A所示,准备好半导体元件10。半导体元件10可以是半导体晶片14(参见图5)或者半导体芯片16(参见图6)中的任一种。即,凸点形成过程可以在晶片状态下统一处理,也可以在芯片状态下处理。半导体元件10包括集成电路,例如多在直方体(包括立方体或者板状)上形成。集成电路多在任意一个面(例如最宽的面)上形成。
半导体元件10具有1个或者多个电极12。电极12是在半导体元件10的面上薄薄平坦形成的焊盘。电极12在半导体元件10的具有集成电路的面上形成。这时,电极12也可以在集成电路区域的外侧上形成。使用半导体芯片16时,电极12多在半导体芯片16的面的端部(例如外形的2边或者4边的端部)上形成。同样,使用半导体晶片14时,电极12多在半导体晶片14的包含1个集成电路的区域15(参见图5)的端部(例如区域的2边或者4边的端部)上形成。电极12采用铝系或者铜系金属形成。
在半导体元件10上,在避开各电极12的至少一部分的位置上形成钝化膜(图中未画出)。钝化膜,例如可以采用SiO2、SiN或者聚酰亚胺树脂等形成。
如图1A所示,准备好支撑引线20的工具30。引线20由金等导电材料构成。工具30使引线20的轴方向相对于电极12的面垂直那样支撑引线20。在图1A所示的例中,工具30包括孔32,引线20贯穿孔32的内侧中。孔32的宽度(直径)比引线20的宽度(直径)要大。这样,可以在孔32的轴方向上将引线20送出。工具30也可以是半导体装置的制造中所使用的毛细管。工具也可以采用孔以外的引导装置支撑引线20。此外,工具30由图中未画出的支撑体(例如超声波喇叭)被支撑在图中未画出的制造装置的本体(引线焊接机)上。
引线20由夹具36夹持。夹具26配置在工具30的上方,即电极12相反侧。打开夹具36后,可以由工具30对引线20进行操作。此外,在图1A所示的例中,工具30以及夹具36虽然分别独立构成,也可以将工具30以及夹具36一体构成,例如也可以使工具30具有夹具36的功能。
引线20的前端部22,从孔32中从电极12侧的开口部伸出到外部。孔32的开口端部(或者按压部)34,可以按压住引线20的一部分(参见图1B、图2A以及图2B)。如图所示,开口端部34的一部分(工具的外周附近)也可以倾斜。或者开口端部34也可以是平坦面。
如图1A所示,工具30配置在半导体元件10的电极12侧(详细讲在电极12的上方)。然后,引线20的前端部22形成为球状(或者块状)。可以通过热能(例如放电或者燃气火焰)将其前端部22熔化后形成为球状。也可以使图中未画出的电焊矩接近前端部22,进行高压放电将前端部22熔化。
如图1B所示,引线20的前端部22配置在任意一个电极12的上方,在夹具36开放的状态下,降下工具30。这样,将引线20的前端部22焊接在电极12上。详细讲,通过工具30的开口端部34按压引线20的前端部22。优选在按压前端部22的期间施加超声波振动或者热等。这样,可以使前端部22和电极12以良好的状态连接。此外,通过开口端部34的按压,在引线20的前端部22上形成上端部以及比上端部面积大(或者宽度宽)的下端部。
然后,如图1C所示,将引线20的一部分24从焊接后的前端部22引出。由于前端部22连接在电极12上,通过使工具30朝离开电极12的方向移动,可以将引线20的一部分24从前端部22引出。
在图1C所示的例中,将引线20的一部分24弯曲引出。这样,引线20中与前端部22连接的部分在前端部22上容易压扁。例如,可以使工具30先向前端部22的高度方向移动,向电极12的上方引出引线20,然后向前端部22的宽度方向移动使引线20的一部分24弯曲。引线20的一部分24的弯曲方式(形状以及方法)并不限定于上述方式。
如图2A所示,用工具30将与前端部22连接的部分压扁。详细讲,在引线20中从前端部22引出的部分(引线20的一部分24)中至少将与前端部22连接的部分压扁。如图2A所示,开口端部34中用以孔32为基准的一边侧的部分(与工具30移动侧相反一侧的部分)将引线20压扁。引线20中与前端部22连接的部分在前端部22上压扁后成平坦面。在进行压扁时,优选施加超声波振动。这样,在电极12上形成凸点40。在此,凸点40具有与电极12连接的下端部44和具有大致平坦面(削掉引线的突起的面)的上端部42(参见图4)。
如图2A所示,使工具30向前端部22加压的同时,在前端部22上向前端部22的宽度方向(图2A的箭头所示方向)移动。换言之,使工具30向前端部22加压的同时,向与半导体元件10的面平行的方向上滑动。这样,可以形成图3以及图4所示的最佳形状的凸点40。在此,图3表示凸点形成后的半导体元件的平面图,图4表示图3的的IV-IV线的截面图。
在使工具30向前端部22的宽度方向(图3以及图4的箭头所示方向)移动的过程中,也可以在工具30的移动方向上加宽凸点40的上端部42。换言之,在凸点42的平面视图中,使凸点40的上端部42形成为椭圆形状。
这样,在后续工艺中,容易将其它引线120焊接在凸点40的上端部42上(参见图7以及图8)。详细讲,通过在凸点40加宽的方向上引出引线120,可以确保引线120和凸点40有较宽的连接区域。因此,可以在可靠并且稳定的状态下将引线120焊接在凸点40上。
在使工具30向前端部22的宽度方向(图3以及图4的箭头所示方向)移动的过程中,也可以在工具30的移动方向上降低(减薄)形成凸点40的上端部42。换言之,凸点40的高度也可以在工具30的移动方向上降低倾斜形成。
这样,在后续工艺中,容易将其它引线120焊接在凸点40的上端部42上(参见图7以及图8)。详细讲,通过从凸点40较高侧向凸点40引出引线120,可以增大引线120和半导体元件10之间的距离。为此,可以防止引线120和半导体元件10接触。另外,由于可以避免引线120和半导体元件10接触,在引线120的环形状、环高度、电极12和半导体芯片16的角部(边缘)之间的距离等的设计上没有限制,可以自由进行设计(例如引线的低环化以及短环化)。
图7以及图8表示工具30的移动方向(前端部22的宽度方向的移动方向)的图。详细讲,图7表示凸点形成后的半导体芯片的平面图,图8表示图7的VIII-VIII线的截面图。图7的箭头所示方向是指在后续工艺中所连接的引线120向凸点40引出的方向。引线120用于将半导体芯片16的电极12和其它电子部件(例如电路板的布线或者其它半导体芯片)电连接。
如图7所示,也可以使工具30向连接在凸点40上的引线120向凸点40引出的方向移动。此外,因袭120的引出方向并不限定与图7的箭头所示方向,可以根据凸点40(或者电极12)的位置自由确定。
多个电极12在半导体芯片16的端部(图7中外形的4边的端部)上形成时,也可以使工具30从半导体芯片16的端部向中央部的方向移动。如图7所示,多个电极12在半导体芯片16的端部上形成时,引线120多从半导体芯片16的端部向中央部的方向引出。例如,多个中2个以上的引线120从聚焦在半导体芯片16的中央部的1点(图中未画出)的方向延伸从凸点40引出。
这样,如图7以及图8所示,凸点40的上端部可以在引线120的引出方向上加宽(细长)。另外,如图8所示,凸点40的上端部42也可以在引线120的引出方向上逐步降低(减薄)形成。即,凸点40中半导体芯片16的端部侧比中央部侧高。其效果如上所述。
此外,上述工具30的移动方向的说明,并不限定于半导体芯片16,也可以适用于半导体晶片14中。详细讲,如图5以及图6所示,如果用半导体晶片14中包含任意一个集成电路的区域15替代半导体芯片16,就可以适用上述工具30的移动方向的说明。
在图2A以及图2B所示的例中,通过使工具30向前端部22的宽度方向移动,将引线20拉薄引出后切断。这时,工具30在使引线20中贯穿工具30的孔32中的部分从前端部22离开的方向(图2A的箭头所示方向)上移动。这样,可以使凸点40的上端部42成最佳形状,同时将引线20切断。另外,可以在施加超声波振动的同时使工具30在前端部22的宽度方向上移动,在给定位置上切断引线20。即,形成多个凸点时,每次可以在一定的位置上切断引线20。为此,引线20中凸出到工具30的外部的部分的长度每次都是一定的,这样,可以使球状的前端部22的直径大小每次都相同。因此,可以稳定连续进行引线20的加工。
此外,当半导体元件10具有多个电极12时,反复进行上述各工艺(图1A~图2B所示工艺),可以在各电极12上形成凸点40。即,凸出到图2B所示的工具30的外部的前端部,如图1A所示再次形成球状,并焊接到半导体元件10的其它电极上。
在上述的例中,虽然示出的是在半导体元件10的电极12上形成凸点的例子,在本实施方案的凸点形成方法中,并不限定电极的方式,例如也可以在引出脚(电路板上的布线或者引出脚板的内引出脚)的一部分上形成凸点。
依据有关本实施方案的带凸点的半导体元件的制造方法,可以在电极12上简单形成具有大致平坦面的凸点40。另外,利用焊接时使用的工具30在电极12上形成凸点40,并且使凸点40的面平坦,制造过程简单并且快捷。这样,例如没有必要专门进行使凸点40的面平坦的工艺(例如平坦化工艺)。
另外,由于可以将凸点40形成为在后续工艺中所进行的焊接中最适合的形状,可以防止引线120偏离凸点40位置,或者引线120弯曲的状态下焊接。
此外,有关本实施方案的凸点形成方法,可以选择适用根据上述制造方法中说明的内容引导出的任何事项(构成、作用以及效果)。
图3~图8表示本实施方案的带凸点的半导体元件。该带凸点的半导体元件,可以采用上述方法制造。另外,在以下的说明中,将省略根据上述方法的内容所引导出的事项。
半导体元件10,可以是图5所示的半导体晶片14,也可以是图6所示的半导体芯片16。
如图3所示,凸点40的上端部42,在半导体元件10的平面视图中,在某一方向上被加宽。详细讲,如图7所示,上端部42在引线120的向凸点40引出的方向上被加宽。或者,上端部42在从半导体芯片16(或者半导体晶片14的区域15(参见图5))的端部向中央部的方向上被加宽。
如图4所示,凸点40的上端部42在某一方向上倾斜。可以象图4那样上端部42的一部分倾斜,也可以整体倾斜。上端部42至少一部分为大致平坦面。如图8所示,上端部42在引线120的向凸点40引出的方向上逐渐降低而倾斜。或者,上端部42在从半导体芯片16(或者半导体晶片14的区域15(参见图5))的端部向中央部的方向上逐渐降低而倾斜
依据有关本实施方案的带凸点的半导体元件,在凸点40的上端部42上容易将引线(例如引线120)焊接。
(第2实施方案)
图9~图14表示有关本实施方案的半导体装置及其制造方法。在本实施方案中,在凸点40上进行引线120的第2次焊接。
在以下所示的例子中,使用上述实施方案中说明的带凸点半导体芯片(包含采用上述方法制造的半导体芯片),制造半导体装置。此外,半导体芯片16也可以将上述带凸点半导体晶片14分割成多个单片后形成。
或者也可以对与上述实施方案不同的半导体芯片(例如周知的半导体芯片)实施本实施方案的内容。
图9~图12表示引线的第2次焊接工艺。图10表示图9的半导体芯片的部分平面图,图12表示图11的半导体芯片的部分平面图。此外,在图10中工具用2点虚线表示。
首先,如图9所示,在半导体芯片16的外侧配置电极52。在图9所示的例中,电极52是由基板50支撑的引出脚(或者布线)的一部分。电极52也可以是焊盘。通过将半导体芯片16搭载在基板50上,将电极52配置在半导体芯片16的外侧。
基板50可以采用有机系(聚酰亚胺树脂等可挠性基板)或者无机系(陶瓷基板、玻璃基板)的任一种材料形成,也可以采用这些材料的复合机构(玻璃环氧树脂基板)构成。基板50可以是单层基板,也可以是多层基板。
作为变形例,电极52也可以是板材的引出脚板上支撑的引出脚的一部分(例如内引出脚)。这时,引出脚是不被支撑的自由端。引出脚具有内引出脚以及外引出脚,内引出脚的部分面向半导体芯片16的电极12配置。通过将半导体芯片16搭载在图中未画出的裸片衬垫(或者散热片)上,将电极52配置半导体芯片16的外侧。
如图9所示,准备好支撑引线120的工具130。然后,将引线120的前端部122形成为球状,用工具130将引线120的前端部122焊接在电极52上。引线120、工具130以及夹具136的事项,可以适用上述内容。工具130具有孔132以及开口部134。另外,引线120的前端部122形成为球状的方法也和上述相同。
如图9所示,在将前端部122焊接在电极52上之后,将引线120引出到电极12上的凸点40。详细讲,如图10所示,引线120被引出到越过凸点40的中心线L的位置。在此,中心线L,如图10所示,是指在引线120的引出方向上通过凸点40的宽度的中心的假想线,和引线120的引出方向垂直的假想线。
然后,将引线120的一部分焊接在凸点40上。这时,工具130(详细讲开口端部134)中使用在引线120的引出方向上第1电极侧的部分进行焊接。引线120的一部分,如图9以及图10所示,也可以焊接在凸点40中引线120的引出方向的中心(与图10的中心线L重叠的部分)位置上,或者也可以焊接在越过中心的部分(图10的中心线L的右侧部分)上。在图9以及图10所示的例中,通过开口端部134按压凸点40中包含引线120的引出方向的中心的区域。如图9以及图10所示,可以将凸点40以及引线120重叠部分的一部分焊接,也可以全部焊接。在前者,优选对引线120中,凸点40中没有越过引线120的引出方向中心的部分(图10的中心线L的左侧部分)的至少一部分不进行按压。这样,可以由没有被按压的部分支撑(上拉)引线120。即,可以防止引线120和半导体芯片16接触。
在向凸点40的焊接工艺中,优选在施加超声波振动的状态下进行。超声波振动通过工具130施加在凸点40上。这样,可以使引线120和凸点40以良好的状态连接。
在图9所示的例中,对工具130加压将引线120的一部分压扁,同时使工具130在凸点40上沿凸点40的宽度方向移动。换言之,在按压凸点40的同时,使工具130在与半导体芯片16的面平行的方向上滑动。这时,也可以使工具130沿引线120向凸点40的引出方向(图9或者图10的箭头所示方向)移动。
这样,凸点40(特别是上端部42)可以加宽(变细长)引线120的引出方向。这样,在后续工艺中,可以容易将其它引线220焊接在凸点40上(参见图15A)。详细讲,可以确保引线220和凸点40有较宽的连接区域。因此,可以在可靠并且稳定的状态下将引线220焊接在凸点40上。另外,凸点40,由于可以在引线120的引出方向上加宽,可以防止相邻凸点40之间相互短路。进一步,由于在工具130的移动方向上可以加宽凸点40,对由超声波振动加宽凸点40在方向上没有限制,可以在自由方向上加宽凸点40。
另外,通过工具130的移动,可以在引线120向凸点40的引出方向上将凸点40的上端部42逐渐降(减薄)。
这样,在后续工艺中,可以容易将其它引线220焊接在凸点40上(参见图15A)。详细讲,可以容易将引线220的形成了球状的前端部222焊接在偏离凸点40的中心的位置上。
在图9以及图11所示的例子中,通过使工具130在前端部122的宽度方向上移动,将引线120拉薄引出后切断。这时,这时,工具130在使引线120中贯穿工具130的孔132中的部分从凸点40离开的方向(图9的箭头所示方向)上移动。这样,可以凸点40成最佳形状,同时将引线120切断。另外,可以在施加超声波振动的同时使工具130在凸点40的宽度方向上移动,在给定位置上切断引线120。即,在多个凸点40上焊接时,每次可以在一定的位置上切断引线120。为此,引线120中凸出到工具130的外部的部分的长度每次都是一定的,这样,可以使球状的前端部122的直径大小每次都相同。因此,可以稳定连续进行引线120的加工。
这样,如图11以及图12所示,在凸点40上形成引线120的连接部126。如图11所示,使引线120的连接部126比焊接前的引线120的直径要小的情况下扯断。此外,半导体芯片16具有多个凸点40时,反复进行上述各工艺,形成多个引线120。
在上述例中,虽然示出的是用引线120将基板50的电极52(引出脚的一部分)和半导体芯片16的电极12电连接的例子,本实施方案的半导体装置的制造方法,并不限定于上述的例子,例如,也可以适用于用引线120将多个半导体芯片的电极之间电连接的情况。
依据有关本实施方案的半导体装置的制造方法,将引线120的一部分焊接在凸点40中引线120的引出方向的中心位置或者越过中心位置的部分上。这样,例如,可以避免工具130按压引线120中在引线120的引出方向的电极52侧凸出的部分。这样,可以防止引线120垂下。因此,可以在可靠并且稳定的状态下将引线120和凸点40焊接。
进一步,由于凸点40在引线120的引出方向被加宽,并且在引线120的引出方向逐渐降低而倾斜,可以在更可靠并且更稳定的状态下焊接引线120。
然后,说明本实施方案的变形例。如图13A以及图13B所示,在本变形例中,在将引线120的一部分焊接在凸点40上的工艺中,将凸点40的一部分压扁。即,如图13A所示,向凸点40的方向上对工具130的开口端部134加压,使凸点40的一部分塑性变形。在凸点40的平面视图中,凸点40的被压扁的区域与开口端部134接触的区域重叠。凸点40的被压扁的区域也可以就是上述引线120和凸点40的焊接区域。
另外,也可以在使凸点40的一部分压扁而对工具130加压的同时,使工具130在凸点40上凸点40的宽度方向(图13A的箭头所示方向)上移动。工具130的移动方式以及所产生的效果和已经说明的情况相同。
这样,如图13B所示,可以在引线120中与凸点40的连接部126中,将凸点40的一部分压扁。
依据本变形例,可以以凸点40中没有被压扁的部分作为支点将引线120向和半导体芯片16相反的方向(上方)提升。即,可以防止引线120和半导体芯片16接触。
此外,本变形例可以选择适用根据上述制造方法中所说明的内容引导出的任何事项(构成、作用以及效果)。
图14表示适用本实施方案的半导体装置的一例。在图14所示的例中,半导体装置包括多个半导体芯片16、18、具有电极52的基板50、封接部60、外部端子62。此外,有关本实施方案的半导体装置,并不限定于以下的例子。
在基板50上形成布线,布线的一部分成为电极52。多个半导体芯片16、18在基板50上积层。详细讲,半导体芯片18面朝下安装在基板50上,半导体芯片16配置在半导体芯片18上。半导体芯片16使具有电极12的面朝向与半导体芯片18相反侧进行配置,用引线120与基板50进行电连接。详细讲,在半导体芯片16上设置凸点40,用引线120将凸点40与基板50的电极52电连接。用引线120进行连接的方式,如上所述。
封接部60多采用树脂(例如环氧树脂)。然后,在基板50上设置多个外部端子62(例如焊锡球)。外部端子62,电连接在基板50的布线上,例如,通过基板50的过孔(图中未画出)设置在和搭载多个半导体芯片16、18的面相反一侧上。
依据有关本实施方案的半导体装置,可以实现引线120的低环化,并且可以提供电连接可靠性高的装置。
此外,有关本实施方案的半导体装置,可以选择适用根据上述制造方法中所说明的内容引导出的任何事项(构成、作用以及效果)。例如,也可以用其它半导体芯片替代上述基板50,适用本实施方案。
(第3实施方案)
图15A~图20表示有关本实施方案的半导体装置及其制造方法。在本实施方案中,在已经焊接了引线120的凸点40上,进行其它引线220的第1次焊接。
在以下所示的例中,包含在上述实施方案中说明的制造方法。或者也可以在与上述实施方案不同的工艺(例如周知的引线键合工艺)之后,,适用本实施方案的内容。
图15A以及图15B表示引线键合工艺。图16是图15A的部分放大图。图17是图16所示连接结构的平面图,并省略了工具。图18表示与引线的接触部分。
如图15A所示,在上述实施方案中已经说明的图11所示的状态中,进一步准备其它电极112。在图15A所示的例中,多个半导体芯片16、116,使各电解51、12、112露出那样被积层在基板50上。半导体芯片116搭载在半导体芯片16上。这时,多数情况下上侧的半导体芯片116的外形比下侧半导体芯片16的外形小。
如图15A所示,准备支撑引线220的工具230,使引线220的前端部222形成为球状。引线220、工具230以及夹具236的事项,可以适用上述内容。工具230具有孔232以及开口部234。另外,引线220的前端部222形成为球状的方法也和上述相同。
然后,通过工具230的开口端部234将引线220的前端部222焊接在凸点40上。这时,如图16以及图17所示,使前端部222的至少一部分重叠在引线120上进行焊接。这样,可以有效活用凸点40的平面面积。此外,优选在超声波振动的同时进行焊接。
如图16所示,在上述焊接工艺中,通过引线220的前端部222以及工具230,对连接在凸点40上的引线120中没有被压扁的部分不进行压扁。这时,优选使引线220的前端部222以及工具230与引线120中没有被压扁的部分不接触。在此,引线120的没有被压扁的部分是指在将引线120焊接在凸点40上的工艺中没有被压扁的部分。即,引线120被压扁的部分是引线120的连接班126。
如果采用图18所示的例进行说明,在上述焊接工艺中,引线220的前端部222以及工具230与引线120的X处附近没有被压扁的部分(X处的左侧)不接触。此外,图18的X处是指将引线120向凸点40的焊接中没有被压扁的区域的边界点。
这样,这样可以防止已经连接在凸点40撒谎那个的引线120的环形状变形。详细讲,可以防止引线120的环高度降低后与半导体芯片接触,或者引线120在横方向上倒下,或者引线120损伤的情况发生。
或者,引线220的前端部222以及工具230,也可以与图18所示的引线120的Y处附近没有被压扁的部分(Y处的左侧)不接触。图18的Y处是指将引线120的直径(厚度)降低到1/2时的边界点。这样,可以更加可靠地到达上述效果。
或者,引线220的前端部222以及工具230,也可以与图18所示的引线120的Z处附近没有被压扁的部分(Z处的左侧)不接触。图18的Z处是指将引线120的直径(厚度)降低到1/3时的边界点。这样,可以更加可靠地到达上述效果。
如图17所示,也可以将引线220的前端部222的中心(在图7中引线220中从前端部222在孔232内连续的部分)配置在凸点40中越过引线120的引出方向的中心的部分(图17的中心线L的右侧)进行焊接工艺。即,使前端部222的中心偏离引线120向引线40的引出方向。这时,如果凸点40(特别是上端部42)在引线120的引出方向已经被加宽,可以确保凸点40和引线220的连接区域。加宽凸点40的方式,和上述第1以及第2实施方案中说明的方式相同。进一步,如果凸点40在引线120的引出方向逐渐降低而倾斜,容易在凸点40上载置引线220的前端部222。使凸点40倾斜的方式,和上述第1以及第2实施方案中说明的方式相同。这样,可以在可靠并且稳定的状态下将引线220的前端部222焊接在凸点40上。
如图17所示,也可以将整个前端部222配置在凸点40中越过引线120的引出方向的中心的部分(图17的中心线L的右侧),也可以包含凸点40中引线120的引出方向的中心(在图17中与中心线L重叠的部分)进行配置。此外,也可以使引线220的前端部222和凸点40,如图17所示一部分之间重叠进行焊接,或者使整个前端部222与凸点40的一部分重叠进行焊接。
如图15B所示,在上述焊接工艺后,将引线220与电极112电连接。详细讲,预先在电极112上形成凸点140,将引线220向凸点140引出,将引线220的一部分焊接在凸点140上。如果凸点140和凸点40是相同的方式形成,则在向凸点140焊接的工艺中,可以到达在第2实施方案中说明的效果。
依据有关本实施方案的半导体装置的制造方法,通过引线220的前端部222以及工具230,由于不将引线120的没有被压扁的部分压扁进行焊接的工艺,不会出现引线120和凸点40之间的接触不良的情况,可以将新引线220焊接在凸点40上。
此外,有关本实施方案的半导体装置的制造方法,可以选择适用根据上述制造方法中所说明的内容引导出的任何事项(构成、作用以及效果)。
图19表示适用本实施方案的半导体装置的一例。在图19所示的例中,半导体装置包括多个半导体芯片16、116、216、具有电极52的基板50、封接部60、外部端子62。基板50、封接部60以及外部端子62的内容如上所述。此外,有关本实施方案的半导体装置,并不限定于以下的例子。
多个半导体芯片16、116、216在基板50上积层。详细讲,半导体芯片16面朝下安装在基板50上,半导体芯片116配置在半导体芯片16上,半导体芯片216配置在半导体芯片116上。各半导体芯片16、116、216使具有电极的面朝向与基板50相反侧进行配置,用引线与基板50进行电连接。用引线120、220进行连接的方式,如上所述。
依据有关本实施方案的半导体装置,可以实现引线120、220的低环化,并且可以提供电连接可靠性高的装置。
图20表示适用本实施方案的半导体装置的另一例。在图20所示的例中,半导体装置包括多个半导体芯片16、116、316、封接部70、搭载这些的裸片衬垫72、引出脚74。该半导体装置具有QFP(Quad Flat Packag)型的封装结构。
裸片衬垫72在其一面上载置多个半导体芯片16、116、316,其另一面从封接部70中露出。这样可以提高半导体装置的散热性能。封接部70多采用环氧树脂系的树脂。引出脚74包括与封接部70的任一半导体芯片(在图20中的半导体芯片16)电连接的内引出脚76、从封接部70露出到外部的外引出脚78。外引出脚78弯曲成给定形状(在图20中海鸥展翅形状),成为半导体装置的外部端子。如图所示,在外引出脚78上设置焊料等金属皮膜44(例如电镀皮膜)。各半导体芯片16、116、316通过引线120、220相互电连接。用引线进行连接的方式,如上所述。
依据有关本实施方案的半导体装置,可以实现引线120、220的低环化,并且可以提供电连接可靠性高的装置。
图21表示应用本实施方案的电路板。图19所示的半导体装置1被安装在电路板80上。在电路板80上,例如一般采用玻璃环氧树脂基板等有机系基板。在电路板80上形成例如由铜构成的布线图案82,形成所希望的电路,布线图案82与半导体装置的外部端子连接。
作为具有有关本实施方案的半导体装置的电子机器,如图22所示的笔记本型微机1000,图23所示的手机电话2000。
本发明并不限定于上述实施方案,可以进行各种变形。例如,本发明包含和实施方案中所说明的构成实质上相同的构成(例如在功能、方法以及结果上相同的构成,或者在目的以及结果上相同的构成)。另外,本发明包含将实施方案中所说明的构成中非本质性部分进行替换后的构成。另外,本发明包括与实施方案中所说明的构成具有相同作用效果的构成,或者可以达到同一目的的构成。另外,本发明包括在实施方案中所说明的构成中添加了公知技术的构成。
Claims (17)
1.一种半导体装置的制造方法,其特征是包括
通过工具将引线的前端部焊接在第1电极上的引线焊接工序a、
将所述引线从所述第1电极引出到第2电极上的凸点的引线引出工序b、以及
利用所述工具,将所述引线焊接在所述凸点的中心或沿所述引线的从所述第1电极向所述第2电极的引出方向越过所述凸点的中心的部分上的引线焊接工序c,
在所述引线焊接工序c的焊接中,使所述工具一边加压压扁所述引线、一边在所述凸点上沿所述引线的所述引出方向移动。
2.根据权利要求1所述的半导体装置的制造方法,其特征是通过所述引线焊接工序c,不仅将所述引线还将所述凸点压扁。
3.根据权利要求1所述的半导体装置的制造方法,其特征是通过所述引线焊接工序c,使所述凸点变形,并成为在所述引线的所述引出方向细长的状态。
4.根据权利要求1所述的半导体装置的制造方法,其特征是通过所述引线焊接工序c,使所述凸点,沿所述引线的所述引出方向倾斜变低。
5.根据权利要求1~4中任一项所述的半导体装置的制造方法,其特征是在实施所述引线焊接工序c时,同时对所述凸点施加超声波振动。
6.根据权利要求1~4中任一项所述的半导体装置的制造方法,其特征是在所述引线焊接工序a之前,还包括
将在不同于所述引线的引线的第2引线上的形成球状的前端部焊接在所述第2电极上的引线焊接工序e、
将所述第2引线的一部分从焊接后的所述前端部引出的引线引出工序f、
将所述第2引线中与所述前端部连接的部分在所述前端部上压扁后在所述第2电极上形成所述凸点的凸点形成工序g、以及
在所述第2电极上留下所述凸点并将所述第2引线切断的引线切断工序h。
7.根据权利要求6所述的半导体装置的制造方法,其特征是在所述凸点形成工序g中,将所述凸点形成为具有连接在所述第2电极上的下端部、和大致呈平坦面的上端部。
8.根据权利要求7所述的半导体装置的制造方法,其特征是在所述凸点形成工序g中,将所述凸点的所述上端部,形成为在与所述凸点连接的所述引线的所述引出方向上成为细长。
9.根据权利要求7所述的半导体装置的制造方法,其特征是在所述凸点形成工序g中,使所述凸点的所述上端部沿向外的方向倾斜变低。
10.一种半导体装置,其特征是包括
第1电极、
具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的半导体芯片、
具有第1及第2端部,所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在从所述引线的所述第1端部向所述第2端部的引出方向上成为细长,且沿所述引线的所述引出方向逐渐变低,
所述引线的所述第2端部连接在所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分。
11.一种半导体装置,其特征是包括
具有集成电路及第1电极的半导体芯片、
具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的另一半导体芯片、
具有第1及第2端部,所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在从所述引线的所述第1端部向所述第2端部的引出方向成为细长,且沿所述引线的所述引出方向逐渐变低,
所述引线的所述第2端部焊接在所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分。
12.根据权利要求10所述的半导体装置,其特征是所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分被压扁。
13.根据权利要求11所述的半导体装置,其特征是所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分被压扁。
14.一种电路板,其特征是安装了包括
第1电极、
具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的半导体芯片、
具有第1及第2端部,所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在从所述引线的所述第1端部向所述第2端部的引出方向上成为细长,且沿所述引线的所述引出方向逐渐变低,
所述引线的所述第2端部连接在所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分
的半导体装置。
15.一种电路板,其特征是安装了包括
具有集成电路及第1电极的半导体芯片、
具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的另一半导体芯片、
具有第1及第2端部,所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在从所述引线的所述第1端部向所述第2端部的引出方向上成为细长,且沿所述引线的所述引出方向逐渐变低,
所述引线的所述第2端部焊接在所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分的半导体装置。
16.一种电子机器,其特征是具有包括
第1电极、
具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的半导体芯片、
具有第1及第2端部,所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在从所述引线的所述第1端部向所述第2端部的引出方向上成为细长,且沿所述引线的所述引出方向逐渐变低,
所述引线的所述第2端部连接在所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分
的半导体装置。
17.一种电子机器,其特征是具有包括
具有集成电路及第1电极的半导体芯片、
具有集成电路和第2电极、并且具有与所述第2电极相连接的下端部和大致呈平坦面的上端部的凸点的另一半导体芯片、
具有第1及第2端部,所述第1端部与所述第1电极电连接而所述第2端部与所述凸点电连接的引线,
形成的所述凸点的所述上端部,在从所述引线的所述第1端部向所述第2端部的引出方向上成为细长,且沿所述引线引出方向逐渐变低,
所述引线的所述第2端部焊接在所述凸点的中心或沿所述引线的所述引出方向越过所述凸点的中心的部分
的半导体装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002041679A JP3573133B2 (ja) | 2002-02-19 | 2002-02-19 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP200241679 | 2002-02-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1440063A CN1440063A (zh) | 2003-09-03 |
CN1260795C true CN1260795C (zh) | 2006-06-21 |
Family
ID=27678352
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB031037763A Expired - Fee Related CN1260795C (zh) | 2002-02-19 | 2003-02-19 | 半导体装置及其制造方法、电路板以及电子机器 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6921016B2 (zh) |
JP (1) | JP3573133B2 (zh) |
CN (1) | CN1260795C (zh) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3935370B2 (ja) * | 2002-02-19 | 2007-06-20 | セイコーエプソン株式会社 | バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP3584930B2 (ja) * | 2002-02-19 | 2004-11-04 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2005159267A (ja) * | 2003-10-30 | 2005-06-16 | Shinkawa Ltd | 半導体装置及びワイヤボンディング方法 |
JP2005268497A (ja) * | 2004-03-18 | 2005-09-29 | Denso Corp | 半導体装置及び半導体装置の製造方法 |
US7475802B2 (en) * | 2004-04-28 | 2009-01-13 | Texas Instruments Incorporated | Method for low loop wire bonding |
KR100548008B1 (ko) * | 2004-05-20 | 2006-02-01 | 삼성테크윈 주식회사 | 와이어 본딩 기기의 자동 볼 형성방법 |
TWI304238B (en) * | 2004-09-07 | 2008-12-11 | Advanced Semiconductor Eng | Wire-bonding method for connecting wire-bond pads and chip and the structure formed thereby |
US7188759B2 (en) * | 2004-09-08 | 2007-03-13 | Kulicke And Soffa Industries, Inc. | Methods for forming conductive bumps and wire loops |
JP4298665B2 (ja) * | 2005-02-08 | 2009-07-22 | 株式会社新川 | ワイヤボンディング方法 |
JP4558539B2 (ja) * | 2005-03-09 | 2010-10-06 | 日立協和エンジニアリング株式会社 | 電子回路用基板、電子回路、電子回路用基板の製造方法および電子回路の製造方法 |
JP2007019415A (ja) | 2005-07-11 | 2007-01-25 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US20100186991A1 (en) * | 2006-10-18 | 2010-07-29 | Kulicke And Soffa Industries, Inc. | conductive bumps, wire loops including the improved conductive bumps, and methods of forming the same |
US20090020872A1 (en) * | 2007-07-19 | 2009-01-22 | Shinkawa Ltd. | Wire bonding method and semiconductor device |
JP4397408B2 (ja) * | 2007-09-21 | 2010-01-13 | 株式会社新川 | 半導体装置及びワイヤボンディング方法 |
JP4625858B2 (ja) * | 2008-09-10 | 2011-02-02 | 株式会社カイジョー | ワイヤボンディング方法、ワイヤボンディング装置及びワイヤボンディング制御プログラム |
JP2011054727A (ja) * | 2009-09-01 | 2011-03-17 | Oki Semiconductor Co Ltd | 半導体装置、その製造方法、及びワイヤボンディング方法 |
US8759987B2 (en) * | 2009-10-09 | 2014-06-24 | Nichia Corporation | Semiconductor device and method of manufacturing the semiconductor device |
TWI409933B (zh) * | 2010-06-15 | 2013-09-21 | Powertech Technology Inc | 晶片堆疊封裝結構及其製法 |
WO2012092707A1 (en) * | 2011-01-04 | 2012-07-12 | Sandisk Semiconductor (Shanghai) Co., Ltd. | Continuous wire bonding |
KR20130042210A (ko) | 2011-10-18 | 2013-04-26 | 삼성전자주식회사 | 멀티-칩 패키지 및 그의 제조 방법 |
KR20140011687A (ko) * | 2012-07-18 | 2014-01-29 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
WO2014083805A1 (ja) * | 2012-11-28 | 2014-06-05 | パナソニック株式会社 | 半導体装置およびワイヤボンディング配線方法 |
JP2014207430A (ja) | 2013-03-21 | 2014-10-30 | ローム株式会社 | 半導体装置 |
TWI518814B (zh) | 2013-04-15 | 2016-01-21 | 新川股份有限公司 | 半導體裝置以及半導體裝置的製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3643321A (en) * | 1970-06-17 | 1972-02-22 | Kulicke & Soffa Ind Inc | Method and apparatus for tailless wire bonding |
US5111989A (en) * | 1991-09-26 | 1992-05-12 | Kulicke And Soffa Investments, Inc. | Method of making low profile fine wire interconnections |
JP3344235B2 (ja) | 1996-10-07 | 2002-11-11 | 株式会社デンソー | ワイヤボンディング方法 |
IT1305646B1 (it) * | 1998-08-07 | 2001-05-15 | St Microelectronics Srl | Formazione di globuli d'oro saldati su piazzuole di collegamento esuccessiva coniatura della loro sommita' |
JP3765952B2 (ja) * | 1999-10-19 | 2006-04-12 | 富士通株式会社 | 半導体装置 |
US6244499B1 (en) * | 1999-12-13 | 2001-06-12 | Advanced Semiconductor Engineering, Inc. | Structure of a ball bump for wire bonding and the formation thereof |
JP2001284388A (ja) | 2000-03-30 | 2001-10-12 | Murata Mfg Co Ltd | ワイヤボンディング方法 |
JP3570551B2 (ja) | 2001-03-16 | 2004-09-29 | 株式会社カイジョー | ワイヤボンディング方法 |
-
2002
- 2002-02-19 JP JP2002041679A patent/JP3573133B2/ja not_active Expired - Fee Related
-
2003
- 2003-01-21 US US10/347,297 patent/US6921016B2/en not_active Expired - Lifetime
- 2003-02-19 CN CNB031037763A patent/CN1260795C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6921016B2 (en) | 2005-07-26 |
JP3573133B2 (ja) | 2004-10-06 |
JP2003243441A (ja) | 2003-08-29 |
US20030155405A1 (en) | 2003-08-21 |
CN1440063A (zh) | 2003-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1280884C (zh) | 半导体装置及其制造方法、电路板以及电子机器 | |
CN1260795C (zh) | 半导体装置及其制造方法、电路板以及电子机器 | |
CN1267978C (zh) | 凸点的形成方法、半导体元件与半导体装置及其制造方法、电路板以及电子机器 | |
CN1161834C (zh) | 半导体器件及其制造方法 | |
CN1132244C (zh) | 树脂封装型半导体装置及其制造方法 | |
CN1206719C (zh) | 接触器、其制造方法、探针板. 及半导体器件测试插座 | |
CN1324701C (zh) | 具有窄间距化的内引线的半导体装置 | |
CN1244139C (zh) | 半导体器件和半导体组件 | |
CN1649098A (zh) | 半导体器件 | |
CN1107349C (zh) | 一种半导体器件引线框架及引线接合法 | |
CN1303677C (zh) | 电路基板、带凸块的半导体元件的安装结构和电光装置 | |
CN1190844C (zh) | 光照射装置的制造方法 | |
CN1424757A (zh) | 半导体器件及其制造方法 | |
CN1441489A (zh) | 半导体装置及其制造方法、电路板和电子仪器 | |
CN1460293A (zh) | 散热型bga封装及其制造方法 | |
CN1441472A (zh) | 半导体装置及其制造方法、电路板和电子仪器 | |
CN1430253A (zh) | 焊接方法以及焊接装置 | |
CN1641873A (zh) | 多芯片封装、其中使用的半导体器件及其制造方法 | |
CN1581474A (zh) | 无引线型半导体封装及其制造方法 | |
CN1207585A (zh) | 半导体装置及半导体装置的引线框架 | |
CN1368760A (zh) | 半导体设备 | |
CN1512574A (zh) | 半导体器件及其制造方法 | |
CN1779951A (zh) | 半导体器件及其制造方法 | |
CN1574346A (zh) | 一种制造半导体器件的方法 | |
CN101076884A (zh) | 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060621 Termination date: 20170219 |
|
CF01 | Termination of patent right due to non-payment of annual fee |