CN118213350A - 用于互连的扩散阻挡衬层 - Google Patents

用于互连的扩散阻挡衬层 Download PDF

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Publication number
CN118213350A
CN118213350A CN202410366205.5A CN202410366205A CN118213350A CN 118213350 A CN118213350 A CN 118213350A CN 202410366205 A CN202410366205 A CN 202410366205A CN 118213350 A CN118213350 A CN 118213350A
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China
Prior art keywords
substrate
conductive
interface
bonding
conductive interconnect
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CN202410366205.5A
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English (en)
Inventor
R·坎卡尔
C·E·尤佐
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Insulation Semiconductor Bonding Technology Co
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Insulation Semiconductor Bonding Technology Co
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Publication of CN118213350A publication Critical patent/CN118213350A/zh
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Abstract

本公开涉及一种用于互连的扩散阻挡衬层。技术和装置的代表性实施方式用于减少或防止导电材料扩散到结合衬底的绝缘材料或电介质材料中。由于重叠，错位的导电结构可以直接接触衬底的电介质部分，尤其是在采用直接结合技术的情况下。通常在重叠处将可以抑制扩散的阻挡界面设置在导电材料和电介质之间。

Description

用于互连的扩散阻挡衬层
分案说明
本申请是于2018年10月01日提交的申请号为201880055006.5、名称为“用于互连的扩散阻挡衬层”的中国发明专利申请的分案申请。
优先权要求和相关申请的交叉引用
本申请根据35U.S.C.§119(e)(1)要求2018年9月27日提交的美国非临时专利申请号16/143,850和2017年10月6日提交的美国临时申请号62/569,232的权益，这些申请通过引用整体并入本文。
技术领域
以下描述涉及集成电路(“IC”)的加工。更具体地说，以下描述涉及用于加工准备结合的管芯或晶圆的技术。
背景技术
管芯或晶圆等可以作为各种微电子封装方案的一部分以三维布置堆叠。这可以包括在较大的基础管芯或晶圆上堆叠一个或多个管芯或晶圆、以竖直布置堆叠多个管芯或晶圆以及这些的各种组合。管芯也可以堆叠在晶圆上，或者晶圆可以在分割之前堆叠在其他晶圆上。管芯或晶圆可以使用各种结合技术以堆叠布置来结合，包括使用直接电介质结合、非粘合技术，诸如直接结合技术或/>混合结合技术，这两种技术均可从XperiCorp的子公司Invensas Bonding Technologies,Inc.(以前的Ziptronix,Inc.)获得(例如，参见美国专利号6,864,585和7,485,968，其以引用方式全文并入本文中)。
当使用直接结合技术结合堆叠的管芯或晶圆时，期望的是待结合管芯或晶圆的表面极其平坦和光滑。例如，表面应具有非常小的表面拓扑变化，使得表面可以紧密配合，以形成持久的键合。还希望表面清洁并且没有杂质、颗粒和/或其他残留物。例如，不期望的颗粒的存在可导致在颗粒的位置处键合有缺陷或不可靠。例如，残留在键合表面上的一些颗粒和残留物可在堆叠管芯之间的键合界面处产生空隙。
结合的管芯或晶圆的相应配合表面通常包括嵌入的导电互连结构等。在一些示例中，结合表面被布置和对齐成使得在结合期间接合来自各个表面的导电互连结构。接合的互连结构在堆叠的管芯或晶圆之间形成连续的导电互连(用于信号，功率等)。然而，由于使用精细间距的导电互连结构、拾取和放置工具的放置精度限制、管芯或晶圆表面上的接触栅格图案、不同的焊盘尺寸等，一个管芯或晶圆的导电互连焊盘可能偏移，或者部分覆盖另一管芯或晶圆的配合表面的电介质部分(例如，氧化硅等)的，而不是与另一管芯或晶圆的配合表面上的相应导电互连焊盘完全对准。
诸如此类的错位可能导致覆盖的互连焊盘的导电材料(例如，铜等)扩散到其与之接触的电介质中，从而潜在地导致微电子结构的劣化的性能。例如，在较高温度(诸如在退火期间)和电场内，氧化硅的阻挡特性可能显著劣化(相对于氮化硅、氧氮化硅、碳氮化硅等)，从而促进导电材料扩散到氧化硅中。这可导致互连器之间的泄漏、短路等。当其涉及管芯或晶圆的结合叠堆的多个导电互连结构时，性能劣化可能是特别有问题的，这会不利地影响封装产率和封装性能。
附图说明
参考附图阐述了详细描述。在这些图中，参考标号的一个或多个最左边的数字标识首次出现参考标号的图。在不同图中使用相同的附图标记表示相似或相同的项目。
对于该讨论，图中所示的装置和系统被示出为具有多个部件。如本文所述，装置和/或系统的各种实施方式可以包括较少的部件并且仍然在本公开的范围内。另选地，装置和/或系统的其他实施方式可以包括附加部件或所描述部件的各种组合，并且仍然在本公开的范围内。
图1为一对堆叠的衬底的轮廓图，示出了堆叠的衬底内的嵌入式导电结构的错位。
图2是示出形成微电子组件的示例过程的图形流程图，该微电子组件包括具有嵌入式导电结构的一对衬底。
图3A和图3B是示出根据各种实施方案的与具有嵌入式导电结构的堆叠衬底一起使用的示例阻挡界面的轮廓图。
图4A至图4E是示出根据附加实施方案的与具有嵌入式导电结构的堆叠衬底一起使用的示例阻挡界面的轮廓图。
图4F为示出根据实施方案的具有多个嵌入式导电结构的示例阻挡界面的平面图。
图5A至图5C是示出根据附加实施方案的与具有嵌入式导电结构的堆叠衬底一起使用的示例阻挡界面的轮廓图。
图6是示出根据实施方案的形成微电子组件的示例过程的图形流程图，该微电子组件包括带有阻挡界面的具有嵌入式导电结构的一对衬底。
图7是示出根据另一实施方案的形成微电子组件的示例过程的图形流程图，该微电子组件包括带有阻挡界面的具有嵌入式导电结构的一对衬底。
图8是示出根据各种实施方案的用于形成微电子组件的示例方法的流程图，该微电子组件包括具有嵌入式导电结构和阻挡界面的一对衬底。
发明内容
装置和技术的各种实施方案减少或防止导电材料扩散到结合衬底的绝缘材料或电介质中。特别地，本文所公开的装置和技术减轻了由于衬底的结合表面上的错位的导电结构造成的不期望的扩散。由于重叠，错位的导电结构可以以其他方式直接接触衬底表面的电介质部分，尤其是在采用直接结合技术的情况下。
这些装置和技术包括使用通常设置在导电材料和电介质之间的阻挡界面，该阻挡界面可以抑制导电层扩散到周围的电介质材料中。
衬底可以是由半导体或非半导体材料构成的管芯、晶圆、载体、大平面板等。半导体材料可以例如包括直接带隙半导体或间接带隙半导体及其组合。非半导体材料可以包括例如电介质材料，例如玻璃、陶瓷、碳氧化硅、氧化硅等，或者它们的组合。本文术语“衬底”的使用旨在包括所有这些和其他类似的示例。
在实施方案中，微电子组件可以至少包括具有第一基本平坦表面的第一衬底，第一衬底包括例如绝缘材料或电介质。电介质可以被设置在半导体、绝缘材料或导电材料的基础管芯或晶圆上。第二衬底具有第一基本平坦的表面，第二衬底也包括例如绝缘材料或电介质。电介质可以被设置在半导体、绝缘材料或导电材料的基础管芯或晶圆上。第一衬底的材料可以是第二衬底的相同(或类似)材料。然而，在另选的实施方案中，第一衬底的材料为与第二衬底的材料不同的材料。第二衬底的第一表面被结合到第一衬底的第一表面，而没有诸如粘合剂的中间材料。
第一导电互连结构嵌入在第一衬底中(或在第一衬底的层中)，第一导电互连结构的表面通过第一衬底的第一表面暴露，以形成第一互连焊盘。第二导电互连结构嵌入在第二衬底中(或在第二衬底的层中)，第二导电互连结构的表面通过第二衬底的第一表面暴露，以形成第二互连焊盘。第一互连焊盘面向并且可以接触第一衬底的第一表面的一部分并且第二互连焊盘面向并且可以接触第二衬底的第一表面的一部分。在一个实施方式中，第二互连焊盘直接结合到第一互连焊盘。
在各种示例中，第二互连焊盘可能相对于第一互连焊盘错位，导致第一和/或第二互连焊盘在相对衬底的绝缘材料或电介质上的一些重叠。
在该实施方案中，第一阻挡界面设置在第一衬底上，并且至少部分地围绕第一互连焊盘的周边。第一阻挡界面包括不同于第一衬底的绝缘材料或电介质的材料，并且被布置成抑制第二导电互连结构的材料扩散到第一衬底中。在该实施方案中，第一阻挡界面的材料也是与第二导电互连结构的材料不同的材料。在一个实施方式中，第一阻挡界面包括气隙、粗糙表面等。
在另一实施方案中，微电子组件还包括设置在第二衬底上的第二阻挡界面。第二阻挡界面至少部分地围绕第二互连焊盘的周边，并且包括与第二衬底的绝缘材料或电介质不同的材料。第二阻挡界面被布置用于抑制第一导电互连结构的材料扩散到第二衬底中。在一个实施方式中，第二阻挡界面包括气隙、粗糙表面等。
在一些实施方案中，第一阻挡界面和/或第二阻挡界面可以包括多种材料或者可以包括由一种或多种材料构成的多个部分。在其他实施方案中，第一阻挡界和/或第二阻挡界面可以包括材料、气隙、粗糙表面等的组合。
在各种实施方案中，第一阻挡界面或第二阻挡界面可以部分地或完全围绕其相应衬底的多个互连焊盘。另选地，多个阻挡界面可以部分地或完全围绕第一衬底或第二衬底的一个或多个互连焊盘。
在一些实施方案中，第一阻挡界面或第二阻挡界面也可以减轻或防止在平坦化期间可能在导电互连结构的周边处发生的电介质侵蚀(例如，圆角化)等。
一些公开的过程可以使用方框流程图来示出，包括图形流程图和/或文本流程图。描述所公开的过程的顺序不旨在被解释为限制，并且可以以任何顺序组合任何数量的所描述的过程框以实现该过程或另选过程。另外，在不脱离本文描述的主题的实质和范围的情况下，可以从这些过程中删除各个框。此外，在不脱离本文描述的主题的范围的情况下，所公开的过程可以在任何合适的制造或加工设备或系统中连同任何硬件、软件、固件或它们的组合一起实现。
下面使用多个示例更详细地解释实施方式。尽管在此处和下文讨论了各种实施方式和示例，但是通过组合各个实施方式和示例的特征和元素，其他实施方式和示例也是可能的。
具体实施方式
概述
图1为一对堆叠衬底102和104的轮廓图，分别示出了堆叠的衬底102和104内的嵌入式导电结构106和嵌入式导电结构108的错位。衬底102和衬底104至少在每个衬底102和104的结合表面上由绝缘材料或电介质(例如，氧化硅等)构成。例如，衬底102和衬底104可以表示微电子组件的由(有源半导体，例如硅等的)基础层构成的顶部绝缘层，该基础层的顶部具有在相关联的绝缘层内的一个或多个金属化层。在一些情况下，衬底102可以显著地大于衬底104。在一个示例中，衬底104可以包括宽度在1至30mm或甚至更大的管芯，而衬底102可以包括比衬底104更大的另一管芯(例如)，较大的衬底诸如平坦的面板，200或300mm的晶圆等。
在结合之前，通过衬底102和104的结合表面暴露的嵌入式导电结构106和嵌入式导电结构108的部分可以形成互连焊盘等。在示例中，衬底102和衬底104在相应的结合表面上结合，并且导电结构106和导电结构108是电耦合的，并且一般也被机械结合以形成单个(连续)导电结构。结合线110指示衬底102和衬底104的结合表面接合的地方。
在示例中，结合衬底102和衬底104形成微电子组件100。例如，衬底102和衬底104可以被直接结合，包括使用混合结合技术，而不使用诸如粘合剂的中间材料。在结合之前，导电结构106和导电结构108可以稍微凹入到衬底102和衬底104的表面下方，以准备金属膨胀。衬底102和衬底104的表面经由直接结合(例如，经由ZibondTM)、电介质到电介质地在室温下结合而不使用粘合剂。然后利用高温退火(<350C)，接触焊盘106和接触焊盘108膨胀并形成金属与金属的结合，从而产生电连接。在结合操作之后，例如当衬底102和衬底104包括晶圆时，可以在分段之前针对对已知良好的晶粒测试结合的组件100，以分离成各种结合的衬底或管芯。
如图1所示，由于以上讨论的各种原因中的一个或多个(包括用于将衬底104结合到衬底102的拾取和放置工具的不准确性(或公差))，当衬底102和衬底104被放置在一起并结合时，导电结构106和导电结构108可能错位。错位的偏移112包括互连焊盘106超出互连焊盘108的周边或边缘的重叠以及/或者互连焊盘108超出互连焊盘106的周边或边缘的重叠。由于偏移112，导电结构106和导电结构108中的一者或两者的一部分可以分别接触衬底104和衬底102的绝缘材料。如上所讨论的那样，由于这种接触，导电结构106和导电结构108中的一者或两者的导电材料(例如，铜或铜合金等)可能扩散到衬底104和衬底102的绝缘材料或电介质中。附加地，一些工艺元素(例如诸如高温退火)或操作参数(例如高频电场等)可能加剧导电材料扩散到衬底104和衬底102的绝缘材料或电介质中，从而导致例如电介质层中不期望的渗漏。
图2是示出根据实施方案的形成微电子组件100的示例性方法200的图形流程图，该微电子组件包括具有嵌入式导电结构106和嵌入式导电结构108的一对衬底102和104。在示例中，镶嵌结构由衬底102形成。在方框(A)处，将导电材料202(例如，铜、铜合金、镍或镍承载导体等)沉积在衬底102的表面上，包括沉积到镶嵌腔中，填充空腔。在方框(B)处，导电材料202被平坦化(例如，经由化学机械抛光(CMP)、蚀刻等)以形成导电结构106。导电结构106的暴露部分可以包括互连焊盘204。在一个实施方案中，可优选的是，互连焊盘204可以稍微凹入到衬底102的结合表面下方。通过清洁方法来制备结合表面，以去除导致不期望的颗粒的缺陷、残余的有机材料等。可以通过将表面中的一个或多个暴露于氮等离子体来制备(一个或多个)清洁表面，以准备用于结合过程。
在方框(C)处，由另一衬底104形成类似的镶嵌结构，该另一衬底在平坦化之后包括导电结构108。导电结构108的暴露部分可以包括互连焊盘206。将衬底104的制备的结合表面放置在衬底102上并堆叠到该衬底上以准备用于结合。然后将组装的衬底102和衬底104在低于350℃并且优选地低于250℃的温度下热处理持续足够的时间，以便于使结合表面永久结合，并且使相对的导电材料以机械和电的方式两者耦合。
方框(D)、(E)和(F)示出了将衬底102结合到衬底104的三个潜在结果。方框(D)表示理想的场景，其中导电结构106和导电结构108良好地对齐，而没有偏移。方框(E)表示平均场景，其中基于用于将衬底104结合到衬底102的放置工具的平均不准确性(例如，公差)，存在导电结构106和导电结构108的平均错位。框(F)表示极端场景，其中基于用于将衬底104结合到衬底102的放置工具的最大不准确性(例如，公差)，存在导电结构106和导电结构108的极端错位。通常，拾取和放置工具的放置速度越高，其放置精度越低，即偏移越大。对于具有极小的互连焊盘尺寸的应用，放置工具可以显著地减速以提高放置精度，这会影响吞吐量。
如上所述，偏移112(在方框(E)和(F)处示出)提供了将导电结构106和导电结构108的导电材料分别扩散到衬底104和衬底102的绝缘材料或电介质中的机会。
示例阻挡界面
根据本公开，为了避免铜扩散到氧化物中，例如，可以围绕互连焊盘106和/或互连焊盘108施加包括电介质结合层、导电阻挡层或其他阻挡物的阻挡界面302以形成防扩散的阻挡物。选择阻挡界面302材料，使得与衬底104和衬底102的绝缘材料或电介质(例如，氧化硅)相比，导电结构106和导电结构108的导电材料(例如，铜)到阻挡材料中的扩散率更差。在各种实施方案中，阻挡材料可以包括具有预选扩散特性的导电或非导电材料。
图3A和图3B是示出根据各种实施方案的与具有嵌入式导电结构106和嵌入式导电结构108的堆叠衬底102和堆叠衬底104一起使用的阻挡界面302的示例的轮廓图。在实施方式中，衬底102和衬底104在没有中间材料(诸如粘合剂)的情况下直接结合，以形成微电子组件300。在实施方式中，微电子组件300包括如上所讨论的微电子组件100，并且包括衬底102和衬底104中的一者或两者上的一个或多个阻挡界面302。在另选的实施方式中，微电子组件300包括呈结合叠堆的多于两个的衬底(诸如衬底102和衬底104)，其中叠堆的衬底中的一个或多个包括一个或多个阻挡界面302。在另一实施方式中，微电子组件300包括分离地结合到另一衬底或晶圆的两个或更多个衬底(诸如衬底102和衬底104)，其中衬底中的两个或更多个包括一个或多个阻挡界面302。
在实施方式中，组件300的(多个)阻挡界面302设置在衬底102和衬底104中的一者或两者处，并且分别至少部分地围绕互连焊盘204和/或互连焊盘206、以及/或者嵌入式导电结构106和嵌入式导电结构108的周边。如图3A所示，(多个)阻挡界面302可以包括与衬底102和/或衬底104的绝缘材料或电介质不同的一种或多种材料。例如，(多个)阻挡界面302可以包括与衬底102和/或衬底104的绝缘材料或电介质不同的电介质材料。在各种实施方式中，(多个)阻挡界面302包括氮化硅、氧氮化硅、碳化硅、碳氮化硅、金刚石、掺杂硼玻璃或氧化物、氧化铝或类似的阻扩散材料中的一种或多种。在其他实施方式中，(多个)阻挡界面302包括镍、镍合金、或各种组合的一种或多种其它导电材料。
附加地，采用阻挡界面302可以包括通过避免在相关结合界面处进行结合来防止扩散的技术。例如，在各种实施方案中，可以结合相应的导电互连结构106和导电互连结构108，但很少或不结合直接围绕的绝缘材料或电介质。如图3B所示，(多个)阻挡界面302中的一个或多个可以包括凹部、气隙、或气体填充的空腔等。同样，(多个)阻挡界面302包括与衬底102和/或衬底104的绝缘材料或电介质不同的材料。在各种实施方式中，(多个)阻挡界面302包括惰性气体或流体、预选气体或流体(基于所期望的特性)、真空等。气隙阻挡界面302可以通过蚀刻、在衬底102和/或衬底104中制造底切、经由CMP对衬底102和/或104进行凹陷化、研磨、衬底附近的衬底圆角化以及CMP期间的互连焊盘界面等来形成。
参见图3A和图3B，在实施方式中，(多个)阻挡界面302被布置成抑制导电互连结构106和导电互连结构108的材料分别扩散到衬底104和衬底102中。例如，选择(多个)阻挡界面302的材料，使得导电互连结构106的材料进入衬底104或衬底102的(多个)阻挡界面302的扩散率或导电互连结构108的材料进入衬底104或衬底102的(多个)阻挡界面302的材料的扩散率小于导电互连结构106或导电互连结构108的材料进入衬底104或衬底102的材料的扩散率(例如，氧化硅)。
在各种实施方案中，阻挡界面302中的一个或多个可以被布置成完全围绕或包围导电结构106和/或导电结构108以及/或者它们各自的互连焊盘204和/或互连焊盘206(即，分别为导电结构106和导电结构108的配合表面)，或者部分围绕导电结构106和/或导电结构108以及/或者它们各自的互连焊盘204和/或互连焊盘206，形成阻挡导电材料(例如，铜)扩散到衬底102和衬底104的材料(氧化硅)中的阻挡物。
如图3A和图3B所示，在各种实施方案中，阻挡界面302具有大于拾取和放置工具的放置精度306(也由图1中的重叠112表示)的厚度304(即，宽度、范围等)。在最大放置错位的情况下，阻挡界面302的该厚度确保导电结构106和导电结构108的材料将接触阻挡界面302而不是衬底104或衬底102。这确保任何导电材料重叠发生在阻挡界面302处，而不是在衬底材料(例如，氧化硅)处，从而防止扩散。附加地，这显著地放松了拾取和放置工具的放置精度要求，这可改善吞吐量，尤其是在管芯至管芯和管芯到晶圆的结合过程中。
因此，在一个实施方案中，(导电结构106的)一个互连焊盘204与(导电结构108的)另一互连焊盘206的相对侧向位移小于阻挡界面302中的一个或多个的宽度。进一步，在一个实施方式中，阻挡界面302中的一个或多个的宽度是导电结构106和/或导电结构108的互连焊盘204和/或206的直径的至少10％。在其他实施方式中，阻挡界面中的一个或多个的宽度为互连焊盘204和/或互连焊盘206的直径的至少20％。
如图3B所示，在一些实施方案中，焊盘204的至少一些部分在结合之后延伸或突出超过微电子组件300上的衬底102的绝缘材料的凹入表面，并且可以延伸超过结合线110。这种延伸可能是形成阻挡界面302的结果，它也可能是由于平坦化在焊盘204的周边周围的衬底102的表面上的电介质侵蚀(即，圆角化)的结果，或是以上两者，或者分离地或组合是其他原因的结果。接合之后焊盘206的经过衬底104的凹入表面的至少一些部分的类似延伸或突出，以及可能地经过结合线110的延伸也可以存在于实施方案中。
在任何情况下，焊盘204和/或焊盘206的延伸的结果是至少部分地围绕焊盘204和/或焊盘206的气隙(有意的或以其他方式)。在一些情况下，当互连焊盘204和互连焊盘206错位时(如图3B所示)，在一些实施方案中，可仅存在焊盘204或焊盘206的通过结合线110的至少一些部分的部分延伸或突起。
在图3A中，(导电结构106的)一个互连焊盘204与(导电结构108的)另一互连焊盘206的相对侧向位移小于阻挡界面302中的一个或多个的宽度。在退火期间，在导电焊盘204/206膨胀超过衬底材料102/104和阻挡界面材料302时，热膨胀系数之间的这种高失配可能在焊盘204/206推动阻挡界面302的位置处诱导衬底102的部分从衬底104脱粘。在实施方式中，可以通过调节退火时间和温度来减轻(例如，减少或消除)脱粘。在实施方式中，结合表面可在约100-150℃下热处理持续2至4小时以在衬底102和衬底104之间形成强结合。焊盘204和焊盘206然后可以在第二热处理期间使用脉冲退火技术在大约250-400℃下退火持续10秒至小于300秒。在示例中，第二热处理的脉冲退火时间小于第一热处理的加热时间的10％。在实施方式中，调节的加热/退火时间对于降低或消除结合的微电子组件300的失配应力或负载是有效的。
虽然图3A和图3B示出延伸穿过衬底102和衬底104的导电结构，但是这些结构可以部分延伸穿过衬底或者衬底上的层。为了简单起见，并且为了集中在结合界面处的结构或结构的部分上，在图3至图7中没有示出衬底上、衬底中或穿过衬底的导电连接的具体细节。
图4A至图4E是示出根据附加实施方案的与具有嵌入式导电结构106和嵌入式导电结构108的堆叠衬底102和堆叠衬底104一起使用的附加示例阻挡界面302的轮廓图。如图3A和图4A所示，阻挡界面302可以嵌入到衬底102和/或衬底104中的一者或多者中。在实施方案中，如图3A和图4A所示，一个或多个阻挡界面302嵌入衬底102和/或衬底104中，并延伸到衬底102和/或衬底104中至小于或等于导电结构106或导电结构108的深度的深度。在该构型中，衬底102和衬底104受到保护而不受导电材料扩散的影响。在实施方案中，如图3A和图4A所示，阻挡界面302可以被设置(并且可以暴露)在衬底102和/或衬底104的结合表面上，并且可以将预定深度延伸到衬底102和/或衬底104中。
如图4B所示，当导电结构106和导电结构108为相异的尺寸时，可以在衬底102或衬底104之一上使用阻挡界面302。例如，阻挡界面302(处于有利的厚度)可以用在导电结构106和导电结构108中的较小者上，以防止从导电结构106和导电结构108中的较大者扩散，而没有暴露在衬底102或衬底104上的重叠。例如，在实施方案中，第一互连焊盘106的宽度小于第二互连焊盘108的宽度，并且阻挡界面302被设置在第一衬底102处，至少部分地围绕第一互连焊盘106的周边。阻挡界面302的厚度/宽度使得第一互连焊盘106和阻挡界面302的组合宽度大于第二互连焊盘108的宽度。换句话讲，与实施方案中的每一个一样，第二互连焊盘108的周边边缘中的至少一个在阻挡界面302的周边内。第二互连焊盘108的另一周边边缘也在阻挡界面302的周边内或第一互连焊盘106的周边内(防止扩散到衬底材料中)。
如图4C所示，嵌入式阻挡界面302可以或可以不暴露在衬底102和衬底104的结合表面上。阻挡界面302可以被设置在结合表面下方的预选距离，并且可以具有各种深度和厚度(即，宽度或范围)。例如，在一个实施方案中，阻挡界面302可以在衬底102或衬底104的整个宽度上延伸。阻挡界面302可以邻接导电结构106和/或导电结构108，并且扩散可以限于阻挡界面302上方的衬底102和衬底104的区域，阻挡界面302防止阻挡界面302下方的扩散。在一些实施方案中，此类阻挡界面302可以由聚合物层或具有所期望的扩散特性的类似材料构成。
如图4D所示，阻挡界面302可以包括衬底102和/或衬底104的结合表面的粗糙区域，其可在衬底102和衬底104之间的结合中以预定宽度包括一个或多个间隙。例如，通常在衬底102和衬底104两者上制备在拓扑方面具有低方差的高度平坦的结合表面，以便在衬底102和衬底104之间具有可靠的直接结合。然而，在实施方案中，部分或全部围绕导电结构106和/或导电结构108的衬底102和/或衬底104的表面区域可以具有更高的粗糙度(表面拓扑方面具有更大的变化)，以在衬底102和衬底104之间产生不平坦或不规则的表面，从而减少或消除衬底102和衬底104的该区域处的结合。例如，粗糙度可以使得表面不够光滑(或留下不足够的表面接触)以形成结合。高粗糙度(例如，大于10nm的变化)阻挡界面302可以利用蚀刻、切割、研磨、选择性CMP等形成。
类似于参照图4B描述的实施方案，如图4E所示，当导电结构106和108是不同尺寸时，阻挡界面302可以用在衬底102和衬底104之一上。在图4E的情况下，阻挡界面302包括与导电结构106和导电结构108中的较小者一起使用的气隙(或流体填充间隙)。当阻挡界面302的尺寸被有利地确定时，导电材料与衬底102或衬底104上没有重叠，并且因此没有扩散。例如，气隙阻挡界面302的尺寸被确定成使得互连焊盘204和互连焊盘206之间的任何偏移(有效地为互连焊盘204和互连焊盘206的边缘)落在阻挡界面302内，而不落在衬底102和衬底104的材料处。
在实施方式中，一个或多个阻挡界面302包括包含以下两者或多者的组合：多个气隙，与衬底102和衬底104的绝缘或电介质材料不同的一种或多种材料，以及预定宽度的粗糙表面。
如图4F的平面图所示，在实施方案中，多个导电结构106(或互连焊盘204)可以被单个阻挡界面302部分或全部围绕或包围。在此类实施方案中，衬底102可以被结合到具有多个导电结构108的另一衬底104，或具有导电结构的多于一个衬底。
另选地，多个阻挡界面302可以部分或完全围绕一个或多个导电结构106、导电结构108、或衬底102和衬底104中的一个或多个的互连焊盘204、互连焊盘206。例如，如图5A至图5C所示，多个导电结构106和导电结构108被阻挡界面302部分或全部围绕。例如，在实施方案中，多个附加的导电互连结构106嵌入在衬底102中，其中附加的导电互连结构106中的每一个的表面通过衬底102的结合表面暴露，以形成多个附加的互连焊盘204。多个附加的导电互连结构108嵌入在相对的衬底104中，并且附加的导电互连结构108中的每一个的表面通过衬底104的结合表面暴露，以形成多个附加的互连焊盘206。
阻挡界面302至少部分地围绕包括第一互连焊盘106和多个附加互连焊盘106的焊盘组的至少一个子集。基于阻挡界面302的位置和组成，阻挡界面302被布置成抑制包括导电互连结构108和多个附加导电互连结构108的互连结构组的导电材料扩散到衬底102中。进一步，(多个)阻挡界面302可被布置成抑制包括导电互连结构106和多个附加导电互连结构106的互连结构组的导电材料扩散到衬底104中。
如图5A和图5C所示，多个导电结构106和108中的每一个都可以包括阻挡界面302。例如，在实施方案中，一个或多个附加阻挡界面302设置在衬底102和/或衬底104处，这些界面至少部分地围绕第一互连焊盘106和多个附加互连焊盘106、和/或第二互连焊盘108和多个附加互连焊盘108的一个或多个附加子集的周边。一个或多个附加阻挡界面302包括不同于衬底102和/或衬底104的绝缘材料或电介质的材料，并且基于阻挡界面302的位置和组成被布置成抑制包括导电互连结构108和多个附加导电互连结构108的互连结构组的材料扩散到衬底102的材料中。进一步，一个或多个附加阻挡界面302可以被布置成抑制包括导电互连结构106和多个附加导电互连结构106的互连结构组的材料扩散到衬底104的材料中。
参考图5A至图5C，在一些实施方案中，每个阻挡界面302之间可以是间隙502，该间隙可以是阻挡界面302之间的空间、填充气体的间隙等。间隙502在衬底102和衬底104的结合表面之间(至少围绕导电结构106和/或导电结构108的周边)形成物理分离。在一些实施方案中，阻挡界面302和(多个)间隙502的组合防止或减少导电结构106和/或导电结构108的导电材料以及它们各自的互连焊盘204和互连焊盘206扩散到衬底104和衬底102的材料中。在另一实施方案中，在衬底102和104的结合表面之间不形成此类间隙502。
另选地，如图5B所示，单个导电结构106和/或导电结构108以及两个或多个导电结构106和/或导电结构108的组可以被单个阻挡界面302部分或全部围绕。在阻挡界面302之间，可以存在或可以不存在间隙502，如上所述。通孔(例如，TSV)(诸如通孔504)可以存在于本文所讨论的任何实施方案中，包括图5B处示出的示例性实施方案。通孔504可以延伸到衬底102和衬底104中的一个或两个的外部范围(例如，暴露的表面)(以及延伸超出其)，或者它可以使一些部分延伸穿过衬底102和/或衬底104。
示例性方法
图6是示出根据实施方案的形成微电子组件300的示例性方法600的图形流程图，该微电子组件包括具有嵌入式导电结构106和嵌入式导电结构108以及一个或多个阻挡界面302的一对衬底102和104。
在方框A处，方法包括在衬底102的表面中形成空腔602(或多个空腔602和空腔603)。空腔602和空腔603可以通过图案化蚀刻等形成。在实施方案中，空腔603中的一个可以延伸至小于另一空腔602的深度的5％的深度。在方框B处，阻挡层604形成在衬底102的表面上和空腔602内。阻挡层604可以例如由氮化硅、氮氧化硅、碳化硅、碳氮化硅、金刚石、掺硼玻璃或氧化物、氧化铝或扩散性比氧化硅差的其他合适材料或它们的组合构成。在其他实施方案中，阻挡层604可以包括导电材料，例如钛或钽或它们对应的氮化物、镍和镍合金、或其他导电材料和组合。
在方框C处，涂覆有阻挡层604的空腔602填充有导电材料202，诸如铜、铜合金等。这可以例如使用双镶嵌工艺来完成。在一些示例中，可能期望的是导电结构106在衬底102而不是阻挡层604处接触空腔602的底部。在这些示例中，可以在用导电材料202填充空腔602之前，从空腔602的底部部分(和/或任何其它所期望的部分)移除阻挡层604的部分，以暴露衬底102。
在方框D处，通过蚀刻、CMP等(在阻挡层604处停止)去除溢出的导电材料202，以在阻挡层604内形成导电结构106(或多个导电结构106)。在方框E处，导电结构106和阻挡层604的一部分经由例如CMP被平坦化，以形成部分或完全围绕互连焊盘204的阻挡界面302(该互连焊盘可以具有非常小的凹部)以及衬底102的基本平坦的表面(具有带有不超过10-20nm的变化的平滑表面形貌)。
在一些实施方案中，阻挡层604或阻挡界面302可用于防止或减轻平坦化期间可能发生的衬底102的绝缘材料或电介质的侵蚀(例如，圆角化)。例如，阻挡层604可以延伸超出导电结构106预定的范围(即，宽度、直径等)并在衬底102的表面上延伸，在平坦化期间保护衬底102的表面。换句话讲，第一阻挡界面302设置在第一衬底102的基本平坦的表面的至少一部分上，并且被布置成保护基本平坦的表面免受由于基本平坦的表面的平坦化或抛光引起的侵蚀。在阻挡界面302在适当的位置的情况下，在导电结构106和衬底102的相交处，或者在阻挡层界面302和衬底102的相交处，不会出现电介质侵蚀(例如，圆角化)。在一些示例中，阻挡界面302可以用作用于抛光衬底102的指示器，并且在一些示例中，阻挡界面302也可以被抛光所期望的量以获得平坦的平滑结合表面。
在方框F处，将具有制备的衬底104、导电结构108和阻挡层302的类似微电子结构放置到衬底102上以用于结合。在方框G处，衬底104直接结合到衬底102而没有中间材料(诸如，粘合剂)以形成微电子组件300。特别地，衬底104结合到衬底102的结合表面和衬底102上的阻挡层302，并且衬底102结合到衬底104的结合表面和衬底104上的阻挡层302。在该步骤中，由于CMP工艺，来自衬底102的导电结构106和来自衬底104的导电结构108可以稍微凹入到结合线110下方，并且可以不物理接触。在一些情况下，导电结构108可以经由加热退火等结合到导电结构106。在如上所讨论的在高温下退火之后，导电结构108与导电结构106配合以形成电连接。
由于错位引起的导电结构106与导电结构108的任何偏移位于阻挡界面302上，而不是在衬底102和衬底104上。因此，导电材料(例如，铜)到衬底102和/或衬底104材料(例如，氧化硅)中的扩散由于(多个)阻挡界面302而减少或消除。
在另一实施方案中，在图6的方框E处平坦化之后，在互连焊盘204和阻挡层302上沉积附加层，该附加层通常与衬底102(例如氧化硅)具有相同类型的材料。随后是另一平坦化工艺，例如CMP，以去除多余的衬底材料并获得其中阻挡层302与围绕它的衬底102的表面齐平的表面。阻挡层302部分地或完全围绕互连器204，并且衬底层102完全或部分地围绕阻挡层302。在该实施方案中，在方框G期间，结合层102和104的直接结合与衬底102的阻挡层302与衬底104的阻挡层302的直接结合一起发生。接着是退火步骤，其中导电结构108可以经由加热退火等结合到导电结构106。
图7是示出根据另一实施方案的形成微电子组件300的示例性方法700的图形流程图，该微电子组件包括具有嵌入式导电结构106和嵌入式导电结构108以及一个或多个阻挡界面302的一对衬底102和104。
在方框A处，该方法包括将阻挡层材料604沉积到氧化物或其他电介质(例如)衬底102的表面上。在方框B处，移除阻挡层604的一部分和衬底102的电介质的一部分，并且所得到的空腔602填充有导电材料202(在方框C处)。在一些实施方案中，在空腔202中形成导电材料602的方法可以包括在用导电材料202填充空腔602之前，在第一阻挡层604和空腔602的表面上涂覆第二阻挡层(未示出)。
在方框D处，通过平坦化导电材料202和第二阻挡层(如果存在的话)来形成具有被阻挡界面302围绕的互连焊盘204的导电结构106。在实施方式中，阻挡界面302防止平坦化期间在导电结构106的交叉点处的衬底102的电介质侵蚀是有效的。在实施方案中，具有制备的阻挡界面302和导电结构106的该结构102可以结合到另一个类似的结构，但是在另一结构上没有阻挡界面302。在此类实施方案中，阻挡层302可以基于用于阻挡层的材料(例如，氮化硅等)充当另一结构的结合表面。
在方框E处，如果期望的话，可以改变阻挡界面302以移除任何不希望的部分。可以沉积抗蚀剂、掩模或其他图案702，并且根据需要蚀刻阻挡界面302(在方框F处)。附加的衬底材料(例如诸如氧化硅)可以沉积在衬底102的表面上，以将表面准备为以便于结合。例如，添加的材料可以在掩模702仍在适当的位置时或者在移除掩模702之后沉积。然后将衬底102的表面平坦化(经由CMP等)以获得平坦的平滑表面(该平坦的平滑表面包括与阻挡界面302齐平的衬底102的表面)以准备用于结合。
在方框G处，示出了所制备的衬底102，其中互连焊盘204具有部分或完全包围的阻挡界面302。两个类似制备的衬底102和衬底104可以在它们的平坦化表面上堆叠和结合以形成微电子结构300，如方框H所示。导电材料的任何重叠发生在(多个)阻挡界面302处而不是衬底102和/或衬底104的电介质处。该方法也可以用于形成具有部分地或完全围绕多个导电互连结构106、108的(多个)阻挡界面302的多个导电互连结构106、108。
在另选的实施方式中，导电结构106和/或导电结构108可以包括导电机械焊盘。在该实施方式中，机械焊盘与阻挡层302或衬底102/衬底104紧密配合以将机械焊盘固定到衬底102/衬底104。
图8是描述根据实施方案的形成微电子组件(诸如微电子组件300)的示例过程800的流程图，该微电子组件包括具有嵌入式导电结构(诸如导电结构106和导电结构108)的一对衬底(诸如，一对衬底102和104)以及一个或多个阻挡界面(诸如，阻挡界面302)。
在方框802处，该过程包括在第一衬底(例如诸如衬底102)的表面中形成第一空腔(或多个第一空腔)。在实施方案中，第一衬底包括绝缘材料或电介质(诸如氧化硅等)，其可以被设置在半导体基底上，该半导体基底具有在基底上、中、穿过该基底的电路。在方框804，该过程包括在第一衬底处形成第一阻挡界面(例如诸如阻挡界面302)，并且至少部分地围绕第一空腔的周边。在实施方式中，该过程包括将第一阻挡层材料沉积到第一空腔的表面的至少一部分上。第一阻挡层材料也可以沉积在第一衬底的至少一部分表面上，特别地部分地或完全围绕第一空腔。在实施方案中，第一阻挡界面包括不同于绝缘材料或电介质的材料，并且被布置成抑制导电材料扩散到第一衬底中。
在方框806，该过程包括用导电材料填充第一空腔。在各种实施方案中，导电材料包括铜、铜合金或类似的导电材料。
在方框808，该过程包括平坦化第一衬底、第一阻挡界面(包括第一阻挡层材料)和导电材料的表面的至少一部分，以形成第一导电互连结构，其中第一阻挡界面至少部分地围绕第一导电互连结构的暴露表面。在实施方案中，第一阻挡界面形成为具有预定宽度。
在另选的实施方式中，该过程包括将绝缘材料或电介质(例如，氧化硅)的附加层沉积到第一衬底的表面上，以改善衬底的结合表面。例如，沉积可以用于填充在先前的平坦化步骤期间产生的任何空隙，以使得衬底的表面与阻挡界面齐平等。在实施方式中，在沉积之后，衬底的表面被重新平坦化，以形成平坦、平滑且齐平的结合表面。第一阻挡界面(至少部分地)围绕导电互连器，并且绝缘材料或电介质(至少部分地)围绕第一阻挡界面。
在实施方式中，该过程包括在第二衬底(例如诸如衬底104)的表面中形成第二空腔，其中第二衬底也包括绝缘材料或电介质。该过程包括在第二衬底处形成第二阻挡界面，并且至少部分地围绕第二空腔的周边，其中第二阻挡界面包括不同于第二衬底的绝缘材料或电介质的材料。在实施方式中，该过程包括将第二阻挡层材料沉积到第二衬底的表面的至少一部分上以及沉积到第二空腔的表面的至少一部分上。
第二阻挡界面被布置成抑制第一导电结构的导电材料(嵌入在第一衬底中)扩散到第二衬底中。在实施方式中，该过程包括形成第一阻挡界面和/或第二阻挡界面以包括填充空气的间隙。在另一实施方式中，该过程包括形成第一阻挡界面和/或第二阻挡界面，以包括第一衬底和/或第二衬底的表面的粗糙区域，该粗糙区域抑制在粗糙区域处进行结合。在其他实施方案中，第一阻挡界面和/或第二阻挡界面包括氮化硅、氮氧化硅、碳化硅、碳氮化硅、金刚石、硼掺杂玻璃或氧化物、氧化铝或类似的抗扩散材料中的一种或多种。
在实施方式中，该过程包括用导电材料填充第二空腔，并且平坦化第二衬底、第二阻挡界面和第二衬底处的导电材料的表面的至少一部分，以形成第二导电互连结构(例如诸如导电结构108)，其中第二阻挡界面至少部分地围绕第二导电互连结构的暴露表面。在一个示例中，该过程包括形成第一阻挡界面或第二阻挡界面，以具有第二导电互连结构的直径的至少10％的宽度。在另一示例中，该过程包括形成第一阻挡界面或第二阻挡界面，以具有第二导电互连结构的直径/宽度的至少20％的宽度。
该过程进一步包括在没有粘合材料的情况下将第二衬底的表面直接结合到第一衬底的表面，并将第二导电互连结构配合到第一导电互连结构，使得当第二导电互连结构和第一导电互连结构偏移或错位时，第二导电互连结构的任何部分接触第一阻挡界面而不接触第一衬底，并且第一导电互连结构的任何部分接触第二阻挡界面而不接触第二衬底。
在实施方式中，该过程包括将第二导电互连结构的暴露表面直接结合到第一导电互连结构的暴露表面。在示例中，该过程包括高温退火以将导电结构结合成单个导电互连器。
尽管在本文中讨论了各种实施方式和示例，但是通过组合各个实施方式和示例的特征和元素，其他实施方式和示例也是可能的。
结论
尽管已经用结构特征和/或方法动作专用的语言描述了本公开的实施方式，但是应当理解，这些实施方式不必限于所描述的特定特征或动作。相反，公开了特定特征和动作作为实现示例性装置和技术的代表性形式。
本文档的每个权利要求构成单独的实施方案，并且组合不同权利要求和/或不同实施方案的实施方案在本公开的范围内，并且在阅读本公开后对于本领域普通技术人员将是显而易见的。

Claims (25)

1.一种衬底，具有键合表面，所述衬底包括：
第一绝缘材料，具有上表面和竖直延伸至少部分地穿过所述第一绝缘材料的厚度的第一腔；
第一导电互连焊盘，至少部分地设置在所述第一腔中，以及
嵌入式阻挡界面材料，设置在所述第一绝缘材料上，而不在所述上表面的下方延伸，
其中所述衬底的所述键合表面准备用于直接键合，所述键合表面包括在所述嵌入式阻挡界面材料之上间隔开的电介质表面，和所述第一导电互连焊盘的上表面，并且
其中所述嵌入式阻挡界面材料抑制导电材料从所述键合表面扩散到所述第一绝缘材料。
2.根据权利要求1所述的衬底，还包括在所述嵌入式阻挡界面材料上并部分地限定所述衬底的所述键合表面的键合层。
3.根据权利要求2所述的衬底，其中所述键合层完全覆盖所述嵌入式阻挡界面材料。
4.根据权利要求2所述的衬底，其中所述键合层包括硅和氧。
5.根据权利要求1所述的衬底，其中所述嵌入式阻挡界面材料跨所述衬底延伸。
6.根据权利要求1所述的衬底，其中所述嵌入式阻挡界面材料包括氮化硅、氧氮化硅、碳化硅或碳氮化硅中的一种或多种。
7.根据权利要求6所述的衬底，其中所述嵌入式阻挡界面材料包括碳氮化硅。
8.根据权利要求1所述的衬底，其中所述嵌入式阻挡界面材料接触所述互连焊盘的侧壁。
9.根据权利要求1所述的衬底，其中所述第一绝缘材料还包括第二腔，所述第二腔竖直延伸至少部分地穿过所述第一绝缘材料的所述厚度，以及至少部分地设置在所述第二腔中的第二导电互连焊盘，其中所述嵌入式阻挡界面材料从所述第一导电互连焊盘延伸到所述第二导电互连焊盘。
10.一种键合结构，包括：
第一衬底，具有键合表面，所述第一衬底包括：
第一绝缘材料，具有上表面和竖直延伸至少部分地穿过所述第一绝缘材料的厚度的第一腔；
第一导电互连焊盘，至少部分地设置在所述第一腔中；
嵌入式阻挡界面材料，设置在所述第一绝缘材料上，而不在所述上表面的下方延伸，所述嵌入式阻挡界面材料抑制导电材料从所述键合表面扩散到所述第一绝缘材料；以及
电介质表面，在所述嵌入式阻挡界面材料之上间隔开，所述电介质表面和所述第一导电互连焊盘的上表面限定所述第一衬底的所述键合表面，以及
第二衬底，具有第二绝缘材料和第二互连焊盘，
其中所述第一衬底和所述第二衬底被直接键合到彼此而没有中间粘合剂。
11.根据权利要求10所述的键合结构，其中所述第一衬底的所述电介质表面被直接键合到所述第二衬底的所述第二绝缘材料，并且所述第一导电互连焊盘被直接接合到所述第二导电互连焊盘。
12.根据权利要求11所述的键合结构，其中所述键合层包括硅和氧。
13.根据权利要求12所述的键合结构，其中所述嵌入式阻挡界面材料包括碳氮化硅。
14.根据权利要求12所述的键合结构，其中所述嵌入式阻挡界面材料包括氮化硅。
15.一种衬底，具有键合表面，所述衬底包括：
第一绝缘材料，具有第一区域和第二区域，所述第一区域具有延伸至少部分地穿过所述第一绝缘材料的厚度的第一腔和第二腔；
第一导电互连接触，至少部分地设置在所述第一腔中；
第二导电互连接触，至少部分地设置在所述第二腔中；
在所述第一区域中的阻挡界面，所述阻挡界面至少在所述第一导电互连接触与所述第二导电互连接触之间延伸，所述第二区域没有所述阻挡界面，
其中所述衬底的所述键合表面准备用于直接键合。
16.根据权利要求15所述的衬底，其中所述第一区域包括跨所述第一区域延伸的导电互连接触区域和所述阻挡界面。
17.根据权利要求16所述的衬底，其中第一区域被没有所述阻挡界面的所述第二区域包围。
18.根据权利要求15所述的衬底，其中所述阻挡界面是所述第一绝缘材料上方的连续层，所述阻挡界面包括穿过其中的、用于所述第一导电互连接接触和所述第二导电互连接触的开口。
19.根据权利要求15所述的衬底，其中所述阻挡界面材料包括氮化硅、氧氮化硅、碳化硅或碳氮化硅中的一种或多种。
20.根据权利要求19所述的衬底，其中所述阻挡界面包括碳氮化硅。
21.根据权利要求15所述的衬底，所述第一导电互连接接触是第一互连焊盘，并且所述第二导电互连接触是第二互连焊盘。
22.根据权利要求15所述的衬底，其中所述阻挡界面是嵌入式阻挡界面，所述嵌入式阻挡界面设置在所述第一绝缘材料的上表面上，而不在所述上表面的下方延伸，其中所述键合表面包括在所述嵌入式阻挡界面之上间隔开的电介质表面，和所述第一导电互连焊盘的上表面。
23.一种键合结构，包括：
第一衬底，具有键合表面，所述衬底包括：
第一绝缘材料，包括第一区域和第二区域，所述第一区域具有延伸至少部分地穿过所述第一绝缘材料的厚度的第一腔和第二腔；
第一导电互连接触，至少部分地设置在所述第一腔中；
第二导电互连接触，至少部分地设置在所述第二腔中；以及
在所述第一区域中的阻挡界面，所述阻挡界面至少在所述第一导电互连接触与所述第二导电互连接触之间延伸，所述第二区域没有所述阻挡界面，以及
第二衬底，具有第二键合表面，所述第二键合表面被直接键合到所述衬底的所述键合表面而没有中间粘合剂。
24.根据权利要求23所述的键合结构，其中所述衬底的所述第一导电互连接触和所述第二导电互连接触，被直接键合到所述第二衬底的对应的第三导电互连接触和第四导电互连接触。
25.根据权利要求23所述的键合结构，其中所述阻挡界面包括碳氮化硅。
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