TWI756476B - 用於互連的擴散障壁環 - Google Patents

用於互連的擴散障壁環 Download PDF

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TWI756476B
TWI756476B TW107134807A TW107134807A TWI756476B TW I756476 B TWI756476 B TW I756476B TW 107134807 A TW107134807 A TW 107134807A TW 107134807 A TW107134807 A TW 107134807A TW I756476 B TWI756476 B TW I756476B
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substrate
conductive
interface
barrier
interconnect
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TW107134807A
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TW201926621A (zh
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拉杰詡 卡特卡
賽普里恩 艾米卡 烏佐
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美商英帆薩斯邦德科技有限公司
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Abstract

技術及裝置之代表性實施例用來減少或防止導電材料擴散至結合基板之絕緣或介電材料中。歸因於重疊，未對準導電結構可能會與該些基板之介電質部分直接接觸，尤其當使用直接結合技術時。可抑制該擴散之障壁界面通常在該導電材料與該介電質之間安置在該重疊處。

Description

用於互連的擴散障壁環
以下描述係關於積體電路（「IC」）之處理。更詳言之，以下描述係關於用於處理晶粒或晶圓以準備結合之技術。 優先權主張及相關申請案之交叉參考
本申請案主張2018年9月27日提交之美國非臨時申請案第16/143,580號及2017年10月6日提交之美國臨時申請案第62/569,232號的權益，該些申請案特此以全文引用之方式併入。
晶粒或晶圓等等可以三維配置堆疊作為之各種微電子封裝方案之部分。此可包括在較大基底晶粒或晶圓上堆疊一或多個晶粒或晶圓，以豎直配置堆疊多個晶粒或晶圓，及此等之各種組合。晶粒可堆疊於晶圓上，或晶圓可在單粒化之前堆疊於其他晶圓上。晶粒或晶圓可使用各種結合技術而以堆疊配置之形式結合，包括使用直接介電質結合、非黏著技術，諸如ZiBond®直接結合技術或DBI®混合結合技術，該兩者可購自Invensas Bonding Technologies公司（以前為Ziptronix公司）、Xperi公司之子公司（參見例如美國專利第6,864,585號及第7,485,968號，該兩者之全文併入於本文中）。
當使用直接結合技術結合堆疊式晶粒或晶圓時，需要待結合之晶粒或晶圓的表面極扁平且平滑。舉例而言，該些表面之表面拓樸應具有極小變化，使得該些表面可緊密地配合以形成持續結合。亦需要表面潔淨且不含雜質、顆粒及/或其他殘餘物。舉例而言，不合需要的顆粒之存在可使得結合在該些顆粒之部位處有缺陷或不可靠。舉例而言，留存於結合表面上之一些顆粒及殘餘物可在堆疊晶粒之間的結合界面處產生空隙。
結合晶粒或晶圓之各別配合表面常常包括內嵌的導電互連結構等等。在一些實例中，結合的表面經配置且對準使得來自各別表面之導電互連結構在結合期間接合。接合的互連結構在堆疊晶粒或晶圓之間形成連續導電互連（用於信號、功率等）。然而，歸因於使用精細間距導電互連結構、取放工具之置放準確度限制、晶粒或晶圓表面上之接觸柵格圖案、相異襯墊大小等等，一個晶粒或晶圓之導電互連襯墊可偏移或部分地覆疊另一晶粒或晶圓之配合表面的介電質部分（例如，氧化矽等），而非與另一晶粒或晶圓之配合表面上之各別導電互連襯墊完全對準。
諸如此之未對準可使得覆疊互連襯墊之導電材料（例如，銅等）擴散至與其接觸之介電質中，潛在地導致微電子結構之效能降低。舉例而言，氧化矽之障壁屬性可在較高溫度下（諸如在退火期間）且在電場內顯著地降低（相對於氮化矽、氮氧化矽、碳氮化矽等），從而促進導電材料擴散至氧化矽中。此會導致漏電、互連之間的短路等等。效能降低在其涉及晶粒或晶圓之結合堆疊的多個導電互連結構時可尤其成問題，其可不利地影響封裝良率及封裝效能。
裝置及技術之各種具體實例減少或防止導電材料擴散至結合基板之絕緣材料或介電質中。特定言之，本文中所揭示之裝置及技術減輕歸因於基板之結合表面上之未對準導電結構的不當擴散。歸因於重疊，未對準導電結構可另外與基板之表面之的介電質部分直接接觸，尤其當使用直接結合技術時。
該些裝置及技術包含使用通常安置在導電材料與介電質之間的障壁界面，其可抑制導電層擴散至環繞的介電材料中。
該些基板可為由半導體或非半導體材料構成之晶粒、晶圓、載體、較大平板等。半導體材料可例如包含直接帶隙或間接帶隙半導體及其組合。非半導體材料可包含例如介電材料，例如玻璃、陶瓷、碳氧化矽、氧化矽等，或其組合。本文中對術語「基板」之使用意欲包括所有此等及其他相似實例。
在一具體實例中，一種微電子組裝件可包括具有第一實質上平坦表面之至少一第一基板，該第一基板包含例如絕緣材料或介電質。該介電質可提供於半導體、絕緣或導電材料之基底晶粒或晶圓上。第二基板具有第一實質上平坦表面，該第二基板亦包含例如絕緣材料或介電質。該介電質可提供於半導體、絕緣或導電材料之基底晶粒或晶圓上。該第一基板之材料可與該第二基板之材料相同（或類似）。然而，在一替代具體實例中，該第一基板之材料為與該第二基板之材料不同之材料。該第二基板之該第一表面在無諸如黏著劑之介入材料之情況下結合至該第一基板之該第一表面。
第一導電互連結構內嵌於該第一基板中（或內嵌於該第一基板之一層中），該第一導電互連結構之表面藉由該第一基板之該第一表面暴露以形成第一互連襯墊。第二導電互連結構內嵌於該第二基板中（或內嵌於該第二基板之一層中），該第二導電互連結構之表面藉由該第二基板之該第一表面暴露以形成第二互連襯墊。該第一互連襯墊面向且可接觸該第一基板之該第一表面之一部分，且該第二互連襯墊面向且可接觸該第二基板之該第一表面之一部分。在一個實施中，該第二互連襯墊直接結合至該第一互連襯墊。
在各種實例中，該第二互連襯墊可相對於該第一互連襯墊未對準，從而導致該第一互連襯墊及/或該第二互連襯墊在相對基板之該絕緣材料或介電質上方的某一重疊。
在該具體實例中，第一障壁界面安置於該第一基板處且至少部分地環繞該第一互連襯墊之周邊。該第一障壁界面包含不同於該第一基板之該絕緣材料或介電質之材料，且經配置以抑制該第二導電互連結構之材料至該第一基板中之擴散。在該具體實例中，該第一障壁界面之該材料亦為與該第二導電互連結構之材料不同的材料。在一個實施中，該第一障壁界面包含氣隙、粗糙化表面等。
在另一具體實例中，該微電子組裝件亦包括安置於該第二基板處之一第二障壁界面。該第二障壁界面至少部分地環繞該第二互連襯墊之一周邊，且包含不同於該第二基板之該絕緣材料或介電質之一材料。該第二障壁界面經配置以抑制該第一導電互連結構之材料至該第二基板中之擴散。在一個實施中，該第二障壁界面包含氣隙、粗糙化表面等。
在一些具體實例中，該第一障壁界面及/或該第二障壁界面可包含多種材料或可包含由一或多種材料構成之多個部分。在其他具體實例中，該第一障壁界面及/或該第二障壁界面可包含材料、氣隙、粗糙化表面等之組合。
在各種具體實例中，該第一障壁界面或該第二障壁界面可部分或完全地環繞其各別基板之多個互連襯墊。替代地，多個障壁界面可部分或完全地環繞該第一基板或該第二基板之一或多個互連襯墊。
在一些具體實例中，該第一障壁界面或該第二障壁界面亦可減輕或防止可在平坦化等期間在導電互連結構之該周邊處發生之介電質侵蝕（例如，圓化）。
可使用區塊流程圖說明所揭示之程序中的一些，包括圖形流程圖及/或文字流程圖。並非意欲將描述所揭示之程序的次序視為限制，且可以任何次序組合任何數目個所描述之程序區塊以實施該些程序或替代程序。另外，可在不脫離本文中所描述之主題之精神及範圍的情況下自程序刪除個別區塊。此外，在不脫離本文中所描述之主題的範圍之情況下，所揭示程序可在任何合適之製造或處理裝置或系統，以及任何硬體、軟體、韌體或其組合中實施。
在下文使用複數個實例來更詳細地解釋實施。儘管在此處且在下文論述各種實施及實例，但其他實施及實例可藉由組合個別實施及實例之特徵及元件來成為可能。
概述
圖1分別為展示堆疊基板102及104內之內嵌的導電結構106及108的未對準之一對堆疊基板102及104之剖面圖。基板102及104至少在每一基板102及104之結合表面處由絕緣材料或介電質（例如，氧化矽等）構成。舉例而言，基板102及104可表示由（諸如矽等的主動半導體之）基層構成之微電子組件的頂部絕緣層，在相關聯絕緣層內，該基層上面有一或多個金屬化層。在一些狀況下，基板102可顯著地大於基板104。在一個實例中，基板104可包含具有在1至30 mm之間或甚至更大的寬度之晶粒，而基板102可包含（例如）大於基板104、諸如平板之較大基板、200或300 mm晶圓等之另一晶粒。
在結合之前，內嵌的導電結構106及108之藉由基板102及104之結合表面暴露的部分可形成互連襯墊等。在一實例中，基板102及104在各別結合表面處結合，且導電結構106及108電耦合，且通常亦機械地結合以形成單一（連續）導電結構。結合線110指示基板102及104之結合表面接合之地方。
在一實例中，結合基板102及104形成微電子組裝件100。舉例而言，基板102及104可直接結合，包括使用混合結合技術，而不使用諸如黏著劑之介入材料。在結合之前，導電結構106及108可在基板102及104之表面下方稍微凹陷以為金屬膨脹準備。基板102及104之表面經由直接結合（（例如，經由ZibondTM ）——不使用黏著劑之室溫下的介電質至介電質）來結合。接著在高溫退火（＜ 350C）之情況下，接觸襯墊106及108膨脹且形成產生電連接之金屬與金屬結合。在結合操作之後，例如當基板102及104包括晶圓時，可在分段之前測試結合組裝件100之良裸晶粒，以分離成各種結合基板或晶粒。
如圖1中所展示，歸因於上文所論述各種原因中之一或多者，包括用於將基板104結合至基板102之取放工具之不準確性（或公差），導電結構106及108可在基板102及104置放在一起且結合時未對準。未對準之偏移112包含互連襯墊106超出互連襯墊108之周邊或邊緣之重疊及/或互連襯墊108超出互連襯墊106之周邊或邊緣之重疊。歸因於偏移112，導電結構106及108中之一者或兩者之一部分可分別接觸基板104及102之絕緣材料。如上文所論述，導電結構106及108中之一者或兩者之導電材料（例如，銅或銅合金等）可歸因於此接觸而擴散至基板104及102之絕緣材料或介電質中。另外，一些程序要素（諸如高溫退火）或操作參數（例如高頻電場等）可使導電材料至基板104及102之絕緣材料或介電質中之擴散加劇，從而誘發例如該介電層中之不當漏電。
圖2為根據一具體實例之說明形成包含具有內嵌的導電結構106及108之一對基板102及104之微電子組裝件100的實例程序200之圖形流程圖。在一實例中，鑲嵌結構係由基板102形成。在區塊（A）處，導電材料202（例如，銅、銅合金、鎳或含鎳導體等）沉積於基板102之表面上方，包括至鑲嵌腔中，填充該腔。在區塊（B）處，導電材料202經平坦化（例如，經由化學機械拋光（chemical mechanical polishing ；CMP）、蝕刻等）以形成導電結構106。導電結構106之暴露部分可包含互連襯墊204。在一個具體實例中，互連襯墊204在基板102之結合表面下方稍微凹陷可為較佳的。結合表面藉由清潔方法加以製備以移除誘發不當顆粒之缺陷、剩餘有機材料及其類似物。清潔表面可藉由將表面中之一或多者暴露至氮電漿而加以製備以為結合程序做準備。
在區塊（C）處，類似鑲嵌結構係由另一基板104形成，該基板在平坦化之後包括導電結構108。導電結構108之暴露部分可包含互連襯墊206。基板104之經製備結合表面置放在基板102上方且堆疊至基板102上以為結合準備。經組裝基板102及104接著在低於350℃且較佳地低於250℃之溫度下經熱處理維持足夠長時間，以使結合表面永久性地結合且使相對導電材料機械地且電氣地耦合。
區塊（D）、（E）及（F）展示將基板102結合至基板104之三個可能結果。區塊（D）表示理想情境，其中導電結構106及108良好地對準且無偏移。區塊（E）表示一般情境，其中基於用於將基板104結合至基板102之置放工具的平均不準確性（例如，公差），存在導電結構106及108之平均未對準。區塊（F）表示極端情境，其中基於用於將基板104結合至基板102之置放工具的最大不準確性（例如，公差），存在導電結構106及108之極端未對準。通常，取放工具之置放速度越高，則其置放準確度越低，亦即偏移越大。對於具有極小互連襯墊大小之應用，置放工具可顯著地減緩以改良置放準確度，從而影響產出率。
如上文所論述，偏移112（在區塊（E）及（F）處展示）提供使導電結構106及108之導電材料分別擴散至基板104及102之絕緣材料或介電質中的機會。 實例障壁界面
根據本發明，例如為了避免銅擴散至氧化物中，包含介電質結合層、導電障壁層或其他障壁之障壁界面302可圍繞互連襯墊106及/或108施加以形成防止擴散之障壁。障壁界面302材料經選擇使得導電結構106及108之導電材料（例如銅）至障壁材料中之擴散率相較於基板104及102之絕緣材料或介電質（例如，氧化矽）的擴散率較差。在各種具體實例中，障壁材料可包括具有預選定擴散率特性之導電或非導電材料。
圖3A及圖3B為根據各種具體實例之展示與具有內嵌的導電結構106及108之堆疊基板102及104一起使用之障壁界面302的實例之剖視圖。在一實施中，基板102及104在無諸如黏著劑之介入材料之情況下直接結合，以形成微電子組裝件300。在該實施中，微電子組裝件300包含如上文所論述之微電子組裝件100且在基板102及104中之一者或兩者上包括一或多個障壁界面302。在一替代實施中，微電子組裝件300在結合堆疊中包括多於兩個基板（諸如基板102及104），其中堆疊之基板中之一或多者包括一或多個障壁界面302。在另一實施中，微電子組裝件300包括分別結合至另一基板或晶圓之兩個或多於兩個基板（諸如基板102及104），其中基板中之兩者或多於兩者包括一或多個障壁界面302。
在一實施中，組裝件300之障壁界面302安置於基板102及104中之一者或兩者處，且至少部分地分別環繞互連襯墊204及/或206之周邊，及/或內嵌的導電結構106及108。如圖3A處所展示，障壁界面302可包含不同於基板102及/或基板104之絕緣材料或介電質之一或多種材料。舉例而言，障壁界面302可包含不同於基板102及/或基板104之絕緣材料或介電質之介電材料。在各種實施中，障壁界面302包含氮化矽、氮氧化矽、碳化矽、碳氮化矽、金剛石、摻雜硼之玻璃或氧化物、氧化鋁或如防擴散材料中之一或多者。在其他實施中，障壁界面302包含鎳、鎳合金或各種組合之一或多種其他導電材料。
另外，使用障壁界面302可包括用以藉由避免相關結合界面處之結合來防止擴散之技術。舉例而言，在各種具體實例中，各別導電互連結構106及108可結合，但緊密環繞的絕緣材料或介電質中極少或無一者結合。如圖3B處所展示，障壁界面302中之一或多者可包含凹槽、氣隙或氣體填充腔等。再次，障壁界面302包含與基板102及/或基板104之絕緣材料或介電質不同的材料。在各種實施中，障壁界面302包含惰性氣體或流體、預選定氣體或流體（基於所要屬性）、真空等。氣隙障壁界面302可藉由蝕刻、在基板102及/或104中製作底切、經由CMP、研磨、在CMP期間在基板及互連襯墊界面附近的基板圓化等使基板102及/或104凹陷等而形成。
參考圖3A及圖3B，在該實施中，障壁界面302經配置以抑制導電互連結構106及108之材料分別擴散至基板104及102中。舉例而言，障壁界面302之材料經選擇使得導電互連結構106之材料或導電互連結構108之材料至基板104或基板102之障壁界面302的材料中之擴散率小於導電互連結構106或108之材料至基板104或基板102之材料（例如，氧化矽）中的擴散率。
在各種具體實例中，障壁界面302中之一或多者可經配置以完全環繞或涵蓋導電結構106及/或108及/或其各別互連襯墊204及/或206（亦即，分別為導電結構106及108之配合表面），或部分地環繞導電結構106及/或108及/或其各別互連襯墊204及/或206，從而形成防止導電材料（例如，銅）至基板102及104之材料（例如，氧化矽）中的擴散之障壁。
如圖3A及圖3B中所展示，在各種具體實例中，障壁界面302具有大於取放工具之置放準確度306的厚度（亦即，寬度、長度等）304（在圖1中亦由重疊112表示）。障壁界面302之此厚度確保在最大置放未對準之狀況下導電結構106及108之材料將接觸障壁界面302而非基板104或102。此確保任何導電材料重疊出現在障壁界面302處而非在基板材料（例如，氧化矽）處，從而防止擴散。另外，此顯著地放寬了對取放工具之置放準確度要求，從而可改良產出率，尤其在晶粒至晶粒及晶粒至晶圓結合程序中。
因此，在一個具體實例中，（導電結構106之）一個互連襯墊204與（導電結構108之）另一互連襯墊206的相對橫向位移小於障壁界面302中之一或多者的寬度。此外，在一個實施中，障壁界面302中之一或多者的寬度係導電結構106及/或108之互連襯墊204及/或206之直徑的至少10%。在其他實施中，障壁界面中之一或多者之寬度係互連襯墊204及/或206之直徑的至少20%。
如圖3B中所展示，在一些具體實例中，襯墊204之至少某一部分在結合之後延伸或伸出超出微電子組裝件300上之基板102之絕緣材料的凹陷表面，且可延伸超出結合線110。此延伸部分可為形成障壁界面302之結果，其可為由於平坦化而在圍繞襯墊204之周邊之基板102的表面上的介電質侵蝕（亦即，圓化）的結果，或兩者，或其他原因單獨或組合造成之結果。在結合之後超過基板104之凹陷表面的襯墊206之至少某一部分之相似延伸部分或伸出部分且可能超過結合線110之延伸部分亦可存在於具體實例中。
在任何狀況下，襯墊204及/或襯墊206之延伸部分之結果為至少部分地環繞襯墊204及/或襯墊206之氣隙（有意或其他）。在一些狀況下，當互連襯墊204及206未對準時（如圖3B中所展示），僅超過結合線110之襯墊204或206之至少某一部分的部分延伸部分或伸出部分可存在於一些具體實例中。
在圖3A中，（導電結構106之）一個互連襯墊204與（導電結構108之）另一互連襯墊206的相對橫向位移係小於障壁界面302中之一或多者的寬度。在退火程序期間，當導電襯墊204/206比基板材料102/104及障壁界面材料302膨脹得更多時，熱膨脹係數之間的此高失配可誘發基板102之部分在襯墊204/206推動障壁界面302之部位處自基板104去結合。在一實施中，可藉由調整退火時間及溫度而減輕（例如，減少或消除）去結合。在該實施中，結合表面可在約100至150℃下經熱處理維持2至4小時以在基板102與104之間形成強力結合。襯墊204及206接著可在第二熱處理期間使用脈動退火（pulse anneal）技術在大約250至400℃下經退火維持10秒至小於300秒。在一實例中，第二熱處理之脈動退火時間小於第一熱處理之加熱時間的10%。在該實施中，經調整加熱/退火時間能有效地減少或消除結合的微電子組裝件300之失配應力或負載。
雖然圖3A及圖3B展示延伸通過基板102及104之導電結構，但該些結構可部分地延伸通過基板或基板上之層。為簡單起見且為了集中於結合界面處的結構或結構之部分，圖3至圖7中未展示基板上、中或通過基板之導電連接的特定的細節。
圖4A至圖4E為根據額外具體實例之展示與具有內嵌的導電結構106及108之堆疊基板102及104一起使用之額外實例障壁界面302的剖視圖。如圖3A及圖4A處所展示，障壁界面302可內嵌至基板102及/或104中之一或多者中。在一具體實例中，如圖3A及圖4A中所展示，一或多個障壁界面302內嵌於基板102及/或104中，且延伸至基板102及/或104中之深度小於或等於導電結構106或108之深度。在此組態中，保護基板102及104免於導電材料擴散。在一具體實例中，如在圖3A及圖4A處所展示，障壁界面302可安置（且可暴露）在基板102及/或104之結合表面處，且可延伸預定深度至基板102及/或104中。
如圖4B中所展示，當導電結構106及108大小相異時，可在基板102或104中之一者上使用障壁界面302。舉例而言，可在導電結構106及108中之較小的導電結構上使用障壁界面302（以有利的厚度），以防止導電結構106及108中的較大導電結構之擴散，且基板102或104上無暴露的重疊。舉例而言，在一具體實例中，第一互連襯墊106之寬度小於第二互連襯墊108之寬度，且障壁界面302安置於第一基板102處，至少部分地環繞第一互連襯墊106之周邊。障壁界面302厚度/寬度使得第一互連襯墊106與障壁界面302之經組合寬度大於第二互連襯墊108之寬度。換言之，如同具體實施中之每一者，第二互連襯墊108之周邊邊緣中之至少一者係在障壁界面302之周邊內。第二互連襯墊108之另一周邊邊緣亦係在障壁界面302之周邊內或在第一互連襯墊106之周邊內（防止擴散至基板材料中）。
如圖4C中所展示，內嵌的障壁界面302可或可不在基板102及104之結合表面處暴露。障壁界面302可安置在結合表面下方的預選定距離處，且可具有各種深度及厚度（亦即寬度或長度）。舉例而言，在一個具體實例中，障壁界面302可橫跨基板102或104之寬度延伸。障壁界面302可抵靠導電結構106及/或108，且擴散可限於障壁界面302上方的基板102及104之區域，障壁界面302防止障壁界面302下方的擴散。在一些具體實例中，此障壁界面302可由聚合層或具有所要擴散率特性之相似材料構成。
如圖4D中所展示，障壁界面302可包含基板102及/或104之結合表面的粗糙區域，該粗糙區域可在基板102與104之間的結合中包括一或多個預定寬度的間隙。舉例而言，具有低拓樸變化之高度平坦結合表面通常在基板102及104上製備以便在基板102與104之間具有可靠的直接結合。然而，在一具體實例中，部分或完全地圍繞導電結構106及/或108之基板102及/或104的表面區域可具有較高粗糙度（較大的表面拓樸變化）以在基板102與104之間產生不平坦或不規則表面，從而減少或消除基板102及104之彼區域處的結合。舉例而言，粗糙度可使表面不充分平滑（或留下不足夠的表面接觸）以形成結合。高粗糙度（例如，大於10 nm變化）障壁界面302可運用蝕刻、切割、研磨、選擇性CMP等形成。
類似於關於圖4B描述之具體實例，如圖4E處所展示，當導電結構106及108大小相異時，可在基板102及104中之一者上使用障壁界面302。在圖4E之狀況下，障壁界面302包含與導電結構106及108中之較小導電結構一起使用的氣隙（或流體填充間隙）。當障壁界面302有利地經大小設定時，基板102或104上不存在導電材料的重疊，且因此無擴散。舉例而言，氣隙障壁界面302可經大小設定，使得互連襯墊204與206（實際上是互連襯墊204及206之邊緣）之間的任何偏移屬於障壁界面302內且不在基板102及104之材料處。
在一實施中，一或多個障壁界面302包含一組合，該組合包括以下各者中之兩者或多於兩者：複數個氣隙、不同於基板102及104之絕緣或介電材料之一或多種材料以及具有預定寬度之粗糙化表面。
如圖4F之平面視圖中所展示，在一具體實例中，複數個導電結構106（或互連襯墊204）可由單一障壁界面302部分或完全地環繞或涵蓋。在此具體實例中，基板102可結合至具有複數個導電結構108之另一基板104或具有導電結構之多於一個基板。
替代地，多個障壁界面302可部分或完全地環繞基板102及104中之一或多者之一或多個導電結構106、108或互連襯墊204、206。舉例而言，如圖5A至圖5C中所展示，多個導電結構106及108由障壁界面302部分或完全地環繞。舉例而言，在一具體實例中，複數個額外導電互連結構106內嵌於基板102中，其中額外導電互連結構106中之每一者之表面藉由基板102之結合表面暴露以形成複數個額外互連襯墊204。複數個額外導電互連結構108內嵌於相對的基板104中，且額外導電互連結構108中之每一者之表面藉由基板104之結合表面暴露以形成複數個額外互連襯墊206。
障壁界面302至少部分地環繞包括第一互連襯墊106及複數個額外互連襯墊106之襯墊的群組之至少子集。障壁界面302經配置以基於障壁界面302之位置及組成來抑制包括導電互連結構108及複數個額外導電互連結構108之互連結構的群組之導電材料擴散至基板102中。此外，障壁界面302亦可經配置以抑制包括導電互連結構106及複數個額外導電互連結構106之互連結構之群組的導電材料擴散至基板104中。
如圖5A及圖5C中所展示，多個導電結構106及108中之每一者可包括障壁界面302。舉例而言，在一具體實例中，一或多個額外障壁界面302安置於基板102及/或基板104處，該一或多個額外障壁界面至少部分地環繞第一互連襯墊106及複數個額外互連襯墊106及/或第二互連襯墊108及複數個額外互連襯墊108之一或多個額外子集的周邊。該一或多個額外障壁界面302包含不同於基板102及/或基板104之絕緣材料或介電質之材料，且經配置以基於障壁界面302之位置及組成來抑制包括導電互連結構108及複數個額外導電互連結構108之互連結構的群組之材料擴散至基板102之材料中。此外，該一或多個額外障壁界面302可經配置以抑制包括導電互連結構106及複數個額外導電互連結構106之互連結構的群組之材料擴散至基板104之材料中。
參考圖5A至圖5C，在一些具體實例中，間隙502可在每一障壁界面302之間，該間隙可為障壁界面302之間的空間、氣體填充間隙等。間隙502在基板102及104之結合表面之間形成物理分離，該物理分離至少圍繞導電結構106及/或108之周邊。在一些具體實例中，障壁界面302與間隙502之組合防止或減少導電結構106及/或108及其各別互連襯墊204及206之導電材料擴散至基板104及102之材料中。在另一具體實例中，無此類間隙502形成於基板102及104之結合表面之間。
替代地，如圖5B中所展示，單一導電結構106及/或108，以及兩個或多於兩個導電結構106及/或108之群組可由單一障壁界面302部分或完全地環繞。障壁界面302之間可存在或可不存在間隙502，如上文所描述。通孔（例如，TSV），諸如通孔504可存在於本文中所論述之具體實例中之任一者中，該些具體實例包括在圖5B處所展示之實例具體實例。通孔504可延伸至基板102及104中之一者或兩者之外部界限（例如，暴露表面）（且超出），或其可延伸某一分率部分而通過基板102及/或基板104。 實例程序
圖6為根據一具體實例之說明形成包含具有內嵌的導電結構106及108之一對基板102及104以及一或多個障壁界面302之微電子組裝件300的實例程序600之圖形流程圖。
在區塊A處，該方法包括在基板102之表面中形成腔602（或複數個腔602及603）。腔602及603可藉由圖案化蝕刻等形成。在一具體實例中，腔603中之一者可延伸小於另一腔602之深度之5%的深度。在區塊B處，障壁層604形成於基板102之表面上及在腔602內。舉例而言，障壁層604可由氮化矽、氮氧化矽、碳化矽、碳氮化矽、金剛石、摻雜硼的玻璃或氧化物、氧化鋁或擴散率屬性比氧化矽差之其他合適材料或其組合構成。在其他具體實例中，障壁層604可包含導電材料，例如鈦或鉭或其對應的氮化物、鎳及鎳合金，或其他導電材料及組合。
在區塊C處，塗佈有障壁層604之腔602填充有導電材料202，諸如銅、銅合金等。舉例而言，此可使用雙鑲嵌程序進行。在一些實例中，可能希望導電結構106在基板102而非障壁層604處接觸腔602之底部。在此等實例中，障壁層604之部分可自腔602之底部部分（及/或任何其他所要部分）移除以在用導電材料202填充腔602之前暴露基板102。
在區塊D處，藉由蝕刻、CMP等移除溢出的導電材料202，在障壁層604處終止，以在障壁層604內形成導電結構106（或多個導電結構106）。在區塊E處，導電結構106及障壁層604之一部分經由CMP平坦化，例如以形成部分或完全地環繞互連襯墊204之障壁界面302及基板102之實質上平坦表面（具有變化不超過10至20 nm之平滑表面構形），該障壁界面可具有極小凹槽。
在一些具體實例中，障壁層604或障壁界面302可用於防止或減輕可在平坦化期間發生之基板102的絕緣材料或介電質之侵蝕（例如，圓化）。舉例而言，障壁層604可在基板102之表面上方延伸超出導電結構106預定長度（亦即寬度、直徑等），從而在平坦化期間保護基板102之表面。換言之，第一障壁界面302安置於第一基板102之實質上平坦表面的至少一部分上方，且經配置以保護實質上平坦表面免於歸因於實質上平坦表面之平坦化或拋光的侵蝕。在障壁界面302在適當位置之情況下，無介電質侵蝕（例如，圓化）可出現在導電結構106與基板102之相交處或在障壁界面302與基板102之相交處。在一些實例中，障壁界面302可用作用於拋光基板102之指示符，且在一些實例中，可亦將障壁界面302拋光所要量以達成平坦、平滑結合表面。
在區塊F處，具有經製備基板104、導電結構108及障壁層302之相似微電子結構經置放至基板102上以用於結合。在區塊G處，基板104在無諸如黏著劑之介入材料之情況下直接結合至基板102，以形成微電子組裝件300。詳言之，基板104結合至基板102之結合表面且結合至基板102上之障壁層302，且基板102結合至基板104之結合表面且結合至基板104上之障壁層302。在此步驟處，來自基板102之導電結構106及來自基板104之導電結構108可歸因於CMP程序在結合線110下方稍微凹陷，且可不實體接觸。在一些狀況下，導電結構108可經由經加熱退火等結合至導電結構106。在如先前所論述在高溫下退火之後，導電結構108配合至導電結構106以形成電連接。
歸因於未對準之導電結構106與導電結構108之任何偏移擱置在障壁界面302上而非在基板102及104上。因此，歸因於障壁界面302，會減少或消除導電材料（例如，銅）擴散至基板102及/或104材料（例如，氧化矽）中。
在另一具體實例中，在圖6之區塊E處平坦化之後，通常與基板102（例如氧化矽）屬於相同材料類型的額外層沉積於互連襯墊204及障壁層302上方。此之後為另一平坦化程序，例如CMP，以移除過量基板材料，且達成如下表面：其中障壁層302與環繞該表面之基板102的表面齊平。障壁層302部分或完全地環繞互連件204，且基板層102完全或部分地環繞障壁層302。在該具體實例中，在區塊G期間，102及104之結合層的直接結合連同基板102之障壁層302與基板104之障壁層302的直接結合一起進行。此之後為退火步驟，其中導電結構108可經由經加熱退火等結合至導電結構106。
圖7為根據另一具體實例之說明形成微電子組裝件300之實例程序700的圖形流程圖，該微電子組裝件包含具有內嵌的導電結構106及108之一對基板102及104以及一或多個障壁界面302。
在區塊A處，該方法包括將障壁層材料604沉積至氧化物或其他介電質（例如）基板102之表面上。在區塊B處，障壁層604之一部分及基板102之介電質的一部分經移除，且所得腔602填充有導電材料202（在區塊C處）。在一些具體實例中，在腔602中形成導電材料202之程序可包括在用導電材料202填充腔602之前在第一障壁層604及腔602之表面上方塗佈第二障壁（未展示）。
在區塊D處，具有由障壁界面302環繞之互連襯墊204的導電結構106係藉由平坦化導電材料202及第二障壁層（若存在）形成。在一實施中，障壁界面302有效地防止在平坦化期間基板102在導電結構106之相交處的介電質侵蝕。在一具體實例中，具有經製備障壁界面302及導電結構106之此結構102可結合至另一相似結構，但障壁界面302不在另一結構上。在此具體實例中，基於用於障壁層之材料（例如，氮化矽等），障壁層302可充當另一結構之結合表面。
在區塊E處，視需要，障壁界面302可經更改以移除任何非所需部分。抗蝕劑、光罩或其他圖案702可經沉積，且障壁界面302可視需要加以蝕刻（在區塊F處）。額外基板材料（諸如氧化矽）可沉積至基板102之表面上以使表面為結合準備。舉例而言，當光罩702仍在適當位置時或在移除光罩702之後，可沉積經添加材料。接著（經由CMP等）平坦化基板102之表面以達成平坦、平滑表面以為結合準備，該平坦、平滑表面包括與障壁界面302齊平之基板102的表面。
在區塊G處，展示具有互連襯墊204之經製備基板102，該互連襯墊具有部分或完全地涵蓋之障壁界面302。兩個類似地製備之基板102及104可在其平坦化表面處堆疊且結合以形成微電子結構300，如在區塊H處所展示。導電材料之任何重疊出現在障壁界面302處而非在基板102及/或104之介電質處。此方法亦可用於形成多個導電互連結構106、108，其中障壁界面302部分或完全地環繞多個導電互連結構106、108。
在一替代實施中，導電結構106及/或108可包括導電機械襯墊。在該實施中，機械襯墊與障壁層302或基板102/104密切地配合以將機械襯墊緊固至基板102/104。
圖8為根據一具體實例之描述形成微電子組裝件（諸如微電子組裝件300）之實例程序800的流程圖，該微電子組裝件包含具有內嵌的導電結構（諸如導電結構106及108）之一對基板（諸如該對基板102及104）以及一或多個障壁界面（諸如障壁界面302）。
在區塊802處，該程序包括在第一基板（諸如基板102）之表面中形成第一腔（或複數個第一腔）。在一具體實例中，第一基板包含絕緣材料或介電質，諸如氧化矽等，該絕緣材料或介電質可提供於半導體基底上，該半導體基底具有在該基底上、中、穿過該基底之電路。在區塊804處，該程序包括在第一基板處形成至少部分地環繞第一腔之周邊的第一障壁界面（諸如障壁界面302）。在一實施中，該程序包括將第一障壁層材料沉積至第一腔之表面的至少一部分上。第一障壁層材料亦可沉積至第一基板之表面的至少一部分上，尤其部分或完全地環繞第一腔。在一具體實例中，第一障壁界面包含不同於絕緣材料或介電質之材料且經配置以抑制導電材料擴散至第一基板中。
在區塊806處，該程序包括用導電材料填充第一腔。在各種具體實例中，導電材料包含銅、銅合金或相似導電材料。
在區塊808處，該程序包括平坦化第一基板之表面的至少一部分、第一障壁界面（包括第一障壁層材料）及導電材料以形成第一導電互連結構，其中第一障壁界面至少部分地環繞第一導電互連結構之暴露表面。在一具體實例中，第一障壁界面形成為具有預定寬度。
在一替代實施中，該程序包括將絕緣材料或介電質（例如，氧化矽）之額外層沉積至第一基板之表面上以改良基板之結合表面。舉例而言，該沉積可用於填充在先前平坦化步驟期間產生之任何空隙，以使基板之表面與障壁界面齊平等。在該實施中，在沉積之後重新平坦化基板之表面以形成平坦、平滑且齊平的結合表面。第一障壁界面環繞（至少部分地）導電互連件，且絕緣材料或介電質環繞（至少部分地）第一障壁界面。
在一實施中，該程序包括在第二基板（諸如基板104）之表面中形成第二腔，其中第二基板亦包含絕緣材料或介電質。該程序包括在第二基板處形成至少部分地環繞第二腔之周邊的第二障壁界面，其中第二障壁界面包含不同於第二基板之絕緣材料或介電質的材料。在一實施中，該程序包括將第二障壁層材料沉積至第二基板之表面的至少一部分上且沉積至第二腔之表面的至少一部分上。
第二障壁界面經配置以抑制第一導電結構（內嵌於第一基板中）之導電材料擴散至第二基板中。在一實施中，該程序包括形成包含氣體填充間隙之第一障壁界面及/或第二障壁界面。在另一實施中，該程序包括形成包含第一基板及/或第二基板之表面的粗糙化區域之第一障壁界面及/或第二障壁界面，其抑制粗糙化區域處之結合。在其他具體實例中，第一障壁界面及/或第二障壁界面包含氮化矽、氮氧化矽、碳化矽、碳氮化矽、金剛石、摻雜硼的玻璃或氧化物、氧化鋁或相似防擴散材料中之一或多者。
在該實施中，該程序包括用導電材料填充第二腔及平坦化第二基板之表面的至少一部分、第二障壁界面及第二基板處之導電材料以形成第二導電互連結構（諸如導電結構108），其中第二障壁界面至少部分地環繞第二導電互連結構之暴露表面。在一個實例中，該程序包括形成具有為第二導電互連結構之直徑的至少10%之寬度的第一障壁界面或第二障壁界面。在另一實例中，該程序包括形成具有為第二導電互連結構之直徑/寬度的至少20%之寬度的第一障壁界面或第二障壁界面。
該程序進一步包括在無黏著材料之情況下將第二基板之表面直接結合至第一基板之表面及將第二導電互連結構配合至第一導電互連結構，使得當第二導電互連結構與第一導電互連結構偏移或未對準時，第二導電互連結構之任何部分接觸第一障壁界面且不接觸第一基板，並且第一導電互連結構之任何部分接觸第二障壁界面且不接觸第二基板。
在一實施中，該程序包括將第二導電互連結構之暴露表面直接結合至第一導電互連結構之暴露表面。在一實例中，該程序包括高溫退火以將導電結構結合至單一導電互連件中。
儘管本文中論述了各種實施及實例，但藉由組合個別實施及實例之特徵及元件，另外實施及實例可為可能的。 結論
儘管已以特定針對於結構特徵及/或方法動作之語言描述本發明之實施，但應理解，實施不一定限於所描述特定特徵或動作。確切而言，將特定特徵及動作揭示為實施實例裝置及技術之代表性形式。
本文之每項技術方案構成單獨具體實例，且組合不同技術方案之具體實例及/或不同具體實例在本發明之範圍內，且將在查閱本發明之後對於一般熟習此項技術者顯而易見。
100‧‧‧微電子組裝件 102‧‧‧基板 104‧‧‧基板 106‧‧‧導電結構/互連襯墊 108‧‧‧導電結構/互連襯墊 110‧‧‧結合線 112‧‧‧偏移/重疊 200‧‧‧實例程序 202‧‧‧導電材料 204‧‧‧互連襯墊 206‧‧‧互連襯墊 300‧‧‧微電子組裝件 302‧‧‧障壁界面/障壁層 304‧‧‧厚度 306‧‧‧置放準確度 502‧‧‧間隙 504‧‧‧通孔 600‧‧‧實例程序 602‧‧‧腔 603‧‧‧腔 604‧‧‧障壁層 702‧‧‧抗蝕劑、光罩或其他圖案 800‧‧‧實例程序 802‧‧‧區塊 804‧‧‧區塊 806‧‧‧區塊 808‧‧‧區塊
參考附圖闡述詳細描述。在該些圖中，參考數字之最左側數位識別首次出現該參考數字之圖。在不同圖中使用相同參考數字指示類似或相同物件。
對此論述，在圖中所說明之裝置及系統展示為具有大量組件。如本文中所描述，裝置及/或系統之各種實施可包括更少組件且保持在本發明之範圍內。替代地，裝置及/或系統之其他實施可包括額外組件或所描述組件之各種組合，且保持在本發明之範圍內。
圖1為展示堆疊基板內之內嵌的導電結構之未對準之一對堆疊基板的剖面圖。
圖2為說明形成包含具有內嵌的導電結構之一對基板之微電子組裝件的實例程序之圖形流程圖。
圖3A及圖3B為根據各種具體實例之展示與具有內嵌的導電結構之堆疊基板一起使用之實例障壁界面的剖視圖。
圖4A至圖4E為根據額外具體實例之展示與具有內嵌的導電結構之堆疊基板一起使用之實例障壁界面的剖視圖。
圖4F為根據一具體實例之展示實例障壁界面及多個內嵌的導電結構之平面視圖。
圖5A至圖5C為根據額外具體實例之展示與具有內嵌的導電結構之堆疊基板一起使用之實例障壁界面的剖視圖。
圖6為根據一具體實例之說明形成包含具有內嵌的導電結構之一對基板及障壁界面之微電子組裝件的實例程序之圖形流程圖。
圖7為根據另一具體實例之說明形成包含具有內嵌的導電結構之一對基板及障壁界面之微電子組裝件的實例程序之圖形流程圖。
圖8為根據各種具體實例之說明用於形成包含具有內嵌的導電結構之一對基板及障壁界面之微電子組裝件的實例程序之流程圖。
100‧‧‧微電子組裝件
102‧‧‧基板
104‧‧‧基板
106‧‧‧導電結構/互連襯墊
108‧‧‧導電結構/互連襯墊
110‧‧‧結合線
112‧‧‧偏移/重疊

Claims (23)

  1. 一種微電子組裝件，其包含：第一基板，其具有第一實質上平坦表面，該第一基板包含絕緣材料；第二基板，其具有第一實質上平坦表面，該第二基板包含絕緣材料，該第二基板之該第一表面在無黏著劑之情況下直接結合至該第一基板之該第一表面；第一導電互連結構，其內嵌於該第一基板中，該第一導電互連結構之表面藉由該第一基板之該第一表面暴露以形成第一互連襯墊；第二導電互連結構，其內嵌於該第二基板中，該第二導電互連結構之表面藉由該第二基板之該第一表面暴露以形成第二互連襯墊；及第一障壁界面，其安置於該第一基板之該第一實質上平坦表面處且至少部分地環繞該第一互連襯墊之周邊，藉此將該第一導電互連結構與該第一實質上平坦表面處之該絕緣材料分離，該第一障壁界面包含至少部分地環繞該第一導電互連結構且接觸所述第二導電互連結構之所述第一障壁界面的第一部分以及至少部分地環繞該第一導電互連結構而無接觸所述第二導電互連結構之所述第一障壁界面的第二部分，所述第一障壁界面包括不同於該第一基板之該絕緣材料之材料，該第一障壁界面之至少一部分延伸預定深度至該第一基板中，該預定深度小於該第一導電互連結構之深度。
  2. 如請求項1所述之微電子組裝件，其中該第一障壁界面經配置以抑制該第二導電互連結構之材料擴散至該第一基板中。
  3. 如請求項1所述之微電子組裝件，其中該第一障壁界面由導電材料構成。
  4. 如請求項3所述之微電子組裝件，其中該第一障壁界面由鈷、氮化鈦、氮化鉭、鎳或鎳合金構成。
  5. 如請求項1所述之微電子組裝件，其中該第一障壁界面為單一層， 其包含：第一部分，其延伸預定深度至該第一基板中，該預定深度小於該第一導電互連結構之深度，及第二部分，其沿著該第一導電互連結構之該表面自該第一部分延伸。
  6. 如請求項1所述之微電子組裝件，其中該第一障壁界面安置於該第一基板之該第一實質上平坦表面的至少一部分上方，且經配置以保護該第一實質上平坦表面免於歸因於該第一實質上平坦表面之平坦化或拋光的侵蝕。
  7. 如請求項1所述之微電子組裝件，其進一步包含第二障壁界面，該第二障壁界面安置於該第二基板處且至少部分地環繞該第二互連襯墊之周邊，該第二障壁界面包含不同於該第二基板之該絕緣材料的材料。
  8. 如請求項7所述之微電子組裝件，其中該第二障壁界面經配置以抑制該第一導電互連結構之材料擴散至該第二基板中。
  9. 如請求項7所述之微電子組裝件，其中該第一導電互連結構之該材料或該第二導電互連結構之該材料至該第一障壁界面之該材料或該第二障壁界面之該材料中的擴散率小於該第一導電互連結構之該材料或該第二導電互連結構之該材料至該第一基板之該材料或該第二基板之該材料中的擴散率。
  10. 如請求項1所述之微電子組裝件，其中該第一基板之該材料或該第二基板之該材料包含氧化矽。
  11. 如請求項1所述之微電子組裝件，其中該第二互連襯墊結合至該第一互連襯墊以形成單一導電結構。
  12. 如請求項1所述之微電子組裝件，其中該第二互連襯墊相對於該第一互連襯墊未對準，從而導致該第一互連襯墊超出該第二互連襯墊之周邊的重疊及/或該第二互連襯墊超出該第一互連襯墊之該周邊的重疊。
  13. 如請求項1所述之微電子組裝件，其中該第一互連襯墊之寬度小 於該第二互連襯墊之寬度，該第一障壁界面安置於該第一基板處且至少部分地環繞該第一互連襯墊之該周邊，使得該第一互連襯墊與該第一障壁界面之經組合寬度大於該第二互連襯墊之該寬度。
  14. 如請求項1所述之微電子組裝件，其中該第二互連襯墊之周邊邊緣係在該第一障壁界面之周邊內。
  15. 如請求項1所述之微電子組裝件，其中該第一基板之該絕緣材料包含氧化矽材料且該第二導電互連結構之該材料包含銅或銅合金。
  16. 如請求項1所述之微電子組裝件，其中該第一障壁界面包含不同於該第二基板之該絕緣材料的介電材料。
  17. 如請求項1所述之微電子組裝件，其中該第一障壁界面由氮化矽、氮氧化矽、碳化矽、碳氮化矽、金剛石、摻雜硼的玻璃或氧化物或氧化鋁中之一或多者構成。
  18. 如請求項1所述之微電子組裝件，其中該第一障壁界面之寬度為該第二互連襯墊之直徑的至少10%，且該第一障壁界面具有接觸該第一導電互連結構之側表面及接觸該第一基板之該絕緣材料之底表面。
  19. 如請求項1所述之微電子組裝件，其中該第一障壁界面之寬度為該第二互連襯墊之直徑之至少20%。
  20. 如請求項1所述之微電子組裝件，其中該第一互連襯墊與該第二互連襯墊之相對橫向位移小於該第一障壁界面之寬度。
  21. 如請求項1所述之微電子組裝件，其中該第一障壁界面內嵌於該第一基板中且延伸至該第一基板中之深度小於或等於該第一導電結構之長度。
  22. 如請求項1所述之微電子組裝件，其中基於用於將該第二基板結合至該第一基板之置放工具之平均不準確性，該第二互連襯墊相對於該第一互連襯墊未對準達一偏移。
  23. 一種微電子組裝件，其包含：第一基板，其具有第一實質上平坦表面，該第一基板包含絕緣材料；第二基板，其具有第一實質上平坦表面，該第二基板包含絕緣材料，該第二基板之該第一表面在無黏著劑之情況下直接結合至該第一基板之該第一表面；第一導電互連結構，其內嵌於該第一基板中，該第一導電互連結構之表面藉由該第一基板之該第一表面暴露以形成第一互連襯墊；第二導電互連結構，其內嵌於該第二基板中，該第二導電互連結構之表面藉由該第二基板之該第一表面暴露以形成第二互連襯墊；及第一障壁界面，其安置於該第一基板之該第一實質上平坦表面處且至少部分地環繞該第一互連襯墊之周邊，藉此將該第一導電互連結構與該第一實質上平坦表面處之該絕緣材料分離，該第一障壁界面包含至少部分地環繞該第一導電互連結構之所述第一障壁界面的第一部分以及至少部分地環繞該第一導電互連結構而無接觸所述第二導電互連結構之所述第一障壁界面的第二部分，所述第一障壁界面包括不同於該第一基板之該絕緣材料之材料，該第一障壁界面之至少一部分延伸預定深度至該第一基板中，該預定深度小於該第一導電互連結構之深度。
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