CN1162193A - 树脂封包型半导体装置 - Google Patents
树脂封包型半导体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 194
- 239000011347 resin Substances 0.000 title claims abstract description 43
- 229920005989 resin Polymers 0.000 title claims abstract description 43
- 239000004020 conductor Substances 0.000 claims abstract description 186
- 230000004927 fusion Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 210000002683 foot Anatomy 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 9
- 239000013256 coordination polymer Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000005855 radiation Effects 0.000 description 7
- 238000004458 analytical method Methods 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 239000007767 bonding agent Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000001149 thermolysis Methods 0.000 description 1
- 210000005239 tubule Anatomy 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
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Abstract
半导体装置,包括芯片,连接芯片于导线框的导电体,和封包树脂。导线框包括框及其支撑的包括实质朝框中心点放射状延伸的第一内导线群和第二内导线群的多数导线。每个第一内导线有第一内端紧邻中心点,每个第二内导线有第二内端离中心点较远;且第一及第二内导线交错排列。该排列方式为至少一些内导线在半导体芯片下面延伸而提供热传导路径。导线框适用在共用于设置不同外形尺寸的半导体芯片且在该导线的间保持着必要的间隙。
Description
本发明是关于一种树脂封包型半导体装置及一种树脂封包型半导体装置的导线框,此半导体装置可让各种尺寸的半导体芯片载置于共用导线框而不需重大地改变装配技术,且此半导体装置改善了散热。
图15a是概要的传统半导体装置平面视图,图15b是图15a沿A-A’线剖开的部份视图,图16是使用于传统半导体装置的具有100个管脚的导线框的平面视图,图17是图16的局部视图。从图15到图17,参考号码1是半导体芯片,2是管心垫(die pad),3是粘接剂,4是内导线,5是金属电线及6是封包树脂。如图所示,在传统半导体装置及用于此的导线框,管心垫2具有符合半导体芯片1大小的尺寸,于是导线框是依所使用的对应的半导体芯片1而制备。换言之,在传统的树脂封包型半导体装置中,许多导线框必须为了不同大小的各半导体芯片以一对一相称的方式制备。
因此,在传统技术上,用于制造半导体装置所需制备的导线框的种类数量必须与半导体芯片的种类数量相等。所以,导线框必须由昂贵的蚀刻法制造而不能用便宜的冲压法,造成了制造成本的增加。
并且,固然可想到将导线框制成长条卷带状,并共用一种导线框于多种不同大小的半导体芯片,然而由于目前的电线粘接技术及塑模技术很难称心如意地达成这种构想。再者,对于传统装置要改善散热,它通常需要散热器或类似物,也造成了成本增加;因为半导体芯片所产生的热量必须经低热传导性的封包树脂的厚层或局部传导出去。
因此,在传统技术上,一种导线框只能用来放置一种相同尺寸的半导体芯片。因半导体芯片大小依半导体芯片的功能而不同。导线框乃为每一种特定的半导体芯片而设计,故实质上只能用于该种芯片。所以导线框只能由昂贵的蚀刻法制造而不可能减少半导体装置的价格。
日本专利公开2-28966号揭示了一种以共同采用一种种类的导线框于多种不同种类半导体芯片为目的的共用于多种不同种类的半导体芯片的导线框的传统制造技术的一例,此技术为,将传统的管心垫予以省略,而将半导体芯片以粘接剂粘接于导线框的内导线,且在芯片与导线的间保留一短距离以便在制造过程中支持半导体芯片。
然而,此种技术不考虑使用冲压方法于导线框的制造的限制来看,导线框可共用的范围是狭窄的及受限的且实际的应用范围也有限。换言的,日本专利公开2-28966号揭示的技术,当引线键合到半导体芯片的管脚数量大的同时粘接垫(bonding pad)很小如150μm到100μm,及当半导体芯片微小时,导线内尖端要完全地围绕半导体芯片会太挤,而且不可能将导线尖端配置于半导体芯片轮廓的导线内部而直接键合内导线于半导体芯片,因而没有实质上的效益。
于是,本发明的目的是提供一种无上述的传统装置的缺陷的半导体装置。
本发明的另一目的是提供一种无上述的传统导线框的缺陷的半导体装置导线框。
本发明的另一目的是提供一种任何不同形状及尺寸的半导体芯片均可放置于相同共用的导线框而无需完全改变装配技术以及改善了散热的半导体装置。
本发明更进一步的目的是提供一种导线框,此导线框可共用于放置许多种不同尺寸的半导体芯片,特别是对半导体装置的制造有用,及可由比蚀刻方法便宜的冲压方法制造。
由上述目的来看,本发明的半导体装置包括半导体芯片,包含第一内导线和第二内导线的多数条导线,各该第一和第二内导线是从半导体芯片中心实质上放射状延伸,以电性连接半导体芯片于内导线的导电体及封包半导体芯片,导电体和内导线的封包树脂。每个第一内导线具有第一内端位于紧邻中心点,每个第二内导线具有第二内端位于离中心点较第一内端远的位置;且第一和第二内导线是实质上互相交错排列。于是,此排列方式使得至少内导线的一部分在半导体芯片下延伸而提供热传导路径。
半导体芯片可只与第一内导线重叠;或者,与第一和第二内导线成为重叠关是。
内导线也可包含第三内导线,每个第三内导线具第三内端位于离中心点较第二内端远的位置,且半导体芯片关于第一,第二及第三内导线有重叠关是。
半导体装置可更进一步包括配置于半导体芯片和内导线间的电性绝缘的良导热器,半导体装置还可包括配置于封包树脂内的散热器。
本发明的导线框包括框以及由框支持的多数条导线,该多数条导线包括实质上向框的中心呈放射状延伸的第一内导线和第二内导线。每个第一内导线有第一内端紧邻中心点,每个第二内导线有第二内端位于离中心点比该第一内端远处,且第一和第二内导线实质上互相交错地配置,由此该导线框适合共用于将不同外部尺寸的半导体芯片载置于导线框上而在导线间维持所需要的间隙。
导线可包括第三内导线,每个第三内导线具第三内端位于离中心点较第二内端远处。
每个第二内导线是配置于第一内导线和第三内导线间,每个第三内导线配置于第一和第二内导线间。
导线框可更进一步包括配置于框内及第一内端内侧的管心垫(die pad)及连接框和管心垫以支持管心垫的支撑脚(supporting pin)。管心垫可配置于包含内导线的平面上。
至少一个内导线可以移除,以便容许熔融的封包树脂平滑流动。
内导线可弯成曲柄状并使内导线内部在一平面内,该平面是平行于包括框的平面,但与包含框的平面不同。
本发明将由下面依附图所示的实施例所作的详细说明更加明了,其中:
图1a是本发明第一实施例半导体装置的概要的平面视图。
图1b是第1a图沿A-A’线剖视的剖面侧视图;
图2a到2c是本发明第一实施例半导体装置的不同改进的概要平面视图;
图2d至2f是各自从图2a至2c沿A-A’线剖视的剖面侧视图;
图3a是本发明第二实施例半导体装置的概要平面视图;
图3b是图3a沿A-A’线剖视的剖面侧视图;
图4a是本发明第三实施例半导体装置的概要平面视图;
图4b是图3a沿A-A’线剖视的剖面侧视图;
图5是本发明导线框的放大局部视图;
图6是本发明另一导线框的放大局部视图;
图7是本发明又一导线框的放大局部视图;
图8仍是本发明其它导线框的放大局部视图;
图9a是本发明另一导线框的放大局部视图;
图9b仍是本发明另一导线框的放大局部视图;
图10a是举例图示于塑模(molding)具有管心支撑导线时的树脂流动路径的部分侧视图;
图10b是举例图示于塑模(molding)时不具有管心垫支撑导线的树脂流动路径的部分侧视图;
图11是本发明的实施例的导线框的局部放大视图,显示了导线的侧边部分;
图12是本发明另一实施例半导体装置的概要侧视图;
图13是本发明又一实施例半导体装置的概要侧视图;
图14是本发明另一实施例半导体装置的概要侧视图;
图15a是传统设计的半导体装置的概要平面视图;
图15b是图15a沿A-A’线剖视的剖面侧视图;
图16是传统导线框的平面视图;
图17是图16所示传统导线框的局部视图。
第一实施例
从图1a及1b与图2a到2f可见,本发明半导体装置包括,设置于具有多条导线L的导线框(lead frame)LF上的半导体芯片1。导线L包含内导线4及外导线9,且内导线4包含第一内导线4a,第二内导线4b及第三内导线4c,每一个内导线从框F中心点CP实质上放射状延伸(参阅图5)。导线框LF也包括设置在中心部位而具支撑脚2a的方块管心垫(die pad)2。半导体装置也包括导电体5如键合电线(bonding wire)以电性连接半导体芯片1于内导线4,也包括封包半导体芯片1,导电体5和内导线4的封包树脂6。
每个第一内导线4a有第一内端15a位于紧邻导线框LF或半导体芯片1的中心点CP。每个第二内导线4b有第二内端15b位于离中心点CP较第一内端15a远处,而每个第三内导线4c有第三内端15c离中心点CP最远处。第一、第二及第三内导线实质上相互交错排列使各自的内导线4间维持需要的间隙。
图1a及1b所示的半导体芯片1为第一种尺寸,而管心垫2与半导体芯片1比较尽可能做成较小的尺寸,其一边的尺寸为2mm到3mm,于是内导线4内端能在半导体芯片1下面的位置。从图1b可见,管心垫2的平面在内导线4平面的上方大约100μm处,以使他们不在同一平面。
此实施例中,小管心垫2为方形且内导线4包含第一种内导线4a具内端15a位于靠近且围绕管心垫2处。可由图看出,内端15a沿着环或圆配置,该圆的中心与管心垫2的中心符合。内导线4也包含第二种内导线4b,该第二内导线4b有沿着第二个环配置的内端15b,该第二个环大于第一个环而且与第一个环同中心。内导线4另外还包含第三种内导线4c,该第三种内导线4c是在第一种内导线4a及第2种内导线4b间的位置,其内端15c在离管心垫2最远之处而与第二个环同中心的围绕着第二个环。
在图2c与2f所示的实施例,标准尺寸的半导体芯片1a载置于本发明的导线框LF上。在制造过程中,半导体芯片1a借一层绝缘粘接剂3附着且由升起的管心垫2支撑。在完整的半导体装置,半导体芯片1a和内导线4a,4b,4c的相对地小的间隙由一层固化的封包树脂填充。当需要时,半导体芯片1a可由键合电线5以电性连接于所有第一内导线4a,第二内导线4b和第三内导线4c。所以,半导体芯片1a与所有的第一、第二和第三内导线4a,4b,4c形成重叠关是。
然而,如图1a,1b,2b和2e所示,当希望装设中型尺寸的半导体芯片1b时,半导体芯片1b只可由键合电线5以电性连接于第一和第二内导线4a和4b,不包括第三内导线4c,以便经导线4建立对外连接的电路。在此例中,半导体芯片1b只与第一及第二导线4a及4b呈重叠关是。
如图2a及2b所示,当要装载最小尺寸的半导体芯片1c时,只有第一内导线4a可经键合电线5以电连接半导体芯片1造成对外的电路。在此例中,半导体芯片1c只与第一内导线4a有重叠关是。
所以,根据此发明,即使是半导体芯片1,如半导体芯片1a,1b及1c等不同尺寸的半导体芯片,同一个共用的导线框LF可用于装载这些半导体芯片1a,1b 1c而不需显著修正制造程序,并且可维持内导线4间的绝缘所需要的间隙。
另外在此实施例,因为多条的内导线4在半导体芯片1下面,半导体芯片1产生的热量可经封包树脂薄层很容易地传导到内导线4且直接到外导线9将热量散到外界,结果改善了散热。
而且,较小半导体芯片1只连接于第一内导线4a,对半导体芯片1提供电路连接的内导线4的数量随着半导体芯片1的尺寸增大而增加;同时,如半导体芯片1尺寸加大,则对引导半导体芯片1所产生的热提供传导作用的导线数量也增加,结果成为适当且有效率的配置。
由图1b及2d到2f可见,不同尺寸的半导体芯片1a,1b及1c等可设置于导线框而不需要将键合线设成延长环路。
第二实施例
图3a及3b表示本发明半导体装置的另一实施例。图3b是图3a沿A-A’线剖视的剖视图。在此实施例,相框(picture frame)形态的绝缘膜7装着于紧邻半导体芯片1底面周围部分的内导线4,使得半导体芯片1底面和内导线4间的电绝缘更为可靠。绝缘膜7可由任何已知适当的电绝缘材料制做。绝缘材料最好有良好的热传导性。半导体芯片1以管心垫2经由未图示的粘接剂支持。
第三实施例
图4a及4b表示本发明半导体装置的第三实施例。图4b是图4a沿A-A’线剖视的剖视图。在此实施例,以电绝缘和具高热传导性的吸震材料,如陶瓷,作成的方形电绝缘片8,以粘接剂3贴着于半导体芯片1底面和管心垫2的间。绝缘片8延伸越过内导线4且超过半导体芯片1的四周。所以,该绝缘片有一部分配置于半导体芯片1和内导线4间。以此配置,半导体芯片1和管心垫2以及内导线4间的绝缘、吸震特性和热传导性都明显地改善了。
第四实施例
图5表示本发明半导体装置第四实施例长方形导线框LF的四分之一。在此实施例中,导线框LF包含框F(仅表示一小部分),管心垫2,管心垫支撑脚(supporting pin)11和第一、第二及第三种内导线12,13,14。支撑脚11以及内导线12,13及14由框F支撑。每个内导线在每一个间距或多数的间距处有不同的长度。另外,至少一种内导线12,13或14以实质上放射状向中心点CP延伸至管心垫2圆周部分。
在此实例中,管心垫2是圆形的且第1种内导线12有内端12a位在靠近且环绕管心垫2处。第二种内导线13位在第一种内导线12间而其内端13a是在离圆形管心垫2周围稍远的位置而且以与管心垫2呈同心圆绕着管心垫2。第三种内导线14位在第一内导线12和第二内导线13间且其内端14a离管心垫2更远,并以与管心垫2同心圆绕着管心垫2。所以,第一种内导线12和第二种内导线13位在圆形管心垫2的圆周方向的每第五导线或在每第五导线间距(lead pitch)处。然而,第三种内导线14位于每隔一个导线间距的位置。
在此实施例中,在制造时,最小尺寸的半导体芯片1c,如图2a所示,粘接于管心垫2而由管心垫2支持,并且经键合电线5以电性连接于第一内导线12。中等尺寸的半导体芯片1b,如图2b所示,由第一内导线支持以外,也可由第二内导线13支撑。最大尺寸的半导体芯片1a,如图2c所示,由第一和第二内导线12、13支持以外,也可由第三内导线14支撑。所以,较小的半导体芯片1c只能由第一内导线12支撑,而制造时用以支持半导体芯片的内导线的数量随着半导体芯片尺寸的增大而增加,此种方式为一种很适合的配置。
第五实施例
图6表示本发明第五实施例。其中,导线框LF的基本结构与图5所示者相似。即是半导体装置导线框包括管心垫2,管心垫支撑脚21和第一、第二及第三种内导线22、23及24,每个内导线在每一个或多数个间距处有不同的长度。另外,至少一种内导线22,23或24延伸到导线框LF中心点CP以及到半导体芯片圆周部分。
图6与图5比较,可见第一和第二内导线22,23具有一或二个三角形延伸的增加扩大区域22b及23b填入放射状延伸相邻内导线间的空间。扩大区域22b和23b大多位于内导线的内端部分。所以,这些扩大部分22b和23b与半导体芯片1接触,因而从半导体芯片1到内导线22及23的热传导性被改善,结果改进了半导体装置的散热作用。
第六实施例
图7表示本发明第六实施例的半导体装置,其导线框LF的基本结构与图5所示者相似。然而,管心垫和管心垫支撑脚则从本实施例导线框LF免除且本实施例导线框LF包括第一、第二及第三种内导线32,33及34,与图5所示者相似。这些内导线32,33
34在每一个或多数间距处有不同的长度。另外,第一内导线32延伸到相当于接近环绕移除的圆形管心垫位置。在此实施例中,图5所示的管心垫支撑脚11于相当第三内导线34内端的位置切断变成增加的第三内导线34。
根据此实施例,在制造时,半导体芯片1不需管心垫即可支撑及电性连接,由于不具备管心垫,在塑模时熔融树脂流入模穴处无模垫及支撑脚的防碍而能平滑流入。并且,由于不均匀的封包树脂的分布使管心垫位置偏移的问题也消除了。
第七实施例
图8表示本发明第六实施例,其中半导体装置导线框LF的基本结构与图5所示者相似。然而,管心垫和管心垫支撑脚从本实施例的导线框LF免除,且本实施例的导线框LF包括第一、第二及第三种内导线42,43及44,与于图5所示者相似。这些内导线42,43及44在每一个或多数个间距处有不同的长度。另外,第一内导线42延伸到相当于接近环绕移除的圆形管心垫位置。在此实施例中,图5所示的管心垫支撑脚11从相当于第三内导线33的内端位置完全移除而指定塑模时供熔融树脂流通的路径40。
根据此实施例,半导体芯片1不需要管心垫即可支撑及电性连接。由于没有具备管心垫,在塑模时熔融树脂流入模穴处无管心垫及支撑脚的防碍,而能平滑流入。另外,由于不均匀的封包树脂的分布而使管心垫位置偏移的问题也消除了。
图9a表示使用具有管心垫支撑脚150的导线框LF以载置半导体芯片1于导线框上的半导体装置。此导线框LF可为如图5-7所示的一种。
图9b表示使用不具备管心垫支撑脚的导线框LF以载置半导体芯片1于导线框上的半导体装置,此导线框具有相当于支撑脚150的空间50。此导线框LF可为如图8所示者。
图10a中以箭头表示当如图9a所示的导线框LF与半导体芯片1载置于塑模模具MD内时模穴(molding cavity)MC中的熔融树脂的流动状态,该导线框具有管心垫支撑脚。图10b中以箭头表示当如图9b所示的导线框LF与半导体芯片1载置于塑模模具MD内时模穴(molding cavity)MC中的融熔树脂的流动状态,该导线框不具备管心垫支撑脚。
如图10a所示,使用具支撑脚150(图9a)的导线框LF时,熔融树脂一部分从塑模MD的闸口50a经由形成于导线框LF下面的通道P进入导线框LF下面的下面空间,而另一部分经导线4及支撑脚150间的狭窄间隙(参阅图9a)流过支撑脚150周围各边而填充导线框LF上面的上面空间。因此,朝上方流动的树脂或多或少受导线4及支撑脚150的阻碍,而使注入于上面空间的树脂量少于注入于下面空间的树脂量。这在熔融树脂中产生压力差,而此压力差将使管心垫2与半导体芯片1一齐在模穴MC内上升。因为近来多脚封包型(multi-pin package type)的半导体装置有非常小的厚度而要求小模穴高度,管心垫2及半导体芯片1在塑模MD内的向上偏移将使键合电线5由封包树脂6外表面暴露出来,这当然造成半导体装置致命性的缺陷。
如图9b及10b所示导线框LF不具备管心垫与管心垫支撑脚时,熔融树脂(图10b箭头所指)流经闸口50进入模穴MC充分自由地均匀扩散到上面及下面空间并且以均匀压力填满模穴MC,结果正如以上所述不会使管心垫2及半导体芯片1在模穴MC内偏移,于是半导体装置的产率提高。
第八实施例
图11表示本发明半导体装置导线框LF的第八实施例。此实施例的导线框LF基本结构与图5所示者相似。此实施例结构与图5所示者不同处在于其内导线104,105,106全都有微弯部分104b,105b及106b或在离管心垫1或离中心点CP的位置向相反方向直角弯曲两次相同的距离,使得端部104a,105a及106a一齐与模垫2在不同放射状位置比导线框LF的平面降低。换言的,管心垫2及内导线104到106的环绕部分形成陷凹状(counter-sank)。该内导线104到106的浅弯从绘制在图11导线框LF平面视图的下的内导线104到106侧视图可显而易见的。此陷凹的目的是为了将外导线9接近半导体芯片1的中心平面放置。该陷凹宜具有相当于半导体芯片1厚度一半的深度并使半导体芯片1于即使使用对称的塑模MD时可定位于封包树脂6内的厚度方向中心位置。
第九实施例
图12表示本发明半导体装置的第九实施例,其所例示的QFP型半导体装置包括半导体芯片61,如以42合金(商标名)制造的具多条直的多数不同长度内导线的导线框62,如铜制的散热片63和将设置于导线框62的半导体芯片61封包的塑模树脂64。在此实施例中,半导体芯片61由具有与图7及8所示的不具备管心垫的结构相似的导线框62的内导线内端部分支撑。平板状的散热片63埋设于封包树脂64内的导线框62下面以便更改善半导体装置的散热。其实本发明的结构中半导体芯片61因具有多数的热传导路径经由多数的内导线而本来已将散热特性显著改善。散热片63可为任何熟悉的形式,与从导线框62同高度悬吊散热片63的支撑脚65支撑其四个角落。
第十实施例
图13表示本发明半导体装置的第十实施例,其所例示的QFP型半导体装置包括半导体芯片71,如由42合金(商标名)制造的具有多条弯曲的多数不同长度的内导线的导线框72,如铜制的散热片73和将半导体芯片71与导线框72封包的树脂膜74。在此实施例中,半导体芯片71是由具备与图11所示者相似的构造的导线框72的内导线的内端部所支持,该导线框72不具备管心垫且内导线内端于72a处弯曲而形成环绕半导体芯片71的陷凹(countersink)。具支撑脚75的散热片73埋设于封包树脂74内以便更改善半导体装置的散热,该半导体装置由于本发明的构造中半导体芯片71具有经过多数内导线的多数热传导路径而本来已经将半导体装置的散热性予以显著改善。
第十一实施例
图14表示本发明半导体装置的第十一实施例,其所例示的QFP型半导体装置包括半导体芯片81,如42合金(商标名)制造的具有多条弯曲的多数不同长度内导线的导引框82,如铜制的散热片83和将半导体芯片81与导线框82封包的树脂模84。在此实施例中,半导体芯片81由具备与图11所示者相似的构造的导线框82的内导线的内端部所支持,该导线框82不具备管心垫,且内导线内端于82a处弯曲而形成环绕半导体芯片81的陷凹(countersink)。由支撑脚85支持的散热片73埋设于封包树脂74内以便更改善半导体装置的散热;该半导体装置由于本发明结构中半导体芯片81具有经过在半导体芯片81下深处延伸的内导线而形成的多数的热传导路径而本来已将半导体装置的散热性显著改善。在此实施例中,83有热块83a,该热块的一个表面从封包树脂84底面暴露于外,由此更改善半导体装置的散热性。
如前所述,本发明的半导体装置包括半导体芯片,包含由半导体芯片中心实质上放射状延伸的第一内导线及第二内导线的多数导线以电性连接半导体芯片于内导线的导电体,以及封包半导体芯片、导电体和内导线的封包树脂。每一个第一内导线有第一内端位于中心点附近;每个第二内导线有第二内端位于离中心点较第一内端远处,且第一及第二内导线是实质上相互交错排列。所以,该排列方式使至少一些内导线在半导体芯片下面延伸而形成热传导路径。于是,可获得一种半导体装置,该半导体中任何不同形状及尺寸的半导体芯片可载置于相同而共用的导线框而不需实质上改变装配技术,而且当中的散热性也改善了。另外,本发明的导线框部分用于半导体装置制造且使较蚀刻加工更便宜的冲压过程能够制造。
本发明的导线框包括框,及由框支持的多数条导线,该导线包括实质上以放射状向框中心点延伸的第一内导线及第二内导线。每个第一内导线有第一内端位于中心点附近。每个第二内导线有第二内端位于离中心点较第一内端远处,且第一及第二内导线实质上相互交错配置,由此,该导线框即适合其用于将不同外部尺寸的半导体芯片安装于其上,而在导线间维持必要的间隙。
Claims (13)
1.一种半导体装置,包括:
一个半导体芯片;
多数导线,包含从该半导体芯片中心点实质上放射状延伸的第一内导线及第二内导线;
多数导电体,以电性连接该半导体芯片与该内导线;以及
一个用来封包该半导体芯片,该导电体及该内导线的封包树脂;
该第一内导线每个具有第一内端位于该中心点附近,该第二内导线每个具有第二内端位于从该中心点较该第一内端远处;且该第一和第二内导线实质上相互交错排列;
由此至少一些该内导线于该半导体芯片下延伸而形成热传导路径。
2.如权利要求1所述的半导体装置,其中,该半导体芯片只与该第一内导线成为重叠关系。
3.如权利要求1所述的半导体装置,其中,该半导体芯片只与该第一及第二内导线成为重叠关系。
4.如权利要求1所述的半导体装置,其中,该内导线包含第三内导线,每个第三内导线具第三内端位于离该中心点较第二内端远处,且该半导体芯片与该第一、第二及第三内导线成为重叠关系。
5.如权利要求1所述的半导体装置,另外包括设在该半导体芯片与该内导线间的具有绝缘性与良好导热性的导热体。
6.如权利要求1所述的半导体装置,另外包括散热片配置与该封包树脂内。
7.一种导线框,包括:
一个框,和
多数导线,由该框支撑,且包含朝该框中心点实质上放射状延伸的第一内导线及第二内导线;
该第一内导线每个具有第一内端位于该中心点处附近,该第二内导线每个具有第二内端位于离该中心点较该第一内端远处,且该第一及第二内导线实质上相互交错排列;
由此,该导线框适合共用于将不同外部尺寸的半导体芯片载置于该导线框,在该导线间维持必要的间隙。
8.如权利要求7所述的导线框,其中该导线包含第三内导线,每个第三内导线具第三内端离该中心点较该第二内端更远。
9.如权利要求8所述的导线框,其中该第二内导线每个配置于该第一内导线和该第三内导线间且该第三内导线每个配置于该第一及第二内导线间。
10.如权利要求7所述的导线框,另外包括一管心垫(die pad)配置于该框和该第一内端的内侧,以及连接该框与该管心垫间以支撑该管心垫的支撑脚。
11.如权利要求10所述的导线框,其中该管心垫是配置于包含该内导线的平面的上。
12.如权利要求7所述的导线框,其中至少一个该内导线被移除以使熔融封包树脂平滑流动。
13.如权利要求7所述的导线框,其中该内导线被弯成曲柄状以使该内导线内段在与包含该框的平面平行的平面内,但该平面与包含该框的平面的同。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP6622096A JPH09260575A (ja) | 1996-03-22 | 1996-03-22 | 半導体装置及びリードフレーム |
JP066220/1996 | 1996-03-22 | ||
JP066220/96 | 1996-03-22 |
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Publication Number | Publication Date |
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CN1162193A true CN1162193A (zh) | 1997-10-15 |
CN1154184C CN1154184C (zh) | 2004-06-16 |
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CNB971034915A Expired - Fee Related CN1154184C (zh) | 1996-03-22 | 1997-03-18 | 树脂封包型半导体装置 |
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Country | Link |
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US (1) | US5753977A (zh) |
JP (1) | JPH09260575A (zh) |
KR (1) | KR970067820A (zh) |
CN (1) | CN1154184C (zh) |
DE (1) | DE19708002B4 (zh) |
TW (1) | TW362267B (zh) |
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KR101486790B1 (ko) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | 강성보강부를 갖는 마이크로 리드프레임 |
KR101563911B1 (ko) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5524479A (en) * | 1978-08-09 | 1980-02-21 | Nec Corp | Semiconductor |
JPS63306648A (ja) * | 1987-06-08 | 1988-12-14 | Shinko Electric Ind Co Ltd | 半導体装置用リ−ドフレ−ムとその製造方法 |
JPS6414942A (en) * | 1987-07-08 | 1989-01-19 | Mitsubishi Electric Corp | Resin sealed semiconductor integrated circuit device |
JPH01161743A (ja) * | 1987-12-17 | 1989-06-26 | Toshiba Corp | 半導体装置 |
US4937656A (en) * | 1988-04-22 | 1990-06-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
JP2629853B2 (ja) * | 1988-07-19 | 1997-07-16 | セイコーエプソン株式会社 | 半導体装置 |
JP2602076B2 (ja) * | 1988-09-08 | 1997-04-23 | 三菱電機株式会社 | 半導体装置用リードフレーム |
JPH03280560A (ja) * | 1990-03-29 | 1991-12-11 | Nec Ic Microcomput Syst Ltd | 半導体装置 |
JPH03283648A (ja) * | 1990-03-30 | 1991-12-13 | Nec Corp | 樹脂封止型半導体装置 |
JPH07235564A (ja) * | 1993-12-27 | 1995-09-05 | Toshiba Corp | 半導体装置 |
-
1996
- 1996-03-22 JP JP6622096A patent/JPH09260575A/ja active Pending
- 1996-12-18 US US08/768,909 patent/US5753977A/en not_active Expired - Fee Related
- 1996-12-19 TW TW085115659A patent/TW362267B/zh not_active IP Right Cessation
-
1997
- 1997-02-27 DE DE1997108002 patent/DE19708002B4/de not_active Expired - Fee Related
- 1997-03-17 KR KR19970009028A patent/KR970067820A/ko not_active Application Discontinuation
- 1997-03-18 CN CNB971034915A patent/CN1154184C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR970067820A (zh) | 1997-10-13 |
DE19708002A1 (de) | 1997-09-25 |
DE19708002B4 (de) | 2004-09-16 |
TW362267B (en) | 1999-06-21 |
JPH09260575A (ja) | 1997-10-03 |
US5753977A (en) | 1998-05-19 |
CN1154184C (zh) | 2004-06-16 |
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