CN101546718B - 半导体装置封装和制造半导体装置封装的方法 - Google Patents

半导体装置封装和制造半导体装置封装的方法 Download PDF

Info

Publication number
CN101546718B
CN101546718B CN2009100070408A CN200910007040A CN101546718B CN 101546718 B CN101546718 B CN 101546718B CN 2009100070408 A CN2009100070408 A CN 2009100070408A CN 200910007040 A CN200910007040 A CN 200910007040A CN 101546718 B CN101546718 B CN 101546718B
Authority
CN
China
Prior art keywords
lead
lead frame
recess
wire
frame material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2009100070408A
Other languages
English (en)
Other versions
CN101546718A (zh
Inventor
C·K·陈
B·H·古
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN101546718A publication Critical patent/CN101546718A/zh
Application granted granted Critical
Publication of CN101546718B publication Critical patent/CN101546718B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明的名称为半导体装置封装和制造半导体装置封装的方法，提供一种制造电子装置的方法。该方法包括提供载体片、蚀刻引框材料片以形成引线框材料片的第一表面上的凹口、将电子芯片放置在载体片的凹口中、以及之后选择性地蚀刻引线框材料片的第二表面，第二表面与第一表面相对。

Description

半导体装置封装和制造半导体装置封装的方法
技术领域
本申请涉及半导体封装，在我们的实施例中是引线上芯片(COL)封装。它还涉及制造半导体封装的方法。
背景技术
常规封装的半导体装置通过使用例如银膏的粘合剂将半导体元件接合到引线框的管芯垫而产生。引线框由接合线连接到半导体元件。半导体装置除外部引线以外的整体被封住。外部引线用于外部连接。
近年来对封装半导体装置的更高密度、更小面积和厚度的要求导致具有不同结构的新型封装的开发。新型封装能用于要求小尺寸、轻重量以及出色热和电性能的手持便携式电子装置
新型封装的示例是COL(引线上芯片)封装，它包括直接安装在引线框上的管芯。COL也被称为LOC(芯片上引线)。
出于这些和其它原因，存在对于本发明的需要。
发明内容
根据本发明的第一方面在于一种制造半导体装置的方法，包括：提供引线框材料片；蚀刻所述引线框材料片以在所述引线框材料片的第一表面上形成凹口；将半导体芯片放置在所述引线框材料片的所述凹口中；以及选择性地蚀刻所述引线框材料片的第二表面，所述第二表面与所述第一表面相对。
根据本发明的第二方面在于一种制造电子装置的方法，包括：提供载体片；对所述载体片进行去除处理以形成所述载体片的第一表面上的凹口；将电子组件放置在所述载体片的所述凹口中；以及之后，选择性地去除所述载体片的第二表面的至少一部分，所述第二表面与所述第一表面相对。
根据本发明的第三方面在于一种半导体装置，包括：多个引线，所述引线的至少一个包括该引线的表面上的凹部；以及在所述凹部中提供的半导体芯片。
根据本发明的第四方面在于一种电子装置，包括：多个电连接元件，所述电连接元件的至少一个包括在所述电连接元件的表面上的凹部；以及在所述凹部中提供的电子组件。
根据本发明的第五方面在于一种电子装置，包括：具有凹部的引线，所述凹部配置成支撑半导体芯片。
附图说明
包括附图以提供对本发明更进一步的理解，并且附图结合于本说明书并构成本说明书的一部分。附图示出本发明的实施例并且结合描述用于解释本发明原理。本发明的其它实施例和本发明的许多预期优点将轻易地被理解，因为通过参考下面的详细描述它们变得更好理解。附图中的元件不一定是彼此成比例的。类似的参考标号指明对应的类似部件。
图1示出包括第一密封COL封装的截面图的半导体封装的一个实施例。
图2示出用于制造图1的封装的引线框材料。
图3示出带有管芯的图2的引线框材料。
图4示出具有蚀刻的底部表面的图3的引线框材料。
图5示出第二密封COL封装的截面图。
图6示出第三密封COL封装的截面前视图。
图7示出从顶部视角的COL封装的暴露的透视图。
图8示出从底部视角的第三COL封装的透视图。
图9示出从顶部视角的第三COL封装的透视图。
图10示出用于制造图8的第三COL封装的制造过程的流程图。
图11示出其顶部表面上具有凹进(indentations)的引线框材料。
图12示出顶部表面上具有凹口的图11的引线框材料。
图13示出图12的引线框材料上提供的管芯。
图14示出连接到图13的管芯的多个接合线。
图15示出以模塑料(molding compound)密封的图14的引线框材料。
图16示出提供有掩模的图15的引线框材料的底部表面。
图17示出镀在图16的引线框材料的底部表面上的导电材料层。
图18示出不带掩模的图16的引线框材料的底部表面。
图19示出具有蚀刻的底部表面的图18的引线框材料。
图20示出分离的图19的引线框材料。
图21示出分离的引线框材料。
具体实施方式
在以下的详细描述中，参考了形成本文一部分的附图，附图中以示例的方式示出其中可实践本发明的特定实施例。在这点上，方向性的术语，例如“顶部”、“底部”、“前”、“后”、“前置的”、“后缘的”等参考图中描绘的方向使用。因为本发明的实施例的组件能以多个不同的方向放置，所以方向性的术语只是出于说明的目的使用，而不是用来限制。应理解，在不脱离本发明的范围的情况下，可利用其它实施例，并且可进行结构的或逻辑的改变。因此，以下的详细描述不应以限制意义来理解，且本发明的范围由所附权利要求来限定。
在以下的描述中，提供细节以描述应用的实施例。但是，本领域技术人员会明白，这些实施例可在没有这些细节的情况下实践。
图1示出包括第一密封COL封装10的半导体装置封装的截面图的一个实施例。第一密封COL封装10包括多个引线指(lead finger)11和半导体芯片12。
引线指11具有凹口18，该凹口置于引线指11的末端。凹口18也称为凹部。半导体芯片12置于引线指11的凹口上。单个引线指11与其相邻引线指11分离。
配置凹口18以接纳半导体芯片12。凹口18使得半导体芯片12能够以较低高度放置。这允许COL封装10更薄。而且，凹口18有助于防止半导体芯片12移动并保持其位置。
引线指11充当半导体芯片12的电路和外部电路之间的电接触或电端子。半导体芯片12具有电路，所述电路从外部电路接收电信号、处理这些电信号并将经处理的信号发射到外部电路。
在通常意义上，引线指11是电连接元件的形式。电连接元件可包括电端子。引线指11也称为引线。在一个实施例中，半导体芯片12是电子组件。半导体芯片12可包括数字或模拟电路。电子组件可包括分立电子组件，例如电阻器。
产生第一密封COL封装10的方法在图2到5中示出。提供引线框材料片14，如图2中所示。引线框材料片14具有第一表面15′和与第一表面15′相对的第二表面15″。
第一表面15′具有连续的表面区域。该连续表面区域在其表面上没有通孔、缺口或开口。尽管如此，该连续表面区域可具有空腔。换句话说，该连续表面区域是不间断的。
接着蚀刻第一表面15′的连续表面区域以形成凹口18，如图2中所示。此后，半导体芯片12置于第一表面15′的凹口18中。这在图3中示出。
此后，蚀刻引线框材料片14的第二表面15″。该蚀刻形成引线框材料片14上的开口空间，使得凹口18上的基底的一部分被去除，该基底是引线框材料片的一部分，其位于半导体芯片12之下。开口空间将第一表面15′连接到第二表面15″。换句话说，引线框材料片14被分离以形成单个引线指11，如图5中所示。引线框材料片14的分离也称为对引线框材料片14分割。
广义上，引线框材料片14是载体片的形式。载体片旨在用于形成电连接元件或引线指。蚀刻的过程是某种形式的去除。
图6到9示出第三COL封装30的不同视图。由图6的截面前视图示出总视图。图7示出从顶部视角的暴露的透视图，以便更好地查看第三COL封装30的内部部件。图8示出从底部视角的透视图，而图9示出从顶部视角的透视图。
图5示出第二密封COL封装20的截面图。图5包括与图1到4的部件类似相同部件。相同部件具有相同名字。相同部件的描绘因此通过引用结合。
第二密封COL封装20包括多个引线指11和半导体芯片12，其被模塑料21覆盖。半导体芯片12置于引线指11的凹口18上。
密封料21旨在保护半导体芯片12免受外部环境的损害。
广义上，模塑料21是密封料的形式。密封料可包括软凝胶体。
下面描述产生第二密封COL封装20的方法。该方法包括提供引线框材料片14。引线框材料片14包括具有连续表面区域的第一表面15′和第二表面15″。
此后，蚀刻第一表面15′的连续表面区域以形成凹口18。半导体芯片12随后置于第一表面15′的凹口18中。
接着，模塑料21置于引线框材料片14上。模塑料21覆盖半导体芯片12和第一表面15′的一部分。第一表面15′的连续表面区域防止模塑料21到达第二表面15″。
接下来蚀刻引线框材料片14的第二表面15″以形成单个引线指11。
以上示出的产生第二密封COL封装20的过程避免了模型泄露(mold bleed)。模塑料21从第一表面15′渗流或扩散到第二表面15″上称为模型泄露。在产生COL封装20的其它方法中，蚀刻引线框材料片14的过程发生在使用模塑料21覆盖半导体芯片12的过程前。蚀刻的引线框材料片14具有缺口，模塑料21能通过缺口渗流到第二表面15″上。以上方法中防止了模塑料21渗流到第二表面15″上的发生，因为缺口在覆盖半导体芯片12的过程期间不存在。
图6到9包括与图1到5的部件类似的部件。类似的部件具有类似的名字。类似部件的描述因此通过引用结合。
第三COL封装30包括引线框31。引线框31包括多个引线33和36。引线框31的其它引线34、35、37和38在图7中能最好地看见。引线34到38具有凹口40，其在引线34到38的顶部上提供。
将管芯42放置在凹口40上，如图6和7所示。多个接合线44到48在管芯42和引线33到38之间附连。管芯接合带50在管芯42和引线33、34、36和37的顶部之间提供。管芯42、引线33到38、以及接合线44到48被模塑料51所覆盖。
管芯42具有上有效表面，其上形成多个电路。这些电路通过接触垫连接到接合线44到48，接触垫放置于有效表面上。电路和接触垫没有在图6到9中示出。
引线33到35可形成第一排而引线36到38可形成第二排，如图7中所示。缺口52将第一排与第二排分离。引线33到38包括类似的外形和类似的高度。引线33到38的部分从模塑料51向下突出，如图6和8中所示。
导电材料的层53，NiAu(镍-金)在引线33到38的底部表面上提供，如图6和8中所示。导电层53对于电测试是足够大的，使得测试探针在电测试期间接触导电层53不要求高精度。接触区域55在引线33到38的顶部表面上提供。接触区域55由接合线44到48连接到管芯42。
如图7中所示，引线33由接合线44附连到管芯42，而引线34由接合线45连接到管芯42。相似地，引线36附连到管芯42并且是通过接合线46。引线37由接合线47和48连接到管芯42。接合线44、45和46包括金材料，而接合线47和48具有铝材料。
管芯接合带50暴露在第三COL封装30的底部，如图8中所示。暴露的管芯接合带50具有部分矩形形状。引线33、34、36和37覆盖管芯接合带50的部分。
引线33到38的部分以向下的方式从模塑料51突出。引线33、34、35、36、37或38与其相邻引线33、34、35、36、37或38分离。引线33到38具有凹进57和58，如图6和8中所示。凹进57和58具有部分圆柱形式。
如图9中所示，模塑料51具有基本上立方体形状。模塑料51密封管芯42、引线框31和接合线44到48，使得这些部件不可见。模塑料51还覆盖引线33到38，使得引线33到38的部分没有被模塑料51所覆盖。
引线33到38的突出部分允许与外部端子的方便的电接触，例如印刷电路板的接触区域。导电层53的材料提供外部端子和引线33到38之间良好的电接触。
管芯接合带50具有热导电材料，以用于经引线33、34、36和37从工作管芯42散热。
广义上，引线33到38是某种类型引线指，而管芯42是某种类型的半导体芯片。模塑料是某种形式的密封料。接合线44到48是线的形式。管芯接合带50是接合材料层的形式。
引线框材料31能够采用带导电层53的预镀框(pre-plated frame)(PPF)形式。导电层53能够包括其它导电材料，例如镍-钯金(NiPdAu)。接合线44到46能够具有铝材料而不是金材料，而接合线47到48可包括金材料而不是铝材料。接合线44到48可具有相同的材料而不是不同的材料。接合线44到48可通过球形接合或楔形接合技术附连到引线框31或管芯42。管芯接合带50可包括管芯接合粘合剂，例如环氧胶。
第三COL封装30的部件提供不同的功能。引线框31为管芯42、管芯接合带50和接合线44到48提供支撑结构。凹口40旨在用于接纳管芯42并提供对管芯42的支撑。管芯42提供第三COL封装30的电子功能，其包括模拟信号或数字信号的处理。
接合线44到46的金材料使得接合线44到46能够方便地附连到管芯42。接合线47和48的铝材料允许接合线47和48具有厚的直径，以用于高电流密度的传输而无需高成本。接合线44到48提供管芯42和外部衬底(例如印刷电路板(PCB))之间通过引线33、34、36和37的电路径。
引线33到38充当用于第三COL封装30的外部电端子。将接合线47和48接合到相同的引线37允许引线37和管芯42之间传递更大的电流量。管芯接合带50将管芯42与引线33、34、36和37电绝缘并散去由管芯42生成的热量。
导电层53防止引线框31氧化。导电层53还提供对外部衬底的良好电接触以及到外部衬底良好的粘合。在应用焊料的情况下，导电层53的金材料在重熔过程期间扩散进入焊料，并有助于将第三COL封装30接合到外部衬底之上。
模塑料51旨在用于保护第三COL封装30的内部部件免受外部环境损害，例如热、放电和机械冲击。内部部件包括引线33到38、管芯42和接合线44到48以及管芯接合带50。而且，模塑料51紧固第三COL封装30的内部部件并防止内部部件移动。
图10示出用于制造图6到9的第三COL封装30的制造过程61到71的流程图60。
流程图60开始于提供其顶部表面上带有凹进的引线框材料的过程61。随后提供蚀刻引线框材料以用于在顶部表面上形成立方体凹口的过程62。将管芯安装到凹口中的过程64置于过程62之后。以接合线连接管芯的过程75置于过程64之后。
以模塑料密封管芯的过程68跟随过程65。将导电层镀到引线框材料的底部表面上的过程69置于过程68之后。蚀刻引线框材料的底部表面的过程70置于过程69之后。在过程70之后提供将引线框材料分离的过程71。
广义上，上述过程能被改变。例如，过程62的蚀刻可包括在引线框上提供凹进的过程。
产生第三COL封装30的方法在图11到21中示出。
提供引线框材料片74，如图11到21中所示。引线框材料片74包括具有统一厚度的铜合金片。引线框材料片74具有连续底部表面75和与底部表面75相对的连续顶部表面76。连续顶部表面76或连续底部表面65在其中不具有通孔、缺口或开口。
此后，凹进77在顶部表面76上形成。凹进77由化学蚀刻过程形成。首先在铜合金片的顶部上提供耐酸掩模。该掩模具有对应凹进77的位置的开口。
掩模通过将光阻层放置在引线框材料片74的顶部表面76上来形成。随后将紫外(UV)光通过光掩模投射到该光阻层上一个预定的时间段。投射引起暴露于UV光的光阻部分的固化。未固化的部分随后被去除。固化的部分形成掩模。换句话说，将像(image)传输到光阻层。
随后将该铜合金片浸入酸(例如氯化铁酸)瓶一个预定的时间段。开口暴露引线框材料片74的将要被酸去除的部分。该去除形成引线框材料片74上的凹进77。接着，从酸瓶移走该铜合金片。掩模和任何残留的酸随后由某种试剂去除，例如丙酮。
该过程产生凹进77，其分布在铁骨构架配置设计(grid formation)中，而在铁骨构架配置设计的结合处提供凹进77。凹进77具有特定的深度和部分圆柱形式。凹进77距离底部表面75统一的距离。图11中凹进77的几何中心以中心线标记。
由生产过程的接下来的过程使用凹进77，以用于放置或对齐引线框材料片74。
如图12中所示，接着蚀刻引线框材料片74的顶部表面76以形成凹口40。形成凹口40的该蚀刻过程与上述形成凹进77的蚀刻过程相似。
蚀刻的顶部表面76受到引线框材料片74的部分的去除。未蚀刻的顶部表面76形成接触区域55。
在晶片上提供管芯接合带50，晶片包括多个管芯42。随后切割晶片以将管芯42与其相邻管芯42分离。该切割也分离添加到管芯42的管芯接合带50。管芯接合带50置于管芯42的底部表面上。
管芯42接着放置于凹口40上，如图13中所示。该放置使用精确的管芯放置机器完成。管芯接合带50将管芯42附连到凹口42并防止管芯42移动。
此后，多个接合线44到48使用线接合机器附连在管芯42和接触区域55之间。这在图14中示出。
引线框材料片74接着由模塑料51覆盖，如图15中所示。覆盖过程包括将引线框材料片74放置在模型中。当模型处于封闭状态，熔化的模塑料51在模型里流动并覆盖管芯42和接合线44到48。引线框材料片74的顶部表面76防止熔化的模塑料51到达引线框材料片74的底部部分。不存在模塑料51到引线框材料片74的底部表面75上的渗流。
随后冷却模塑料51。该冷却允许模塑料回到固态。模塑料51包括脱模剂以用于从模型方便地去除密封的引线框材料片74。密封模塑料51随后进行模塑后加工以增加密封模塑料51的粘性。
如图16中所示，用于形成导电层53的掩模78随后在引线框材料片74的底部表面75上提供。掩模78具有开口，通过这些开口暴露且不覆盖引线框材料片74的底部表面75。
NiAu材料的导电层53接着镀到引线框材料片74的底部表面75之上。导电层53置于底部表面75的暴露部分上。这在图17中示出。由引线框材料片74通过一系列湿化学镀液的顺序浸入来提供该镀操作。
随后去除掩模78，如图18中所示。
接着蚀刻引线框材料片74的底部表面75以暴露管芯接合带50，如图19中所示。NiAu材料的导电层53充当用于此蚀刻过程的抗蚀刻掩膜。NiAu材料的层53具有抗蚀刻性质。金材料对酸的蚀刻有抗耐性。蚀刻过程产生引线框材料片74的底部表面75上的缺口52，并暴露管芯接合带50的底部表面的一部分。缺口52将底部表面75连接到顶部表面76。
随后分离蚀刻的引线框材料片74以形成分离的COL封装30，如图20中所示。该分离通过沿着切割线(saw street)80的切割来执行。切割线80从模塑料51的顶部表面延伸到凹进77，并到达引线框材料片74的底部表面75。该切割分离模塑料51和蚀刻的引线框材料片74以形成分离的COL封装30。
分离的COL封装30在图21中示出。第三COL封装30可在后续过程中受到进一步的封装和电测试以确保第三COL封装30满足封装和装置规格。
上述方法将模塑料51保持在引线框31的顶部表面76，并有利地防止模塑料51到达底部表面75。因此，避免了模型泄露。而且，该方法产生用于紧固管芯42的凹口40并将管芯42放置在较低高度。
广义上，许多其它蚀刻技术能够用于替换上述的蚀刻过程。凹进77通过冲压机器而不是蚀刻来提供。
虽然上述描述包含许多特性，但这些不应被认为是限制实施例的范围，而仅是提供可预见的实施例的说明。特别是实施例的上述优点不应被认为是限制实施例的范围，而仅是解释在所述实施例投入实践时可能的成就。因此，实施例的范围应该由权利要求及其等同物来决定，而不是由所给出的示例。

Claims (25)

1.一种制造半导体装置的方法，包括：
提供引线框材料片；
蚀刻所述引线框材料片以在所述引线框材料片的第一表面上形成凹口；
将半导体芯片放置在所述引线框材料片的所述凹口中；以及
选择性地蚀刻所述引线框材料片的第二表面，所述第二表面与所述第一表面相对，而且，通过选择地蚀刻所述引线框材料片的第二表面的蚀刻过程，只有管芯接合带的底部表面的某些部分被暴露，管芯接合带的其他部分则被引线覆盖。
2.如权利要求1所述的方法，包括，其中所述凹口通过选择性地蚀刻所述引线框材料片的所述第一表面而形成。
3.如权利要求1所述的方法，其中所述方法还包括将所述半导体芯片放置在所述凹口中之前，将接合材料添加到所述半导体芯片上。
4.如权利要求1所述的方法，其中所述方法还包括在将所述半导体芯片放置在所述凹口中之后，在所述半导体芯片和所述引线框材料片之间附连多个线。
5.如权利要求1所述的方法，其中所述方法还包括在选择性地蚀刻所述第二表面之前，以模塑料覆盖所述半导体芯片。
6.如权利要求1所述的方法，包括，其中选择性地蚀刻所述第二表面直到所述引线框材料片被分割。
7.如权利要求6所述的方法，包括分割所述引线框材料片以形成电连接元件。
8.如权利要求6所述的方法，其中所述方法还包括镀所分割的引线框材料片的部分。
9.如权利要求1所述的方法，包括，其中所述引线框材料片包括金属衬底。
10.一种制造电子装置的方法，包括：
提供载体片；
对所述载体片进行去除处理以形成所述载体片的第一表面上的凹口；
将电子组件放置在所述载体片的所述凹口中；以及之后，
选择性地去除所述载体片的第二表面的至少一部分，所述第二表面与所述第一表面相对，而且，通过选择地去除所述载体片的第二表面的至少一部分的去除过程，只有管芯接合带的底部表面的某些部分被暴露，管芯接合带的其他部分则被引线覆盖。
11.如权利要求10所述的方法，包括，其中所述载体片采用具有连续表面区域的引线框材料片的形式。
12.如权利要求10所述的方法，包括，其中所述电子组件采用半导体芯片的形式。
13.如权利要求10所述的方法，其中所述方法还包括在选择性地去除所述第二表面之前，以密封料覆盖所述电子组件。
14.一种半导体装置，包括：
多个引线，所述引线的至少一个包括该引线的表面上的凹部；以及
在所述凹部中提供的半导体芯片，
其中，通过选择性地蚀刻与所述表面相对的该引线的表面的蚀刻过程，只有管芯接合带的底部表面的某些部分被暴露，管芯接合带的其他部分则被引线覆盖。
15.如权利要求14所述的半导体装置，其中所述半导体装置还包括放置在所述半导体芯片和所述凹部之间的接合材料层。
16.如权利要求15所述的半导体装置，其中所述接合材料层包括电绝缘和热传导材料。
17.如权利要求14所述的半导体装置，其中所述半导体装置还包括附连在所述半导体芯片和所述引线之间的多个线。
18.如权利要求14所述的半导体装置，其中所述半导体装置还包括覆盖所述半导体芯片和所述引线至少一部分的模塑料。
19.如权利要求14所述的半导体装置，包括，其中所述引线的至少一个从所述模塑料突出。
20.如权利要求19所述的半导体装置，包括，其中所述半导体装置还包括在突出的引线上提供的导电材料层。
21.一种电子装置，包括：
多个电连接元件，所述电连接元件的至少一个包括在所述电连接元件的表面上的凹部；以及
在所述凹部中提供的电子组件，
其中，通过选择性地蚀刻与所述表面相对的所述电连接元件的另一表面的蚀刻过程，只有管芯接合带的底部表面的某些部分被暴露，管芯接合带的其他部分则被引线覆盖。
22.如权利要求21所述的电子装置，包括，其中所述电子连接元件采用引线的形式。
23.如权利要求21所述的电子装置，包括，其中所述电子组件采用半导体芯片的形式。
24.一种电子装置，包括：
具有凹部的引线，所述凹部配置成支撑半导体芯片，其中，通过选择性地蚀刻与所述凹部相对的引线表面的蚀刻过程，只有管芯接合带的底部表面的某些部分被暴露，管芯接合带的其他部分则被引线覆盖。
25.如权利要求24所述的电子装置，包括：
在所述引线和所述半导体芯片之间提供的接合材料。
CN2009100070408A 2008-02-01 2009-02-01 半导体装置封装和制造半导体装置封装的方法 Expired - Fee Related CN101546718B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/024634 2008-02-01
US12/024,634 US8084299B2 (en) 2008-02-01 2008-02-01 Semiconductor device package and method of making a semiconductor device package

Publications (2)

Publication Number Publication Date
CN101546718A CN101546718A (zh) 2009-09-30
CN101546718B true CN101546718B (zh) 2012-05-02

Family

ID=40896918

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009100070408A Expired - Fee Related CN101546718B (zh) 2008-02-01 2009-02-01 半导体装置封装和制造半导体装置封装的方法

Country Status (3)

Country Link
US (2) US8084299B2 (zh)
CN (1) CN101546718B (zh)
DE (1) DE102009006826B4 (zh)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5443497B2 (ja) * 2008-09-25 2014-03-19 エルジー イノテック カンパニー リミテッド リードフレームの製造方法
CN102177579A (zh) * 2008-11-05 2011-09-07 株式会社三井高科技 半导体装置及其制造方法
US8089145B1 (en) * 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US9899349B2 (en) * 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
EP2248161B1 (en) * 2009-03-06 2019-05-01 Kaixin Inc. Leadless integrated circuit package having high density contacts
KR101753416B1 (ko) 2009-04-03 2017-07-19 카이씬, 인코포레이티드 Ｉｃ 패키지용 리드프레임 및 제조방법
TW201039420A (en) * 2009-04-17 2010-11-01 Unimicron Technology Corp Chip package structure and manufacturing method thereof
US20100314728A1 (en) * 2009-06-16 2010-12-16 Tung Lok Li Ic package having an inductor etched into a leadframe thereof
US9362138B2 (en) * 2009-09-02 2016-06-07 Kaixin, Inc. IC package and method for manufacturing the same
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
CN102117753A (zh) * 2010-01-05 2011-07-06 飞思卡尔半导体公司 封装半导体器件的方法
US8420508B2 (en) * 2010-03-17 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with bump contact on package leads and method of manufacture thereof
US8329509B2 (en) * 2010-04-01 2012-12-11 Freescale Semiconductor, Inc. Packaging process to create wettable lead flank during board assembly
CN101853832B (zh) * 2010-04-28 2011-12-07 江苏长电科技股份有限公司 基岛露出型及埋入型基岛引线框结构及其先刻后镀方法
CN101853834B (zh) * 2010-04-28 2012-01-04 江苏长电科技股份有限公司 下沉基岛及埋入型基岛引线框结构及其先刻后镀方法
CN201838585U (zh) * 2010-06-17 2011-05-18 国碁电子(中山)有限公司 堆叠式芯片封装结构及其基板
JP4929382B2 (ja) * 2010-07-13 2012-05-09 株式会社東芝 電子部品構造体及び電子機器
TW201241970A (en) * 2011-04-08 2012-10-16 Advanced Semiconductor Eng Semiconductor package with recesses in the edged leadas
CN102290396A (zh) * 2011-09-26 2011-12-21 铜陵三佳山田科技有限公司 Sma集成电路冲切成型产品及sma多排引线框架
US9576873B2 (en) * 2011-12-14 2017-02-21 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with routable trace and method of manufacture thereof
TWI446501B (zh) * 2012-01-20 2014-07-21 矽品精密工業股份有限公司 承載板、半導體封裝件及其製法
TWI476841B (zh) * 2012-03-03 2015-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9312194B2 (en) * 2012-03-20 2016-04-12 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8569112B2 (en) * 2012-03-20 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and leadframe etching and method of manufacture thereof
US8623708B1 (en) * 2012-07-05 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with grid-array mechanism and method of manufacture thereof
US9105620B1 (en) * 2012-12-27 2015-08-11 Stats Chippac Ltd. Integrated circuit packaging system with routable traces and method of manufacture thereof
CN103400806A (zh) * 2013-07-03 2013-11-20 华天科技（西安）有限公司 一种基于框架采用切割道优化技术的扁平封装件的制作工艺
CN103400812A (zh) * 2013-07-03 2013-11-20 华天科技（西安）有限公司 一种底填料填充的fcqfn封装件及其制作工艺
CN103400805A (zh) * 2013-07-03 2013-11-20 华天科技（西安）有限公司 一种基于框架采用切割刀优化技术的扁平封装件的制作工艺
US9013013B1 (en) * 2013-12-06 2015-04-21 Infineon Technologies Ag Pressure sensor package having a stacked die arrangement
US9773722B1 (en) * 2014-05-07 2017-09-26 UTAC Headquarters Pte. Ltd. Semiconductor package with partial plating on contact side surfaces
US9741642B1 (en) 2014-05-07 2017-08-22 UTAC Headquarters Pte. Ltd. Semiconductor package with partial plating on contact side surfaces
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US9905515B2 (en) 2014-08-08 2018-02-27 Mediatek Inc. Integrated circuit stress releasing structure
US9748187B2 (en) 2014-12-19 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer structure and method for wafer dicing
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US9922843B1 (en) 2015-11-10 2018-03-20 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
WO2017181399A1 (en) * 2016-04-22 2017-10-26 Texas Instruments Incorporated Improved lead frame system
JP6678506B2 (ja) * 2016-04-28 2020-04-08 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
US9972558B1 (en) 2017-04-04 2018-05-15 Stmicroelectronics, Inc. Leadframe package with side solder ball contact and method of manufacturing
JP6621781B2 (ja) * 2017-08-10 2019-12-18 太陽誘電株式会社 集合プリント基板、プリント配線板の製造方法
US10615105B2 (en) * 2017-10-20 2020-04-07 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
JP7156641B2 (ja) * 2019-02-14 2022-10-19 住友電工デバイス・イノベーション株式会社 半導体装置用のパッケージおよび半導体装置
DE102019112778B4 (de) * 2019-05-15 2023-10-19 Infineon Technologies Ag Batchherstellung von Packages durch eine in Träger getrennte Schicht nach Anbringung von elektronischen Komponenten
US11901309B2 (en) * 2019-11-12 2024-02-13 Semiconductor Components Industries, Llc Semiconductor device package assemblies with direct leadframe attachment
US11532539B2 (en) 2020-12-29 2022-12-20 Semiconductor Components Industries, Llc Semiconductor package with wettable flank

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184208A (en) 1987-06-30 1993-02-02 Hitachi, Ltd. Semiconductor device
JP2708191B2 (ja) 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
US5313102A (en) 1989-12-22 1994-05-17 Texas Instruments Incorporated Integrated circuit device having a polyimide moisture barrier coating
JP2528991B2 (ja) 1990-02-28 1996-08-28 株式会社日立製作所 樹脂封止型半導体装置及びリ―ドフレ―ム
US5214846A (en) 1991-04-24 1993-06-01 Sony Corporation Packaging of semiconductor chips
JPH06151685A (ja) 1992-11-04 1994-05-31 Mitsubishi Electric Corp Ｍｃｐ半導体装置
KR100269281B1 (ko) 1992-12-17 2000-10-16 윤종용 반도체장치
KR970010678B1 (ko) * 1994-03-30 1997-06-30 엘지반도체 주식회사 리드 프레임 및 이를 이용한 반도체 패키지
US5796159A (en) * 1995-11-30 1998-08-18 Analog Devices, Inc. Thermally efficient integrated circuit package
US5863805A (en) 1996-07-08 1999-01-26 Industrial Technology Research Institute Method of packaging semiconductor chips based on lead-on-chip (LOC) architecture
JP3006546B2 (ja) 1997-06-12 2000-02-07 日本電気株式会社 半導体装置及びリードフレーム
US6933594B2 (en) 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
FR2798226B1 (fr) * 1999-09-02 2002-04-05 St Microelectronics Sa Procede de mise en boitier d'une puce de semi-conducteur contenant des capteurs et boitier obtenu
JP2001077232A (ja) * 1999-09-06 2001-03-23 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6451627B1 (en) 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
JP3883784B2 (ja) * 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
KR100393448B1 (ko) * 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
DE10132385B4 (de) 2001-07-06 2006-07-13 Infineon Technologies Ag Elektronisches Bauteil, einen Nutzen und einen Systemträger für ein derartiges Bauteil mit auf ihren Unterseiten verteilten Außenkontakten, sowie Verfahren zur Herstellung derselben
US6482680B1 (en) 2001-07-20 2002-11-19 Carsem Semiconductor Sdn, Bhd. Flip-chip on lead frame
DE10147375B4 (de) 2001-09-26 2006-06-08 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zur Herstellung desselben
US6661087B2 (en) 2001-10-09 2003-12-09 Siliconware Precision Industries Co., Ltd. Lead frame and flip chip semiconductor package with the same
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7186588B1 (en) * 2004-06-18 2007-03-06 National Semiconductor Corporation Method of fabricating a micro-array integrated circuit package
US7943431B2 (en) * 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture

Also Published As

Publication number Publication date
DE102009006826A1 (de) 2009-08-27
US20120068323A1 (en) 2012-03-22
US20090194854A1 (en) 2009-08-06
US8084299B2 (en) 2011-12-27
DE102009006826B4 (de) 2019-02-21
US8912635B2 (en) 2014-12-16
CN101546718A (zh) 2009-09-30

Similar Documents

Publication Publication Date Title
CN101546718B (zh) 半导体装置封装和制造半导体装置封装的方法
US5661088A (en) Electronic component and method of packaging
US8487424B2 (en) Routable array metal integrated circuit package fabricated using partial etching process
CN100479135C (zh) 半导体器件及其制造方法
EP1253650B1 (en) Surface-mount type light emitting diode and method for manufacturing the same
JP3155741B2 (ja) Ｃｓｐのｂｇａ構造を備えた半導体パッケージ
CN102341899B (zh) 具有多种ic封装构造的无引线阵列塑料封装
EP0623956A2 (en) A semiconductor device having no die supporting surface and method for making the same
US7977161B2 (en) Method of manufacturing a semiconductor package using a carrier
US8314438B2 (en) Semiconductor chip assembly with bump/base heat spreader and cavity in bump
CN101383301B (zh) 形成倒装芯片突起载体式封装的方法
KR20000059861A (ko) 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
CN102386106A (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US6250606B1 (en) Substrate for semiconductor device, semiconductor device and manufacturing method thereof
KR100271639B1 (ko) 적층형 반도체패키지 및 그 제조방법 및 그 적층방법
US11710684B2 (en) Package with separate substrate sections
US20220270960A1 (en) Open-Cavity Package for Chip Sensor
KR100390453B1 (ko) 반도체 패키지 및 그 제조방법
KR100473336B1 (ko) 반도체패키지
KR100285663B1 (ko) 패키지화된집적회로소자및그제조방법
KR100308116B1 (ko) 칩스케일반도체패키지및그제조방법_
KR100668817B1 (ko) 반도체 패키지의 제조 방법
KR100356808B1 (ko) 칩 스케일 반도체 패키지
JP2001127196A (ja) ターミナルランドフレーム及びその製造方法、並びに樹脂封止型半導体装置及びその製造方法
JPH07326690A (ja) 半導体装置用パッケージおよび半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120502

Termination date: 20200201

CF01 Termination of patent right due to non-payment of annual fee