CN201838585U - 堆叠式芯片封装结构及其基板 - Google Patents

堆叠式芯片封装结构及其基板 Download PDF

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CN201838585U
CN201838585U CN2010202276672U CN201020227667U CN201838585U CN 201838585 U CN201838585 U CN 201838585U CN 2010202276672 U CN2010202276672 U CN 2010202276672U CN 201020227667 U CN201020227667 U CN 201020227667U CN 201838585 U CN201838585 U CN 201838585U
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bearing seat
pin
load bearing
chip
substrate
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杨望来
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- Core Of Electronic Science And Technology (zhongshan) Co Ltd
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CN2010202276672U priority Critical patent/CN201838585U/zh
Priority to US13/069,390 priority patent/US8587100B2/en
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Publication of CN201838585U publication Critical patent/CN201838585U/zh
Priority to US13/875,331 priority patent/US9379505B2/en
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Abstract

一种堆叠式芯片封装结构，包括基板、第一芯片、第二芯片及封胶体。所述基板包括多个引脚、承载座、收容部和凹陷部，所述承载座位于所述基板的中间区域。每一个引脚的顶面高于所述承载座的顶面。所述收容部位于所述承载座的上方并被所述引脚环绕。所述凹陷部位于所述引脚和所述承载座的底面。所述第一芯片固定于所述承载座并隐藏于所述收容部中。所述第二芯片固定于所述第一芯片。所述连接线电性连接所述第二芯片和所述引脚。所述封胶体将所述基板、所述连接线、所述第一芯片及所述第二芯片封装于其内，并填充所述凹陷部。本实用新型提供的堆叠式芯片封装结构，通过将第一芯片隐藏于基板的收容部中，缩小了产品体积。

Description

堆叠式芯片封装结构及其基板
技术领域
本实用新型涉及半导体封装技术，特别涉及一种堆叠式芯片封装结构。
背景技术
现有的堆叠式芯片封装结构，是将第一芯片堆叠于基板的顶面再将第二芯片堆叠于第一芯片的顶面。然而，这种封装结构体积较大，不能满足电子产品小型化的发展趋势，且成本较高。
实用新型内容
有鉴于此，需提供一种能减少体积的堆叠式芯片封装结构。
还需提供一种能减少上述堆叠式芯片封装结构体积的基板。
一种堆叠式芯片封装结构，包括基板、第一芯片、第二芯片及封胶体。所述基板包括多个引脚、承载座、收容部和凹陷部，所述承载座位于所述基板的中间区域。每一个引脚的顶面高于所述承载座的顶面。所述收容部位于所述承载座的上方并被所述引脚环绕。所述凹陷部位于所述引脚和承载座的底面。所述第一芯片固定于所述承载座并隐藏于所述收容部中。所述第二芯片固定于所述第一芯片。所述连接线电性连接所述第二芯片和所述引脚。所述封胶体将所述基板、所述连接线、所述第一芯片及所述第二芯片封装于其内，并填充所述凹陷部。
一种基板，用于承载至少一个芯片。所述基板包括多个引脚、承载座、收容部和凹陷部，所述承载座位于所述基板的中间区域。每一个引脚的顶面高于所述承载座的顶面。所述收容部位于所述承载座的上方并被所述引脚环绕。所述凹陷部位于所述引脚和所述承载座的底面。
优选地，所述基板为框架结构，所述框架结构包括多个加强肋，所述加强肋与所述承载座连接。
优选地，所述引脚相互独立并成排分布于所述加强肋之间，每一排至少有一个引脚的长度少于其它引脚的长度。
优选地，每一个引脚呈台阶状，每一排至少有一个引脚包括承接部、连接部及外缘部，所述连接部的高度大于所述承接部的高度，所述外缘部的顶面和底面分别与所述承接部的顶面和底面平齐。
优选地，所述承接部的顶面和所述承载座的顶面平齐并与所述承载座之间形成间隙。
本实用新型的堆叠式芯片封装结构，通过将第一芯片隐藏于基板的收容部中，缩小了产品体积。
附图说明
图1是本实用新型的堆叠式芯片封装结构的组装剖视示意图。
图2是图1中无封胶体的组装剖视示意图。
图3是本实用新型的基板的立体图。
主要元件符号说明
堆叠式芯片封装结构            100
封胶体                        10
基板                          20
本体                          21
承载座                        23
引脚                          25
承接部                        252
连接部                        254
外缘部                        256
加强肋                        26
收容部                        27
凹陷部                        28
第一芯片                      30
锡球                          32
第二芯片                      40
连接线                            50
粘着剂                            60
具体实施方式
图1是本实用新型的堆叠式芯片封装结构100的剖视示意图。本实用新型的堆叠式芯片封装结构100包括封胶体10、基板20、第一芯片30、第二芯片40及多个连接线50。
请参照图2和图3，基板20为框架结构，其包括本体21、承载座23、多个引脚25、多个加强肋26、收容部27及凹陷部28。承载座23位于基板20的中间区域并通过所述加强肋26与本体21相连，从而增加承载座23的稳定性并避免偏移。
所述引脚25相互独立并成排分布于所述加强肋26之间，每一排至少有一个引脚25的长度少于其它的引脚25的长度。在本实施方式中，每一排包括三个引脚25，其中中间引脚25的长度小于另两个引脚25的长度。
在本实施方式中，每一排至少有一个引脚25包括承接部252、连接部254及外缘部256，连接部254的高度大于承接部252的高度。连接部254的顶面高于承载座23的顶面。承接部252的顶面和底面分别与承载座23的顶面和的底面平齐，并与承载座23之间形成间隙。外缘部256的顶面和底面分别与承接部252的顶面和底面平齐，并分别与本体21的的顶面和底面平齐。每一排的其它引脚25不包括承接部252。
具有承接部252的每一个引脚25的承接部252和连接部254的顶面和底面均被半蚀刻，形成台阶状。无承接部252的每一个引脚25的连接部254的顶面和底面均被半蚀刻，亦形成台阶状。
在其它实施方式中，每一个引脚25包括承接部252、连接部254及外缘部256，均为台阶状。
因连接部254的顶面高于承载座23的顶面，从而在承载座23的上方形成收容部27，即收容部27位于承载座23的上方并被连接部254环绕。
凹陷部28通过半蚀刻方式形成于承载座23和所述引脚25的底面。形成于承载座23的凹陷部28位于承载座23的底面四周，形成于所述引脚25的凹陷部28位于承接部252和外缘部256的底面。
基板20的背面还粘着胶膜(未图示)，用于固定承载座23和所述引脚25，并防止后续封胶时的溢胶问题。
第一芯片30包括多个锡球32，通过所述锡球32电性连接于承载座23和所述引脚25的承接部252。组装后，第一芯片30的顶面与连接部254的顶面平齐，即第一芯片30隐藏于基板20的收容部27中。
第二芯片40通过粘着剂60固定于第一芯片30。
连接线50电性连接第二芯片40和所述引脚25的连接部254，这样第二芯片40便与基板20电性连接。在本实施方式中，连接线50为金线。
封胶体10将连接线50、第一芯片30、第二芯片40及基板20封装于内，封胶体10的外缘与基板20的外缘平齐，且封胶体10填充凹陷部28、第一芯片30的锡球32之间的间隙、承载座23与每一个引脚25之间的间隙及基板20的顶面，且基板20的各引脚25及承载座23的底面非凹陷部28部分外露于封胶体10底面外形成各自独立不相连状，待封胶体10固化后，撕去粘贴于基板20背面的胶膜，即形成堆叠式芯片封装结构100。在本实施方式中，封胶体10为黑胶。
因第一芯片30隐藏于基板20的收容部27中，从而减少了堆叠式芯片封装结构100的高度，即缩小了产品体积并节约了成本。
因封胶体10填充凹陷部28、第一芯片30的锡球32之间的间隙、承载座23与每一个引脚25之间的间隙，从而增进基板20与封胶体10之间的连接力，提高水气渗入堆叠式芯片封装结构100内部的困难度，进而确保堆叠式芯片封装结构100具有良好的可靠度。

Claims (10)

1.一种堆叠式芯片封装结构，包括基板、第一芯片、第二芯片及封胶体，其特征在于：
所述基板包括多个引脚、承载座、收容部和凹陷部，所述承载座位于所述基板的中间区域，每一个引脚的顶面高于所述承载座的顶面，所述收容部位于所述承载座的上方并被所述引脚环绕，所述凹陷部位于所述引脚和所述承载座的底面；
所述第一芯片固定于所述承载座并隐藏于所述收容部中；
所述第二芯片固定于所述第一芯片；
所述连接线电性连接所述第二芯片和所述引脚；及
所述封胶体将所述基板、所述连接线、所述第一芯片及所述第二芯片封装于其内；
其中，所述封胶体填充所述凹陷部。
2.如权利要求1所述的堆叠式芯片封装结构，其特征在于，所述基板为框架结构，所述框架结构包括多个加强肋，所述加强肋与所述承载座连接。
3.如权利要求2所述的堆叠式芯片封装结构，其特征在于，所述引脚相互独立并成排分布于所述加强肋之间，每一排至少有一个引脚的长度少于其它引脚的长度。
4.如权利要求3所述的堆叠式芯片封装结构，其特征在于，每一个引脚呈台阶状，每一排至少有一个引脚包括承接部、连接部及外缘部，所述连接部的高度大于所述承接部的高度，所述外缘部的顶面和底面分别与所述承接部的顶面和底面平齐。
5.如权利要求4所述的堆叠式芯片封装结构，其特征在于，所述承接部的顶面和所述承载座的顶面平齐并与所述承载座之间形成间隙。
6.一种基板，用于承载至少一个芯片，其特征在于：所述基板包括多个引脚、承载座、收容部和凹陷部，所述承载座位于所述基板的中间区域，每一个引脚的顶面高于所述承载座的顶面，所述收容部位于所述承载座的上方并被所述引脚环绕，所述凹陷部位于所述引脚和承载座的底面。
7.如权利要求6所述的基板，其特征在于，所述基板为框架结构，所述框架结构包括多个加强肋，所述加强肋与所述承载座连接。
8.如权利要求7所述的基板，其特征在于，所述引脚相互独立并成排分布于所述加强肋之间，每一排至少有一个引脚的长度少于其它引脚的长度。
9.如权利要求8所述的基板，其特征在于，每一个引脚呈台阶状，每一排至少有一个引脚包括承接部、连接部及外缘部，所述连接部的高度大于所述承接部的高度，所述外缘部的顶面和底面分别与所述承接部的顶面和底面平齐。
10.如权利要求9所述的基板，其特征在于，所述承接部的顶面和所述承载座的顶面平齐并与所述承载座之间形成间隙。
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