CN201681868U - 芯片倒装封装结构 - Google Patents

芯片倒装封装结构 Download PDF

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CN201681868U
CN201681868U CN 201020177746 CN201020177746U CN201681868U CN 201681868 U CN201681868 U CN 201681868U CN 201020177746 CN201020177746 CN 201020177746 CN 201020177746 U CN201020177746 U CN 201020177746U CN 201681868 U CN201681868 U CN 201681868U
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metal
plastic packaging
metal leg
leg
chip
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王新潮
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

本实用新型涉及一种芯片倒装封装结构，包括若干金属脚(1)，在所述金属脚(1)的正面和背面分别设置有第一金属层(3)和第二金属层(4)，在金属脚(1)正面通过金属粘结物质(5)设置有芯片(6)，在所述金属脚(1)的上部以及芯片(6)外包封有填料塑封料(7)，在所述金属脚(1)外围以及金属脚(1)与金属脚(1)之间的区域嵌置无填料塑封料(2)，所述无填料塑封料(2)将金属脚(1)的下部连接成一体，且使所述金属脚(4)背面尺寸小于金属脚(4)正面尺寸，形成上大下小的金属脚(4)结构。本实用新型的有益效果是：可降低封装成本，可选择的产品种类广，芯片倒装的质量与产品可靠度的稳定性好，塑封体与金属脚的束缚能力大。

Description

芯片倒装封装结构
(一)技术领域
本实用新型涉及一种芯片倒装封装结构。属于半导体封装技术领域。
(二)背景技术
传统的芯片倒装封装结构主要有二种：
第一种：
采用金属基板的正面进行化学蚀刻及表面电镀层后，在金属基板的背面贴上一层耐高温的胶膜形成可以进行封装过程的引线框载体(如图2所示)。
第二种：
采用金属基板的正面进行化学蚀刻及表面电镀层后，即完成引线框的制作(如图3所示)。而引线框的背面则在封装过程中再进行背面蚀刻。
而上述的二种引线框在封装过程中存在了以下的不足点：
第一种：
1)此种的引线框架因背面必须要贴上一层昂贵可抗高温的胶膜。所以直接增加了高昂的成本。
2)也因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜，所以在封装过程中的装片工艺只能使用导电或是不导电的树脂工艺，而完全不能采用共晶工艺以及软焊料的工艺进行装片，所以可选择的产品种类就有较大的局限性。
3)又因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜，而在封装过程中的芯片倒装键合工艺中，因为此可抗高温的胶膜是软性材质，所以造成了芯片倒装键合参数的不稳定，严重的影响了芯片倒装的质量与产品可靠度的稳定性。
4)再因为此种的引线框架的背面必须要贴上一层可抗高温的胶膜，而在封装过程中的塑封工艺过程，因为塑封的高压关系很容易造成引线框架与胶膜之间渗入塑封料，而将原本应属金属脚是导电的型态因为渗入了塑封料反而变成了绝缘脚(如图4所示)。
第二种：
此种的引线框架结构在金属基板正面进行了半蚀刻工艺，虽然可以解决第一种引线框架的问题，但是因为只在金属基板正面进行了半蚀刻工作，而在塑封过程中塑封料只有包覆住半只脚的高度，所以塑封体与金属脚的束缚能力就变小了，如果塑封体贴片到PCB板上不是很好时，再进行返工重贴，就容易产生掉脚的问题(如图5所示)。
尤其塑封料的种类是采用有填料时候，因为材料在生产过程的环境与后续表面贴装的应力变化关系，会造成金属与塑封料产生垂直型的裂缝，其特性是填料比例越高则越硬越脆越容易产生裂缝。
(三)发明内容
本实用新型的目的在于克服上述不足，提供一种降低封装成本、可选择的产品种类广、芯片倒装的质量与产品可靠度的稳定性好、塑封体与金属脚的束缚能力大的芯片倒装封装结构。
本实用新型的目的是这样实现的：一种芯片倒装封装结构，包括若干金属脚，在所述金属脚的正面和背面分别设置有第一金属层和第二金属层，在金属脚正面通过金属粘结物质设置有芯片，在所述金属脚的上部以及芯片外包封有填料塑封料，在所述金属脚外围以及金属脚与金属脚之间的区域嵌置无填料塑封料，所述无填料塑封料将金属脚的下部连接成一体，且使所述金属脚背面尺寸小于金属脚正面尺寸，形成上大下小的金属脚结构。
本实用新型的有益效果是：
1)此种的引线框的背面不须要贴上一层昂贵可抗高温的胶膜。所以直接降低了高昂的成本。
2)也因为此种的引线框架的背面不须要贴上一层可抗高温的胶膜，所以在封装过程中的装片工艺除了能使用导电或是不导电的树脂工艺外，还能采用共晶工艺以及软焊料的工艺进行装片，所以可选择的产品种类就广。
3)又因为此种的引线框架的背面不须要贴上一层可抗高温的胶膜，确保了芯片倒装键合参数的稳定性，保证了芯片倒装的质量与产品可靠度的稳定性。
4)再因为此种的引线框架不须要贴上一层可抗高温的胶膜，而在封装过程中的塑封工艺过程，完全不会造成引线框与胶膜之间渗入塑封料。
5)由于在所述金属脚与金属脚间的区域嵌置有无填料的软性填缝剂，该无填料的软性填缝剂与在塑封过程中的常规有填料塑封料一起包覆住整个金属脚的高度，所以塑封体与金属脚的束缚能力就变大了，不会再有产生掉脚的问题。
(四)附图说明
图1为本实用新型芯片倒装封装结构示意图。
图2为以往在金属基板的背面贴上一层耐高温的胶膜图作业。
图3为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。
图4为以往形成绝缘脚示意图。
图5为以往形成的掉脚图。
图中附图标记：
金属脚1、无填料塑封料2、第一金属层3、第二金属层4、金属粘结物质5、芯片6、有填料塑封料7。
(五)具体实施方式
图1为本实用新型芯片倒装封装结构示意图。由图1可以看出，本实用新型芯片倒装封装结构，包括若干金属脚1，在所述金属脚1的正面和背面分别设置有第一金属层3和第二金属层4，在金属脚1正面通过金属粘结物质5设置有芯片6，在所述金属脚1的上部以及芯片6外包封有填料塑封料7，在所述金属脚1外围以及金属脚1与金属脚1之间的区域嵌置无填料塑封料2，所述无填料塑封料2将金属脚1的下部连接成一体，且使所述金属脚4背面尺寸小于金属脚4正面尺寸，形成上大下小的金属脚4结构。所述金属粘结物质5可以采用锡金属、金质金属、镍金金属或钛镍金金属。

Claims (1)

1.一种芯片倒装封装结构，包括若干金属脚(1)，在所述金属脚(1)的正面和背面分别设置有第一金属层(3)和第二金属层(4)，在金属脚(1)正面通过金属粘结物质(5)设置有芯片(6)，在所述金属脚(1)的上部以及芯片(6)外包封有填料塑封料(7)，其特征在于：在所述金属脚(1)外围以及金属脚(1)与金属脚(1)之间的区域嵌置无填料塑封料(2)，所述无填料塑封料(2)将金属脚(1)的下部连接成一体，且使所述金属脚(4)背面尺寸小于金属脚(4)正面尺寸，形成上大下小的金属脚(4)结构。
CN 201020177746 2010-04-26 2010-04-26 芯片倒装封装结构 Expired - Lifetime CN201681868U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856289A (zh) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 单芯片倒装先蚀刻后封装基岛露出封装结构及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856289A (zh) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 单芯片倒装先蚀刻后封装基岛露出封装结构及其制造方法
CN102856289B (zh) * 2012-05-09 2014-10-29 江苏长电科技股份有限公司 单芯片倒装先蚀刻后封装基岛露出封装结构及其制造方法

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