CN202259265U - 新型无基岛预填塑封料引线框结构 - Google Patents

新型无基岛预填塑封料引线框结构 Download PDF

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Publication number
CN202259265U
CN202259265U CN 201120339947 CN201120339947U CN202259265U CN 202259265 U CN202259265 U CN 202259265U CN 201120339947 CN201120339947 CN 201120339947 CN 201120339947 U CN201120339947 U CN 201120339947U CN 202259265 U CN202259265 U CN 202259265U
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China
Prior art keywords
lead frame
plastic packaging
packaging material
frame structure
pin
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CN 201120339947
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English (en)
Inventor
梁志忠
谢洁人
吴昊
耿丛正
夏文斌
郁科峰
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型涉及一种引线框结构，具体涉及一种新型无基岛预填塑封料引线框结构，属于半导体封装技术领域。它包括引脚（1），所述引脚（1）与引脚（1）之间填充有塑封料（2），其特征在于：所述引脚（1）正面长度小于背面长度，形成上小下大的引脚结构。本实用新型涉及一种新型无基岛预填塑封料引线框结构，其引脚正面长度小于背面长度，形成上小下大的引脚结构，能够适用于封装尺寸较大的芯片，使芯片与引脚不易产生短路，有利于提高封转芯片密度。

Description

新型无基岛预填塑封料引线框结构
技术领域
本实用新型涉及一种引线框结构，具体涉及一种新型无基岛预填塑封料引线框结构，属于半导体封装技术领域。
背景技术
以往的四面扁平无引脚封装（QFN）引线框（如图1所示），通常情况下在封装时要求芯片尺寸必须比基岛小，以防止装片时装片胶（导电或不导电）沾污引脚（如图2所示），因此限制了封装芯片的尺寸，芯片密度（chip scale）较低。
发明内容
本实用新型的目的在于克服上述不足，提供一种新型无基岛预填塑封料引线框结构，能够适用于大尺寸芯片的封装，有利于提高芯片的封装密度。
本实用新型的目的是这样实现的：一种新型无基岛预填塑封料引线框结构，它包括引脚，所述引脚与引脚之间填充有塑封料，其特点是：所述引脚正面长度小于背面长度，形成上小下大的引脚结构。
与现有技术相比，本实用新型的有益效果是： 
本实用新型涉及一种新型无基岛预填塑封料引线框结构，其引脚正面长度小于背面长度，形成上小下大的引脚结构，能够适用于封装尺寸较大的芯片，使芯片装片胶（导电或不导电）不易沾污引脚，有利于提高封转芯片密度。  
附图说明
图1为现有无基岛预填塑封料引线框的结构示意图。
图2为现有无基岛预填塑封料引线框在封装大尺寸芯片时产生短路的示意图。
图3为本实用新型无基岛预填塑封料引线框的结构示意图。
图4为本实用新型无基岛预填塑封料引线框封装大尺寸芯片的示意图。
其中：
引脚1
塑封料2
芯片3
导电胶4。
具体实施方式
参见图3~图4，本实用新型一种新型无基岛预填塑封料引线框结构，它包括引脚1，所述引脚1与引脚1之间填充有塑封料2，所述引脚1正面长度小于背面长度，形成上小下大的引脚结构。

Claims (1)

1.一种新型无基岛预填塑封料引线框结构，它包括引脚（1），所述引脚（1）与引脚（1）之间填充有塑封料（2），其特征在于：所述引脚（1）正面长度小于背面长度，形成上小下大的引脚结构。
CN 201120339947 2011-09-13 2011-09-13 新型无基岛预填塑封料引线框结构 Expired - Lifetime CN202259265U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102324411A (zh) * 2011-09-13 2012-01-18 江苏长电科技股份有限公司 新型无基岛预填塑封料引线框结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102324411A (zh) * 2011-09-13 2012-01-18 江苏长电科技股份有限公司 新型无基岛预填塑封料引线框结构
WO2013037188A1 (en) * 2011-09-13 2013-03-21 Jiangsu Changjiang Electronics Technology Co. Ltd Pre-encapsulated islandless lead frame structures and manufacturing method

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Address after: Tianjin City, Tianjin free trade zone (Dongjiang Bonded Port) No. 6865 North Road, 1-1-1802-7 financial and trade center of Asia

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Address before: 214434 Binjiang Middle Road, Jiangyin Development Zone, Jiangsu, China, No. 275, No.

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Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd.

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Address before: 1-1-1802-7, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin pilot free trade zone (Dongjiang Free Trade Port Area), Tianjin

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