CN208674105U - 引线框架及采用该引线框架的封装体 - Google Patents

引线框架及采用该引线框架的封装体 Download PDF

Info

Publication number
CN208674105U
CN208674105U CN201821511399.XU CN201821511399U CN208674105U CN 208674105 U CN208674105 U CN 208674105U CN 201821511399 U CN201821511399 U CN 201821511399U CN 208674105 U CN208674105 U CN 208674105U
Authority
CN
China
Prior art keywords
lead frame
routing area
area
pin
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201821511399.XU
Other languages
English (en)
Inventor
阳小芮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Kaihong Sci & Tech Electronic Co Ltd
Shanghai Kaihong Electronic Co Ltd
Original Assignee
Shanghai Kaihong Sci & Tech Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Kaihong Sci & Tech Electronic Co Ltd filed Critical Shanghai Kaihong Sci & Tech Electronic Co Ltd
Priority to CN201821511399.XU priority Critical patent/CN208674105U/zh
Application granted granted Critical
Publication of CN208674105U publication Critical patent/CN208674105U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型提供一种引线框架及采用该引线框架的封装体,所述引线框架包括至少一基岛及至少一个设置在所述基岛周围的引脚,至少一个所述引脚的上表面具有一打线区及设置在所述打线区外围的平台区,所述打线区为引脚与导电引线连接的区域,所述打线区的高度低于所述平台区的高度。本实用新型的优点在于,打线区的高度低于所述平台区的高度,则在后续封装工艺中,相当于将导电引线深埋在塑封料中,更加有利于导电引线的固定,且所述打线区能够起到锁模的作用,进一步加强引线框架与塑封料的结合,提高封装体的可靠性。

Description

引线框架及采用该引线框架的封装体
技术领域
本实用新型涉及半导体封装领域,尤其涉及一种引线框架及采用该引线框架的封装体。
背景技术
现在基本主流IC类零件都是使用QFN(Quad Flat No-lead Package,方形扁平无引脚封装)的无引脚的封装。图1是现有的QFN封装体1内部结构示意图,请参阅图1,所述QFN封装体1包括一个基岛10及围绕所述基岛10设置的多个引脚11,在所述基岛10上设置有芯片12,芯片12与引脚11之间通过导电引线13连接。由于目前的电子产品对可靠性的要求越来越高,如图1所示的一些常规设计的封装体产品已经无法满足用户的需求。为了增强QFN的封装可靠性,需要对框架设计及工艺等进行创新设计,以满足产品要求。
实用新型内容
本实用新型所要解决的技术问题是,提供一种引线框架及采用该引线框架的封装体,其能够加强引线框架与塑封体的结合,提高封装体的可靠性。
为了解决上述问题,本实用新型提供了一种引线框架,包括至少一基岛及至少一个设置在所述基岛周围的引脚,至少一个所述引脚的上表面具有一打线区及设置在所述打线区外围的平台区,所述打线区为引脚与导电引线连接的区域,所述打线区的高度低于所述平台区的高度。
在一实施例中,所述平台区包围所述打线区。
在一实施例中,所述平台区半包围所述打线区,形成钳形结构。
在一实施例中,所述平台区的外侧面向外突出。
在一实施例中,所述基岛的边缘呈曲线形状。
在一实施例中,所述基岛的边缘呈波浪形状。
本发明还提供一种封装体,其包括一上述的引线框架、至少一芯片及一塑封所述引线框架及所述芯片的塑封体,所述芯片设置在所述基岛上,一导电引线的一端连接至所述引脚的打线区,另一端连接至芯片,所述塑封体填充所述打线区。
本实用新型的优点在于,本实用新型引线框架的打线区的高度低于所述平台区的高度,则在后续封装工艺中,相当于将导电引线深埋在塑封料中,更加有利于导电引线的固定,且所述打线区能够起到锁模的作用,进一步加强引线框架与塑封料的结合,提高封装体的可靠性。
附图说明
图1是现有的QFN封装体内部结构示意图;
图2是本实用新型引线框架的一个实施例的俯视结构示意图;
图3是本实用新型引线框架的一个实施例的侧视结构示意图;
图4是本实用新型引线框架的另一个实施例的俯视结构示意图;
图5是本实用新型封装体的俯视结构示意图;
图6是本实用新型封装体的侧视结构示意图。
具体实施方式
下面结合附图对本实用新型提供的引线框架及采用该引线框架的封装体的具体实施方式做详细说明。
图2是本实用新型引线框架20的一个实施例的俯视结构示意图,图3是本实用新型引线框架20的一个实施例的侧视结构示意图。请参阅图2及图3,所述引线框架20包括至少一基岛201及至少一个设置在所述基岛201周围的引脚202。其中,多个所述引线框架20可形成一引线框架阵列。在本说明书中,仅以一个引线框架为例进行说明。
在至少一个所述引脚202的上表面具有一打线区203及设置在所述打线区203外围的平台区204。其中,在附图中,采用填充线示意性标示出打线区203。在本实施例中,在所有引脚202的上表面均设置打线区203及设置在所述打线区203外围的平台区204。在本实用新型其他实施例中,也可以在间隔的引脚202的上表面设置所述打线区203及所述平台区204。图4是本实用新型引线框架的另一个实施例的俯视结构示意图。请参阅图4,在本实施中,在间隔的引脚202的上表面设置所述打线区203及所述平台区204。
所述打线区203为所述引脚202与导电引线50(绘示于图5中)连接的区域,即在后续封装工艺中,导电引线50与所述引脚202的连接处位于所述打线区203。所述打线区203的高度低于所述平台区204的高度。具体地说,打线区203相对于所述平台区204向下凹陷。所述平台区204的高度相当于
所述平台区204可以半包围所述打线区203,也可以全包围所述打线区203。例如,在本实施例中,所述平台区204半包围所述打线区203,形成钳形结构;而在其他实施例中,所述平台区204全包围所述打线区203,即所述平台区204形成环形凸起,所述打线区203位于所述环形凸起的中心,所述打线区203的高度低于所述平台区204的高度。
本实用新型引线框架的打线区203的高度低于所述平台区204的高度,则在后续封装工艺中,相当于将导电引线深埋在塑封料中,更加有利于导电引线的固定,且所述打线区203能够起到锁模的作用,进一步加强引线框架与塑封料的结合,提高封装体的可靠性。进一步,所述平台区204的外侧面向外凸出,使得所述平台区204的外边缘形成曲线形状,以加强与塑封料的结合,进一步提高可靠性。
进一步,所述基岛201的边缘呈曲线形状,其作用也在于加强引线框架与塑封料的结合,提高封装体的可靠性。具体地说,在本实施例中,所述基岛201的边缘呈波浪形状。
本实用新型还提供一种封装体。所述封装体采用上述的引线框架。图5是本实用新型封装体的俯视结构示意图,图6是本实用新型封装体的侧视结构示意图,其中,为了清楚说明本实用新型技术方案,在图5中,示意性地绘示封装体内部结构。
请参阅图5及图6,所述封装体5包括一引线框架20、至少一芯片30及一塑封所述引线框架20及所述芯片30的塑封体40。在本实施例中,仅绘示一个芯片30。所述芯片30设置在所述基岛201上。一导电引线50的一端连接至所述引脚202的打线区203。另一端连接至芯片30。所述塑封体40覆盖所述引线框架,且所述塑封体填充所述打线区203。
在本实用新型的封装体中,由于所述打线区203的高度低于所述平台区204的高度,则所述塑封体40填充进所述打线区203后,所述打线区203能够起到锁模的作用,加强所述引线框架20与塑封体40的结合,提高封装体5的可靠性。进一步,所述基岛201的边缘呈曲线形状,其作用也在于加强引线框架20与塑封体40的结合,提高封装体5的可靠性。
以上所述仅是本实用新型的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本实用新型原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本实用新型的保护范围。

Claims (7)

1.一种引线框架,其特征在于,包括至少一基岛及至少一个设置在所述基岛周围的引脚,至少一个所述引脚的上表面具有一打线区及设置在所述打线区外围的平台区,所述打线区为引脚与导电引线连接的区域,所述打线区的高度低于所述平台区的高度。
2.根据权利要求1所述的引线框架,其特征在于,所述平台区包围所述打线区。
3.根据权利要求1所述的引线框架,其特征在于,所述平台区半包围所述打线区,形成钳形结构。
4.根据权利要求1所述的引线框架,其特征在于,所述平台区的外侧面向外突出。
5.根据权利要求1所述的引线框架,其特征在于,所述基岛的边缘呈曲线形状。
6.根据权利要求5所述的引线框架,其特征在于,所述基岛的边缘呈波浪形状。
7.一种封装体,其特征在于,包括一权利要求1~6任意一项所述的引线框架、至少一芯片及一塑封所述引线框架及所述芯片的塑封体,所述芯片设置在所述基岛上,一导电引线的一端连接至所述引脚的打线区,另一端连接至芯片,所述塑封体填充所述打线区。
CN201821511399.XU 2018-09-14 2018-09-14 引线框架及采用该引线框架的封装体 Active CN208674105U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201821511399.XU CN208674105U (zh) 2018-09-14 2018-09-14 引线框架及采用该引线框架的封装体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201821511399.XU CN208674105U (zh) 2018-09-14 2018-09-14 引线框架及采用该引线框架的封装体

Publications (1)

Publication Number Publication Date
CN208674105U true CN208674105U (zh) 2019-03-29

Family

ID=65842126

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201821511399.XU Active CN208674105U (zh) 2018-09-14 2018-09-14 引线框架及采用该引线框架的封装体

Country Status (1)

Country Link
CN (1) CN208674105U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119396A (zh) * 2018-09-14 2019-01-01 上海凯虹科技电子有限公司 引线框架及采用该引线框架的封装体

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119396A (zh) * 2018-09-14 2019-01-01 上海凯虹科技电子有限公司 引线框架及采用该引线框架的封装体

Similar Documents

Publication Publication Date Title
CN204102862U (zh) 一种基于腔体技术多芯片叠加封装装置
CN208674105U (zh) 引线框架及采用该引线框架的封装体
CN101609819B (zh) 导线架芯片封装结构及其制造方法
CN209119087U (zh) 引线框架及采用该引线框架的封装体
CN208596671U (zh) 大功率封装体
CN109119396A (zh) 引线框架及采用该引线框架的封装体
US7812430B2 (en) Leadframe and semiconductor package having downset baffle paddles
CN106409805A (zh) 一种五引脚ic结构
CN203733785U (zh) 一种具有改进型封装结构的半导体器件
US8957510B2 (en) Using an integrated circuit die configuration for package height reduction
CN105990298A (zh) 一种芯片封装结构及其制备方法
CN208336209U (zh) 半导体封装件及其使用的导线框架条
CN203812871U (zh) 多芯片dip封装结构
CN211480018U (zh) 半导体导线架结构及其封装结构
CN209418493U (zh) 一种引线框架
CN207217519U (zh) 一种封装引线框架
CN207398115U (zh) 一种改善多芯片堆叠装片的结构
CN202434503U (zh) 一种dip10集成电路器件及引线框、引线框矩阵
CN206685373U (zh) 贴片封装半导体的框架
CN205376512U (zh) 导线架及四方扁平无外引脚封装结构
CN206349352U (zh) 一种封装导线架结构
CN110504232A (zh) 四方扁平无引脚封装及使其能够被切割的方法
CN110600447A (zh) 一种新型引线框架结构及封装结构
CN105355619B (zh) 导线框架条
CN216288426U (zh) 一种高效高可靠性sot23-6封装mosfet引线框架结构

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant