CN207398115U - 一种改善多芯片堆叠装片的结构 - Google Patents
一种改善多芯片堆叠装片的结构 Download PDFInfo
- Publication number
- CN207398115U CN207398115U CN201721251162.8U CN201721251162U CN207398115U CN 207398115 U CN207398115 U CN 207398115U CN 201721251162 U CN201721251162 U CN 201721251162U CN 207398115 U CN207398115 U CN 207398115U
- Authority
- CN
- China
- Prior art keywords
- chip
- lower layer
- work
- base material
- frame base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Landscapes
- Materials For Medical Uses (AREA)
Abstract
本实用新型一种改善多芯片堆叠装片的结构,它包括框架基材(1),所述框架基材(1)正面设置有下层芯片(2)和“工”字型支架(6),所述“工”字型支架(6)正面设置有上层芯片(3),所述框架基材(1)、下层芯片(2)及上层芯片(3)之间均通过焊线(7)相连接,所述下层芯片(2)、上层芯片(3)、“工”字型支架(6)和焊线(7)外围包封有塑封料(8)。本实用新型一种改善多芯片堆叠装片的结构,它在同样大小的封装内尽可能的增加空间利用率,可以更方便的布局,避免上层芯片部分区域悬空设置,避免下层芯片部分打线区域被上层芯片遮盖的问题。
Description
技术领域
本实用新型涉及一种改善多芯片堆叠装片的结构,属于半导体封装技术领域。
背景技术
目前半导体产品的发展趋势就是小型化,密集化,在尽可能小的区域内安装尽可能多的芯片,减少空间占用,提高空间利用率,且客户需求的封装一般都有尺寸要求,因此产品的封装尺寸是受限制的,同样的的封装尺寸,多芯片堆叠装片有效的减小了封装尺寸,满足现在的发展趋势,现有对多芯片装片存在一些问题,目前有以下几种:
1、多芯片装片时,装片区域不够大无法满足条件,此时需重新设计芯片或框架,且不一定能满足所需要求,如图1、图2所示,此时因装片区域不足迫使芯片堆叠布置,上层芯片部分区域悬空(圆圈位置),部分打线区域悬空,影响打线制程,使得上层芯片悬空打线区域没有足够的强度造成芯片应力断裂的问题;
2、芯片堆叠装片时,由于受尺寸的限制以及下层芯片与上层芯片尺寸接近的等因素影响,下层芯片的部分打线区域容易被上层芯片的装片所遮盖。
实用新型内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种改善多芯片堆叠装片的结构,在有限的空间内,它可以有效的增强多芯片装片的能力,增加将空间利用率,避免悬空打线区域因没有足够的强度造成芯片断裂的问题,同时也避免因空间不足造成下层芯片的部分打线区域容易被上层芯片的装片遮盖的问题。
本实用新型解决上述问题所采用的技术方案为:一种改善多芯片堆叠装片的结构,它包括框架基材,所述框架基材正面通过装片胶设置有下层芯片,所述框架基材正面通过贴膜设置有“工”字型支架,所述“工”字型支架正面通过装片胶设置有上层芯片,所述框架基材、下层芯片及上层芯片之间均通过焊线相连接,所述下层芯片、上层芯片、“工”字型支架和焊线外围包封有塑封料。
所述“工”字型支架为上大下小的“工”字型支架。
所述下层芯片的部分区域及部分焊线容置于“工”字型支架下面的空间。
所述下层芯片有多个。
与现有技术相比,本实用新型的优点在于:
本实用新型一种改善多芯片堆叠装片的结构,提高了框架基材的利用率,可以更方便布局,一方面避免上层芯片悬空打线区域因没有足够的强度支撑造成芯片应力断裂的问题,同时也避免因空间不足造成下层芯片的部分打线区域容易被上层芯片的装片遮盖的问题。
附图说明
图1为传统多芯片装片结构的示意图。
图2为传统多芯片装片结构的另一示意图。
图3为本实用新型一种改善多芯片堆叠装片的结构实施例1的示意图。
图4~图10为本实用新型一种改善多芯片堆叠装片的结构实施例1工艺方法的流程示意图。
图11为本实用新型一种改善多芯片堆叠装片的结构实施例2的示意图。
图12~图17为本实用新型一种改善多芯片堆叠装片的结构实施例2工艺方法的流程示意图。
图18~图24为本实用新型一种改善多芯片堆叠装片的结构实施例2另一工艺方法的流程示意图。
其中:
框架基材1
下层芯片2
上层芯片3
装片胶4
贴膜5
“工”字型支架6
焊线7
塑封料8。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
实施例1:
如图3所示,本实施例中的一种改善多芯片堆叠装片的结构,它包括框架基材1,所述框架基材1正面通过装片胶4设置有下层芯片2,所述框架基材1正面通过贴膜5设置有“工”字型支架6,所述“工”字型支架6正面通过装片胶4设置有上层芯片3,所述框架基材1、下层芯片2及上层芯片3之间均通过焊线7相连接,所述下层芯片2、上层芯片3、“工”字型支架6和焊线7外围包封有塑封料8;
所述“工”字型支架6为上大下小的“工”字型支架,根据实际芯片的规格、封装厚度、打线能力来定制顶面与底面的面积与高度;
所述下层芯片2的部分区域及部分焊线7容置于“工”字型支架6下面的空间;
所述下层芯片2有多个;
贴膜5为“工”字型支架6底部使用,为保证安装稳定,需选用合适的film膜;
其工艺方法包括如下步骤:
步骤一、参见图4,取一框架基材;
步骤二、参见图5,在框架基材上贴装下层芯片;
按不同要求可使用刷胶或蘸胶工艺装片;
步骤三、参见图6,下层芯片与框架基材之间进行打线作业;
步骤四、参见图7,在框架基材上贴装“工”字型支架;
为保证“工”字型支架的平整度,采用film膜贴装的方式较平整且稳定,但是不限定采用其他方式是实现“工”字型支架的贴装,Film膜的选用需根据材质及工艺选用合适的膜;
步骤五、参见图8,在“工”字型支架上贴装上层芯片;
步骤六、参见图9,上层芯片与框架基材之间进行打线作业;
步骤七、参见图10,包封。
实施例2:
参见图11,实施例2与实施例1的区别在于:所述下层芯片2有多个。
其工艺方法包括如下步骤:
步骤一、参见图12,取一框架基材;
步骤二、参见图13,在框架基材上贴装多个下层芯片;
步骤三、参见图14,在框架基材上贴装“工”字型支架;
步骤四、参见图15,在“工”字型支架上贴装上层芯片;
步骤五、参见图16,框架基材、下层芯片及上层芯片之间均通过焊线相连接;
步骤六、参见图17,包封。
或其工艺方法包括如下步骤:
步骤一、参见图18,取一框架基材;
步骤二、参见图19,在框架基材上贴装多个下层芯片;
步骤三、参见图20,下层芯片与框架基材之间打线作业;
步骤四、参见图21,在框架基材上贴装“工”字型支架;
步骤五、参见图22,在“工”字型支架上贴装上层芯片;
步骤六、参见图23,上层芯片与框架基材之间进行打线作业;
步骤七、参见图24,包封。
除上述实施例外,本实用新型还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本实用新型权利要求的保护范围之内。
Claims (4)
1.一种改善多芯片堆叠装片的结构,其特征在于:它包括框架基材(1),所述框架基材(1)正面通过装片胶(4)设置有下层芯片(2),所述框架基材(1)正面通过贴膜(5)设置有“工”字型支架(6),所述“工”字型支架(6)正面通过装片胶(4)设置有上层芯片(3),所述框架基材(1)、下层芯片(2)及上层芯片(3)之间均通过焊线(7)相连接,所述下层芯片(2)、上层芯片(3)、“工”字型支架(6)和焊线(7)外围包封有塑封料(8)。
2.根据权利要求1所述的一种改善多芯片堆叠装片的结构,其特征在于:所述下层芯片(2)有多个。
3.根据权利要求1所述的一种改善多芯片堆叠装片的结构,其特征在于:所述“工”字型支架(6)为上大下小的“工”字型支架。
4.根据权利要求1所述的一种改善多芯片堆叠装片的结构,其特征在于:所述下层芯片(2)的部分区域及部分焊线(7)容置于“工”字型支架(6)下面的空间。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201721251162.8U CN207398115U (zh) | 2017-09-27 | 2017-09-27 | 一种改善多芯片堆叠装片的结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201721251162.8U CN207398115U (zh) | 2017-09-27 | 2017-09-27 | 一种改善多芯片堆叠装片的结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN207398115U true CN207398115U (zh) | 2018-05-22 |
Family
ID=62404234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201721251162.8U Active CN207398115U (zh) | 2017-09-27 | 2017-09-27 | 一种改善多芯片堆叠装片的结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN207398115U (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107579048A (zh) * | 2017-09-27 | 2018-01-12 | 江苏长电科技股份有限公司 | 一种改善多芯片堆叠装片的结构及其工艺方法 |
-
2017
- 2017-09-27 CN CN201721251162.8U patent/CN207398115U/zh active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107579048A (zh) * | 2017-09-27 | 2018-01-12 | 江苏长电科技股份有限公司 | 一种改善多芯片堆叠装片的结构及其工艺方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI305410B (en) | Multi-chip package structure | |
US7015587B1 (en) | Stacked die package for semiconductor devices | |
US8125063B2 (en) | COL package having small chip hidden between leads | |
US7911067B2 (en) | Semiconductor package system with die support pad | |
CN105161431A (zh) | 晶圆级芯片封装方法 | |
CN106898591A (zh) | 一种散热的多芯片框架封装结构及其制备方法 | |
CN105185717A (zh) | 晶圆级芯片封装方法 | |
JP2005539403A5 (zh) | ||
CN101958257B (zh) | 双面图形芯片直接置放先镀后刻模组封装方法 | |
CN205723498U (zh) | 多芯片的系统级晶圆级封装结构 | |
CN207398115U (zh) | 一种改善多芯片堆叠装片的结构 | |
US7667306B1 (en) | Leadframe-based semiconductor package | |
CN105161465A (zh) | 晶圆级芯片封装方法 | |
CN210575949U (zh) | 一种大芯片的垂直堆叠结构 | |
US8299587B2 (en) | Lead frame package structure for side-by-side disposed chips | |
CN107579048A (zh) | 一种改善多芯片堆叠装片的结构及其工艺方法 | |
US20080283981A1 (en) | Chip-On-Lead and Lead-On-Chip Stacked Structure | |
CN105895587A (zh) | Daf与低粗糙度硅片结合性来克服基板与芯片分层方法 | |
CN208608197U (zh) | 层叠封装结构 | |
CN107146777A (zh) | 一种免切割封装结构及其制造工艺 | |
CN206864462U (zh) | 一种分拣式存储芯片封装结构 | |
CN202196776U (zh) | 一种扁平无载体无引线引脚外露封装件 | |
CN204361080U (zh) | 电路系统及其芯片封装 | |
CN207183224U (zh) | 加热块及具有其的加热装置、压制加热组件 | |
CN101226915B (zh) | 封装基板及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |