CN109712948A - 一种集成被动元件的芯片封装结构 - Google Patents

一种集成被动元件的芯片封装结构 Download PDF

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CN109712948A
CN109712948A CN201910068219.8A CN201910068219A CN109712948A CN 109712948 A CN109712948 A CN 109712948A CN 201910068219 A CN201910068219 A CN 201910068219A CN 109712948 A CN109712948 A CN 109712948A
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chip
passive device
lead frame
dao
packaging structure
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杨建伟
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Guangdong Style Science And Technology Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种集成被动元件的芯片封装结构，包括引线框架、芯片、被动元件以及用于封装引线框架、芯片、被动元件的塑封料，所述引线框架包括基岛和引脚，所述被动元件设置在所述基岛上，所述芯片设置在被动元件上，所述芯片通过金线与引线框架的引脚连接。本发明采用堆叠封装设计，实现了引线框架基岛的系统模块封装，把被动元件和芯片依次连接到引线框架的基岛上，既能实现引线框基岛小尺寸封装，又能解决柔性印刷电路板基岛的不充分填充问题造成的可靠性问题，同时，提高产品生产效率，提高引线框架架和塑封料材料的利用率，另外，使用引线框架的引脚和基岛来连接芯片和被动元件，减少可以封装模块的阻抗，避免信号传输干扰问题。

Description

一种集成被动元件的芯片封装结构
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种集成被动元件的芯片封装结构。
背景技术
现有技术中，引线框基岛QFN封装产品, 大部分仅仅为芯片封装，没有将被动元件和芯片整合在一起进行封装，少数将被动元件和芯片整合在一起产品，采用平面封装方式，导致产品尺寸会大大增加，很难满足小尺寸封装的要求，因此，被动元件和芯片整合在一起的封装基本都是采用柔性印刷电路板来实现，但此类封装又存在被动元件底部空间很小（<50um）,塑封工艺会出现被动元件底部不充分填充，造成产品可靠性问题。
发明内容
本发明的目的在于提供一种尺寸小、可靠性高、生产效率高的集成被动元件的芯片封装结构。
本发明是这样实现的：一种集成被动元件的芯片封装结构，包括引线框架、芯片、被动元件以及用于封装引线框架、芯片、被动元件的塑封料，所述引线框架包括基岛和引脚，所述被动元件设置在所述基岛上，所述芯片设置在被动元件上，所述芯片通过金线与引线框架的引脚连接。
其中，所述基岛为掏空设计，基岛上设有通孔用于容纳塑封料。
其中，所述芯片底部还设有装片膜。
其中，所述芯片尺寸大于被动元件的尺寸。
其中，所述被动元件通过导电胶固定在基岛上。
本发明的有益效果为：本发明所述集成被动元件的芯片封装结构采用堆叠封装设计，实现了引线框架基岛的系统模块封装，把被动元件和芯片依次连接到引线框架的基岛上，既能实现引线框基岛小尺寸封装，又能解决柔性印刷电路板基岛的不充分填充问题造成的可靠性问题，同时，提高产品生产效率，提高引线框架架和塑封料材料的利用率，另外，使用引线框架的引脚和基岛来连接芯片和被动元件，减少可以封装模块的阻抗，避免信号传输干扰问题，产品可应用于电子高端智能领域，如时钟模块，信号模块等。
附图说明
图1是本发明所述集成被动元件的芯片封装结构实施例的截面图；
图2是所述芯片封装结构在未注塑塑封料时的立体结构示意图；
图3是把被动元件连接到引线框架后的俯视图；
图4是把芯片连接到被动元件后的俯视图。
其中，1、引线框架；11、基岛；111、通孔；12、引脚；2、芯片；3、被动元件；4、塑封料；5、金线；6、装片膜；7、导电胶。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
作为本发明所述集成被动元件的芯片封装结构的实施例，如图1至图4所示，包括引线框架1、芯片2、被动元件3以及用于封装引线框架1、芯片2、被动元件3的塑封料4，所述引线框架1包括基岛11和引脚12，所述被动元件3设置在所述基岛11上，所述芯片2设置在被动元件3上，所述芯片2通过金线5与引线框架1的引脚12连接。
本发明设计结合引线框架基岛和柔性印刷电路板的特性，在引线框架的基岛11上设计被动元件堆叠芯片的方式，作为一个实施例，所述塑封料尺寸为4*4mm，相比非堆叠的传统设计尺寸最小为8*4mm，尺寸减为传统的50%，大大减小了产品尺寸。
在本实施例中，本发明采用引线框基岛被动元件堆叠芯片的设计封装方式可支持大于被动元件3的芯片2堆叠在被动元件3上，芯片2外围悬空式的结构依然可以正常焊线，芯片2厚度可薄至100um,可以不需要其它特殊辅助要求。当芯片2的尺寸大于支撑的被动元件3的尺寸时，也可以在芯片2底部还置装片膜6，装片膜6可以增加对芯片2的支撑强度和支撑面积。
在本实施例中，所述基岛11为掏空设计，基岛11上设有通孔111用于容纳塑封料4。使被动元件3的底部有足够的空间，解决了以柔性印刷电路板基岛的不充分填充造成的产品可靠性问题，提高了产品的可靠性。
在本实施例中，所述被动元件3通过导电胶7固定在基岛11上，实现电连接和固定。
本发明采用引线框架基岛被动元件堆叠芯片的设计封装方式，使塑封UPH（unitsper hour）提高到32.4K，相比传统设计非堆叠设计UPH为16.8K，塑封的UPH提高93%，效果大大提高；材料方面使用量降低，本发明提高引线框架的利用率（以引线框架尺寸为240x74mm为例，引线框架利用率为原来的240%），塑封料使用量降低42%（传统设计一模产品数量为336颗，本发明一模为810颗）
本发明所述集成被动元件的芯片封装结构采用堆叠封装设计，实现了引线框架基岛的系统模块封装，把被动元件3和芯片2依次连接到引线框架1的基岛11上，既能实现引线框架的基岛11小尺寸封装，又能解决柔性印刷电路板基岛的不充分填充问题造成的可靠性问题，同时，提高产品生产效率，提高引线框架和塑封料材料的利用率，另外，使用引线框架的引脚12和基岛11来连接芯片2和被动元件3，减少可以封装模块的阻抗，避免信号传输干扰问题，产品可应用于电子高端智能领域，如时钟模块，信号模块等。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (5)

1.一种集成被动元件的芯片封装结构，其特征在于，包括引线框架、芯片、被动元件以及用于封装引线框架、芯片、被动元件的塑封料，所述引线框架包括基岛和引脚，所述被动元件设置在所述基岛上，所述芯片设置在被动元件上，所述芯片通过金线与引线框架的引脚连接。
2.根据权利要求1所述的芯片封装结构，其特征在于，所述基岛为掏空设计，基岛上设有通孔用于容纳塑封料。
3.根据权利要求1所述的芯片封装结构，其特征在于，所述芯片底部还设有装片膜。
4.根据权利要求3所述的芯片封装结构，其特征在于，所述芯片尺寸大于被动元件的尺寸。
5.根据权利要求1所述的芯片封装结构，其特征在于，所述被动元件通过导电胶固定在基岛上。
CN201910068219.8A 2019-01-24 2019-01-24 一种集成被动元件的芯片封装结构 Pending CN109712948A (zh)

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CN110600447A (zh) * 2019-08-01 2019-12-20 长电科技（宿迁）有限公司 一种新型引线框架结构及封装结构

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110600447A (zh) * 2019-08-01 2019-12-20 长电科技（宿迁）有限公司 一种新型引线框架结构及封装结构

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