JP4929382B2 - 電子部品構造体及び電子機器 - Google Patents
電子部品構造体及び電子機器 Download PDFInfo
- Publication number
- JP4929382B2 JP4929382B2 JP2010158695A JP2010158695A JP4929382B2 JP 4929382 B2 JP4929382 B2 JP 4929382B2 JP 2010158695 A JP2010158695 A JP 2010158695A JP 2010158695 A JP2010158695 A JP 2010158695A JP 4929382 B2 JP4929382 B2 JP 4929382B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- solder
- semiconductor package
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
- H05K7/10—Plug-in assemblages of components, e.g. IC sockets
- H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
- H05K7/1061—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by abutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Description
実施形態の電子機器は、半導体パッケージと、基板とを有する。前記半導体パッケージは、凹部が設けられたリードフレームと該リードフレームを覆っためっき層とを含む電極部を含む。前記基板は、前記半導体パッケージが実装されている。前記電極部は、前記凹部が前記めっき層で覆われた規制部を有する。
まずは、第1実施形態について図1ないし図3を参照して説明する。
次に、第2実施形態について図5を参照して説明する。
次に、第3実施形態について図6及び図7を参照して説明する。
次に、第4実施形態について図8ないし図10を参照して説明する。
次に、第5実施形態について図11を参照して説明する。
次に、第6実施形態について図12を参照して説明する。
次に、第7実施形態について図13を参照して説明する。
次に、第8実施形態について図14を参照して説明する。
4…半導体パッケージ(電子部品構造体)
5,21,33…基板
10…半導体チップ(電子部品)
11…第一電極部(電極部)
11a…リードフレーム
11b…めっき層
11d,11dE…半田付け領域
11e…半田付け領域の周縁部
11f,11fA,11fB,11fC,11fD,11fE…規制部
11g…規制部の底面
11h…規制部の側面
11i…接続面
13…接続層
20…パーソナルコンピュータ(電子機器)
30…磁気ディスク装置(電子機器)
Claims (8)
- 電子部品と、
前記電子部品に電気的に接続され凹部が設けられたリードフレームと、前記電子部品側とは反対側で該リードフレームを覆うとともに基板に半田付けされるめっき層とを含む電極部と、
を備え、
前記電極部は、前記凹部が前記めっき層で覆われた規制部を有する電子部品構造体。 - 前記電子部品と前記リードフレームとの間に接続層を有した請求項1に記載の電子部品構造体。
- 前記規制部の底面から、前記接続層が露出された請求項2に記載の電子部品構造体。
- 前記規制部は、格子状に設けられた請求項2に記載の電子部品構造体。
- 凹部が設けられたリードフレームと該リードフレームを覆っためっき層とを含む電極部を含む半導体パッケージと、
前記半導体パッケージが実装された基板と、
を備え、
前記電極部は、前記凹部が前記めっき層で覆われた規制部を有する電子機器。 - 前記リードフレームにおける前記めっき層側とは反対側に接続層を有した請求項5に記載の電子機器。
- 前記規制部の底面から、前記接続層が露出された請求項6に記載の電子機器。
- 前記規制部は、格子状に設けられた請求項7に記載の電子機器。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010158695A JP4929382B2 (ja) | 2010-07-13 | 2010-07-13 | 電子部品構造体及び電子機器 |
US13/028,980 US20120014078A1 (en) | 2010-07-13 | 2011-02-16 | Electronic Component Structure and Electronic Device |
US13/756,209 US20130141884A1 (en) | 2010-07-13 | 2013-01-31 | Electronic Component Structure and Electronic Device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010158695A JP4929382B2 (ja) | 2010-07-13 | 2010-07-13 | 電子部品構造体及び電子機器 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012023129A JP2012023129A (ja) | 2012-02-02 |
JP4929382B2 true JP4929382B2 (ja) | 2012-05-09 |
Family
ID=45466838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010158695A Active JP4929382B2 (ja) | 2010-07-13 | 2010-07-13 | 電子部品構造体及び電子機器 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20120014078A1 (ja) |
JP (1) | JP4929382B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102032271B1 (ko) * | 2013-08-09 | 2019-10-16 | 한국전자통신연구원 | 전자기기의 접합구조 |
JP6327114B2 (ja) * | 2014-10-30 | 2018-05-23 | 三菱電機株式会社 | 電子部品搭載基板、電動機、空気調和機、及び電子部品搭載基板の製造方法 |
JP2022133486A (ja) * | 2019-07-30 | 2022-09-14 | 株式会社デンソー | 半導体パッケージおよび半導体装置 |
JP7215982B2 (ja) * | 2019-09-17 | 2023-01-31 | 株式会社東芝 | プリント基板及びディスク装置 |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3059560B2 (ja) * | 1991-12-25 | 2000-07-04 | 株式会社日立製作所 | 半導体装置の製造方法およびそれに使用される成形材料 |
US5497032A (en) * | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
JPH0997969A (ja) * | 1995-09-28 | 1997-04-08 | Denso Corp | 表面実装用印刷回路 |
JPH09102567A (ja) * | 1995-10-09 | 1997-04-15 | Mitsubishi Electric Corp | 半導体装置 |
US6329711B1 (en) * | 1995-11-08 | 2001-12-11 | Fujitsu Limited | Semiconductor device and mounting structure |
US6159770A (en) * | 1995-11-08 | 2000-12-12 | Fujitsu Limited | Method and apparatus for fabricating semiconductor device |
US5916696A (en) * | 1996-06-06 | 1999-06-29 | Lucent Technologies Inc. | Conformable nickel coating and process for coating an article with a conformable nickel coating |
JP3314757B2 (ja) * | 1999-05-07 | 2002-08-12 | 日本電気株式会社 | 半導体回路装置の製造方法 |
JP3062192B1 (ja) * | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
US6504238B2 (en) * | 2000-01-31 | 2003-01-07 | Texas Instruments Incorporated | Leadframe with elevated small mount pads |
JP2001313363A (ja) * | 2000-05-01 | 2001-11-09 | Rohm Co Ltd | 樹脂封止型半導体装置 |
JP2002076215A (ja) * | 2000-08-29 | 2002-03-15 | Sony Corp | 半導体装置パッケージ及びその作製方法 |
JP3470111B2 (ja) * | 2001-06-28 | 2003-11-25 | 松下電器産業株式会社 | 樹脂封止型半導体装置の製造方法 |
JP2003037344A (ja) * | 2001-07-25 | 2003-02-07 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
US6630373B2 (en) * | 2002-02-26 | 2003-10-07 | St Assembly Test Service Ltd. | Ground plane for exposed package |
US20030178707A1 (en) * | 2002-03-21 | 2003-09-25 | Abbott Donald C. | Preplated stamped small outline no-lead leadframes having etched profiles |
US7122884B2 (en) * | 2002-04-16 | 2006-10-17 | Fairchild Semiconductor Corporation | Robust leaded molded packages and methods for forming the same |
TWI257693B (en) * | 2003-08-25 | 2006-07-01 | Advanced Semiconductor Eng | Leadless package |
US7315077B2 (en) * | 2003-11-13 | 2008-01-01 | Fairchild Korea Semiconductor, Ltd. | Molded leadless package having a partially exposed lead frame pad |
US7125747B2 (en) * | 2004-06-23 | 2006-10-24 | Advanced Semiconductor Engineering, Inc. | Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe |
US7169651B2 (en) * | 2004-08-11 | 2007-01-30 | Advanced Semiconductor Engineering, Inc. | Process and lead frame for making leadless semiconductor packages |
JP2006060141A (ja) * | 2004-08-23 | 2006-03-02 | Sharp Corp | 印刷基板及びこれを用いた表面実装型半導体パッケージの実装方法 |
JP2006216843A (ja) * | 2005-02-04 | 2006-08-17 | Matsushita Electric Ind Co Ltd | メモリカードおよびプリント配線板 |
JP4634230B2 (ja) * | 2005-06-17 | 2011-02-16 | 株式会社オートネットワーク技術研究所 | 回路基板、電子部品及び電気接続箱 |
US7504733B2 (en) * | 2005-08-17 | 2009-03-17 | Ciclon Semiconductor Device Corp. | Semiconductor die package |
US7550828B2 (en) * | 2007-01-03 | 2009-06-23 | Stats Chippac, Inc. | Leadframe package for MEMS microphone assembly |
US7871865B2 (en) * | 2007-01-24 | 2011-01-18 | Analog Devices, Inc. | Stress free package and laminate-based isolator package |
US7932587B2 (en) * | 2007-09-07 | 2011-04-26 | Infineon Technologies Ag | Singulated semiconductor package |
US7868431B2 (en) * | 2007-11-23 | 2011-01-11 | Alpha And Omega Semiconductor Incorporated | Compact power semiconductor package and method with stacked inductor and integrated circuit die |
US20090166826A1 (en) * | 2007-12-27 | 2009-07-02 | Janducayan Omar A | Lead frame die attach paddles with sloped walls and backside grooves suitable for leadless packages |
US8084299B2 (en) * | 2008-02-01 | 2011-12-27 | Infineon Technologies Ag | Semiconductor device package and method of making a semiconductor device package |
US20090315163A1 (en) * | 2008-06-20 | 2009-12-24 | Terry Johnson | Semiconductor Die Packages with Stacked Flexible Modules Having Passive Components, Systems Using the Same, and Methods of Making the Same |
US7923847B2 (en) * | 2008-08-27 | 2011-04-12 | Fairchild Semiconductor Corporation | Semiconductor system-in-a-package containing micro-layered lead frame |
US8008784B2 (en) * | 2008-10-02 | 2011-08-30 | Advanced Semiconductor Engineering, Inc. | Package including a lead frame, a chip and a sealant |
US20100133693A1 (en) * | 2008-12-03 | 2010-06-03 | Texas Instruments Incorporated | Semiconductor Package Leads Having Grooved Contact Areas |
US7858443B2 (en) * | 2009-03-09 | 2010-12-28 | Utac Hong Kong Limited | Leadless integrated circuit package having standoff contacts and die attach pad |
US8044495B2 (en) * | 2009-06-22 | 2011-10-25 | Texas Instruments Incorporated | Metallic leadframes having laser-treated surfaces for improved adhesion to polymeric compounds |
CN102859687B (zh) * | 2010-05-12 | 2015-09-23 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
-
2010
- 2010-07-13 JP JP2010158695A patent/JP4929382B2/ja active Active
-
2011
- 2011-02-16 US US13/028,980 patent/US20120014078A1/en not_active Abandoned
-
2013
- 2013-01-31 US US13/756,209 patent/US20130141884A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20120014078A1 (en) | 2012-01-19 |
JP2012023129A (ja) | 2012-02-02 |
US20130141884A1 (en) | 2013-06-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9119320B2 (en) | System in package assembly | |
JP2006196709A (ja) | 半導体装置およびその製造方法 | |
JP2007158001A (ja) | テープキャリアパッケージ及びそれを搭載した表示装置 | |
US11303788B2 (en) | Electronic device and camera module thereof | |
JP4929382B2 (ja) | 電子部品構造体及び電子機器 | |
US9451699B2 (en) | Circuit board, electronic device, and method of manufacturing circuit board | |
JP2006339316A (ja) | 半導体装置、半導体装置実装基板、および半導体装置の実装方法 | |
JP2012191002A (ja) | 半導体装置 | |
US20130016289A1 (en) | Television and electronic apparatus | |
JP2009016398A (ja) | プリント配線板構造、電子部品の実装方法および電子機器 | |
JP2014003101A (ja) | 回路板、電子機器 | |
JP5050111B1 (ja) | テレビジョン装置および電子機器 | |
JP2006270930A (ja) | 携帯機器 | |
WO2014122797A1 (ja) | 電子機器および半導体電子部品 | |
US20120274866A1 (en) | Television apparatus and electronic apparatus | |
JP2012216642A (ja) | 電子機器および基板アセンブリ | |
US9591761B2 (en) | Screen control module having greater anti-warp strength of a mobile electronic device and controller thereof | |
JP4996729B2 (ja) | 電子機器および基板アセンブリ | |
TWI819809B (zh) | 感光組件、攝像模組及電子裝置 | |
JP4825919B1 (ja) | 電子機器 | |
JP2015038899A (ja) | 回路板及び電子機器 | |
WO2015001653A1 (ja) | 電子機器 | |
TWI244668B (en) | Tape carrier package | |
JP5342034B2 (ja) | 電子部品および電子機器 | |
JP2008166619A (ja) | 回路モジュール、デジタル放送受信装置および放熱体 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111202 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120117 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120213 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150217 Year of fee payment: 3 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4929382 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150217 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 Free format text: JAPANESE INTERMEDIATE CODE: R313121 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |