CN1153267C - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
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- CN1153267C CN1153267C CNB991084586A CN99108458A CN1153267C CN 1153267 C CN1153267 C CN 1153267C CN B991084586 A CNB991084586 A CN B991084586A CN 99108458 A CN99108458 A CN 99108458A CN 1153267 C CN1153267 C CN 1153267C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 140
- 238000000034 method Methods 0.000 title description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052737 gold Inorganic materials 0.000 claims abstract description 51
- 239000010931 gold Substances 0.000 claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 12
- 238000007599 discharging Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000008018 melting Effects 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 59
- 238000005516 engineering process Methods 0.000 description 14
- 238000012545 processing Methods 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 238000011990 functional testing Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000003044 adaptive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 1
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Abstract
设置于半导体芯片(4)的表面上的电极端(5)在平面视图上具有方形。而且,设置于电极端(5)上的凸块(8)的突出顶部(8a)指向电极端(5)的角部(5a)。于是,使通过毛细管(1)供给的金丝(2)的下端部熔化而形成的金球(2a)与电极端(5)接合,然后,沿方形电极(5)的对角线方向移动毛细管(1)。因而,使金丝(2)的主体与金球(2a)分离开,以形成凸块(8)。
Description
技术领域
本发明涉及一种将多个凸块设置在半导体器件芯片表面上的倒扣式半导体器件(集成电路器件),特别涉及使每个凸块与器件的一个起电极外露的焊盘作用的电极端对应地设置,采用表面朝下焊接技术等,通过其凸块与电路基板接合的一种倒扣式半导体器件,以及制造该种器件的方法。本发明还涉及采用各种电子设备的制造工艺,使半导体器件的每个电极端与电路基板的一个相应电极电连接的一种半导体器件与电路基板接合的方法。
背景技术
在倒扣式半导体器件(集成电路器件)的制造工艺中,一般按图19所示的技术形成凸块(凸起电极)。即,把高压施加于切割电极3与经焊接工具的毛细管1所供给的金丝2之间,以使金丝2的下端部熔化,其下端部形成圆形金球2a。然后,借助于热压焊技术或超声焊技术,将金球2a与安排在半导体芯片(IC芯片)4表面上的方形电极端5接合,而形成一个凸块6。
但是,根据此种常规凸块形成技术,在金球2a与电极端5接合之后,金丝2的下端部立刻与金球2a分开,弯向凸块6,如双点划线2b所示。金丝2的弯曲方向由毛细管1的移动方向确定。于是,相对于切割电极3的弯曲方向是不固定,然后,这可根据下步形成的凸块6的位置或方向而变化。所以,使金丝2下端和切割电极3之间的电火花间隙不均匀,而使火花电流不均匀。因而,这就有一个难以在预定位置形成无不规则形状的多个凸块6的问题。而且,当凸块6伸出于电极端区时,又出现了一个容易引起电极间短路或误连的问题。
另外,在倒扣式半导体器件S的制造工艺中,为了调节设置于半导体芯片4表面上的每个凸块6的高度要求进行整平处理,那么就要进行高精度地平整处理。
如图20所示,按常规的整平处理技术,首先把在其前表面具有凸块6的半导体芯片4放置在平坦的整平台11上,使半导体芯片4的前表面朝上。在此条件下,使压板12向下移动,使压板12的平滑的下表面压向凸块6。然后,大体上改变了每个凸块6头部的形状,使每个焊块6的高度一致。
如上所述,通过整平处理虽然使凸块6变形了,但各凸块6的变形程度是不完全一致,可以说是千差万别,所以,在此步骤,应当检验一下,整平处理是否合格,或是否引起了故障,如短路等。但是,基于目测的常规检验技术,存在一个不能期望精确而有效检验的问题。
而且,当半异体芯片大时,所需的凸块的数量也变多,因而实施整平处理所需的压力也要变大。这又出现了一个需要配备一个昂贵的大个的压力设备的问题。
另一方面,在各种电子设备的制造工艺中,使半导体器件S的各个电极一次全部地与电路基板的各个相对应的电极电连接,以使半导体器件S与电路基板接合。下面,将说明一种半导体器件S与电路基板接合的常规方法,参照图21~24。
即,如图21所示,在半导体器件S中,在半导体芯片4的每个电极端5上,用球焊技术,使用金丝、焊丝等形成凸块6(凸起电极)。因为在凸块形成步骤难以一一调节凸块的高度,所以每个凸块6不可避免地会有不同的高度。
于是,如图22所示,为了在接合步骤前矫正每个凸块6的高度不规则性,首先,用一个施压部件13将半导体器件S压下,然后,把半导体器件S的各凸块6压到平的平板14的表面上。接着,使每个凸块6的顶部变形,以使每个凸块6的高度一致。
然后,如图23所示,将半导体器件S的凸块6的已平整的顶部压到在其上涂有预定厚度导电胶15的平的转移板16的表面,以使导电胶15转移到凸块6的顶部。
进而,如图24所示,把半导体器件S放置在电路基板17上,使涂有导电胶15的各凸块6的顶部对准电路基板17上所设置的一个相对的电极18,然后使半导体器件S与电路基板17接合。
根据上述的常规接合技术,每个凸块6的高度是一致的,即矫正了高度的不规则性。于是,转移到每个凸块6顶部的导电胶15的厚度有10μm之厚。所以,将与半导体器件S接合的电路基板17的每个电极18的厚度(高度)不规则性必经被转移到每个凸块6顶部的厚约10μm的导电胶15吸收。因此,当电路基板17具有大于10μm的弯翘时,或电路基板17的电极18当中的厚度不规则度大于10μm时,这就出现了这样一种半导体器件S不能合适地与电路基板17接合的问题。
再如图24所示,因为半导体器件S的每个凸块6的顶部与电路基板17的相对应的电极18之间的距离是不一致的,也有这样一种半导体器件S与电路基板17之间的焊结强度可能不充分的问题,而且还有这样一种每个凸块6的连接电阻值可能不一致的问题。例如,可以形成连接电阻为30(mΩ/凸块)的凸块6,这是标准阻值,或可能形成接合电阻为100(mΩ/凸块)的凸块6。
发明内容
本发明的开发旨在解决上述传统的问题,并且其目的在于提供一种制造半导体器件的方法,即使作为凸块的一种材料的金丝下端部是弯曲的,按本发明的方法,形成半导体器件而无凸块形状的不规则性。
而且,本发明的另一目的在于提供一种制造半导体器件的方法,按此法,通过整平处理而变形的凸块的机械或/和电学特性是可以精确而有效掌握的。再有,本发明的另一目的在于提供一种制造半导体器件的方法,按此法,可使凸块高精度地变形,并能容易对有许多凸块的半导体器件实行整平处理。
再有,本发明的另一目的在于提供一种将半导体器件与电路基板接合方法,按此法,可一次全部地高可靠地将半导体器件的多个凸块与电路基板的多个电极接合。
按照本发明的第一方面,提供一种制造半导体器件的方法,包括用金丝作凸块的材料在设置于半导体芯片表面上的第一和第二电极端上各形成一凸块的步骤,所说的第一和第二电极端沿所说的半导体芯片的一侧布置,所说的金丝是通过毛细管供给的,而所说的凸块形成步骤包括以下各步骤:将金球接合到位于所说的毛细管正下方的所说的第一电极端上,以形成第一凸块,所说的金球是在预定放电条件下将所说的金丝端部熔化而形成的;移动固定所说的半导体芯片的固定台,以便将所说的第二电极端置于所说的毛细管的正下方;以及将另一金球接口到所说的第二电极端,以形成第二凸块,所说的金球是在与所说的第一凸块的放电条件相同的放电条件下,将所说的金丝端部熔化形成的,其中所说的固定台按X方向和Y方向移动,并且还按θ方向旋转,所说的X方向是沿所说的半导体芯片的纵向边的方向,所说的Y方向是沿所说的半导体芯片的横向边的方向,所说的θ方向是以所说的半导体芯片的垂直中线为θ角的方向。
按照本发明的第二方面,提供一种制造半导体器件的方法,包括用金丝作凸块材料在设置于半导体芯片表面上的第一和第二电极端上各形成一凸块的步骤;所说的第一和第二电极在所说的半导体上彼此并排地布置,所说的金丝是通过毛细管供给的,而所说的凸块形成步骤包括以下各步骤:将金球接合到位于所说的毛细管正下方的所说的第一电极端上,以形成第一凸块,所说的金球是用切割电极在预定放电条件下将所说的金丝端部熔化而形成的;环绕所说的毛细管移动所说的切割电极,以便能在与第一凸块的放电条件相同的放电条件下,使所说的金丝端部熔化,然后将另一金球接合到所说的第二电极端,以形成第二凸块,所说的金球是在放电条件下使所说的金丝端部熔化而形成的。
按照本发明的第三方面,提供一种制造半导体器件的方法,包括:用一半导体固定台将在一表面上具有多个凸块的半导体芯片与所说的表面相反的另一表面上固定;部分或全部地把所说的凸块压到整平台上,以使所说的每个凸块的高度一致,同时实施对所说的半导体芯片的功能测试,其中,所说的半导体芯片的功能测试是借助于对应于每个所说的凸块而设置在所说的整平台的功能测试用的电极而实现的;所说的功能测试用的电极与所说的凸块接触,并且每个所说的电极被分成两个相邻电极块,每个电极块与一个凸块接触并可以执行所说的半导体芯片的所说的功能测试。
按照本发明的第四方面,基于本发明第三方面的制造方法,其中所说的半导体固定台和所说的整平台,二者中至少之一在将所说的凸块压到所说的整平台上时是被加热的。
按照本发明的第五方面,提供一种使半导体器件与电路基板接合的方法,其方式是,使设置于所说的半导体器件上的每个电极端上所设置的凸块与形成电路的所说的电路基板的一个相对应的电极相连接,所说的方法包括以下各步骤:使所说的半导体器件相对于所说的电路基板定位,其方式是,将每个所说的凸块各自定位于所说的电路基板的一个相对应的电极上方;将所说的半导体器件压到所说的电路基板上,以使每个所说的凸块顶部变形,因而使每个所说的凸块高度与所说电路基板的一个相对应的电极的实际高度相适配;将所说的半导体器件的凸块推压到涂敷于平板表面上的导电胶膏状焊锡的表面,以便将所说的导电胶或所说的膏状焊锡转移到所说的凸块上;以及使所说的半导体器件相对于所说的电路基板定位,其方式是,将所说的导电胶或所说的膏状焊锡转移到其上的每个所说的凸块各自配置在所说的电路基板的一个相对应的电板上,以使所说的半导体器件与所说的电路基板接合。
按照本发明的第六方面,基于本发明第五方面的方法,其中对所说的半导体器件中的电路的功能测试是在将所说的半导体器件压到所说的电路整板上时实现的。
按照本发明的第七方面,基于本发明第五方面的方法,其中所说的半导体器件是在将所说的半导体器件压到所说的电路基板上时被加热的。
附图说明
从参照附图结合优选实施例的如下的说明中,会使本发明的以上和其它目的、特点和优点变得明了,各图中相同的部分以相同标号代表。
图1是表示凸块周围的半导体器件部分的带有根据本发明的凸块的半导体器件(集成电路器件)的平面图;
图2是图1所示半导体器件的局部剖面图:
图3是由半导体器件和在凸块形成步骤中用来形成凸块的设备所构成的组合图的局部剖面图;
图4是由半导体器件和在凸块形成步骤中用来形成凸块的设备构成的组合的透视图;
图5是表明毛细管和切割电极间的位置关系的由二者构成的组合示意图;
图6是根据本发明的装有半导体器件的整平处理设备在整平处理之前状态下的侧视图;
图7是根据本发明的装有半导体器件的整平处理设备在整平处理过程中的状态下的侧视图;
图8是根据本发明的另一整平处理设备和半导体器件在整平处理之前状态下的侧视图;
图9是根据本发明的整平处理设备和半导体器件在整平处理过程中状态下的侧视图;
图10是根据本发明的另一装有半导体器件的整平处理设备侧视图;
图11是根据本发明的另一装有半导体器件的整平处理设备侧视图;
图12是带有凸块的半导体器件的侧视图;
图13是带有电极的电路基板的侧视图;
图14是说明半导体器件的每个凸块的高度与电路基板的一个相对应的电极高度相适配的状态下的由半导体器件与电路基板构成组合的侧视图;
图15是每个凸块的高度被校正后的半导体器件的侧视图;
图16是表明半导体器件的每个凸块高度与电路基板的一个相对应的电极高度相适配的状态下由半导体器件与电路基板构成的组合的侧视图;
图17是本发明的半导体器件的侧视图,图中的器件已被推压到涂敷于平板表面的导电胶上,以使导电胶转到每个凸块的顶部;
图18是由半导体器件和与半导体器件接合的电路基板构成的组合体的侧视图;
图19是由常规半导体器件与在凸块形成步骤中用来形成凸块的常规设备构成的组合的局部的图;
图20是由常规半导体器件及用以使半导体器件实行整平处理的常规整平处理设备构成的组合侧视图;
图21是常规的带有凸块的半导体器件的侧视图;
图22是由常规半导体器件及用以使半导体器件平坦的常规设备构成的组合侧视图;
图23是常规半导体器件的侧视图,图中的器件已被推压到涂敷于平板表面上的导电胶上,以使导电胶转移至每个凸块的顶部;
图24是由常规半导体器件及与半导体器件接合的常规电路基板构成的组合体侧视图。
具体实施方式
下面将具体地说明本发明的几个优选实施例。
<实施例1>
下面将参照附图说明本发明的实施例1。
如图1和2所示,在本发明的实施例1中,多个电极端5外露于半导体芯片4(IC芯片)的表面绝缘层7。于是,每个电极端5在平面图中有方的形状。
因而,设置于每个电极端5上的柱式凸块的突出顶部8a指向电极端5的一角部。于是,当径向线对应于通过两对角部的对角线“a”或“b”时,自电极端5的中心至四周的径向线的长度最长。所以,即使每个凸块8的位置或形状稍有些不规则时,几乎不会出现凸块8滑出到电极端5的外边。所以,不必担忧电极端5上的凸块8。接触到相邻的电极端5或相邻电极端5上的凸块8。
如图3所示,每个凸块8是用金丝作材料形成的,即,将高火花电压施加于切割电极3与通过焊接工具的毛细管1供给的金丝2之间,以便在端部形成金球,然后借助热压焊技术或超声焊技术,使金球与电极端5键合。然后立即沿电极端5的对角线“a”的方向移动毛细管1,使金丝2的主体部与金球(凸块8)分开。因此,形成于电极端5上的凸块8的突出顶部8a指向角部5a。
在图4所示的实例中,将切割电极3末端与由毛细管1供给的金丝2之间的距离设定为预定的火花间隔“c”。进而,可借助固定台9使半导体芯片沿x方向和y方向移动,也可顺着Θ方向转动。在此情况下,在沿半导体芯片4一边安排的电极端5(第一电极端)上形成凸块8之后,最好移动和转动半导体芯片4。然后,在沿半导体芯片4的另一边安排的电极端5(第二电极端)上形成凸块8。于是,考虑到金丝2的弯曲方向和/或弯曲的程度,可将火花间隙“c”固定为一恒定值。因而,可使形成金球时的放电条件和/或所形成的凸块8的方向或形状一致。
在图5所示的实例中,切割电极3可绕毛细管1转动。在此情况下,因为切割电极3是响应于由毛细管1供给的金丝2端部的弯曲方向而转动的,可使火花间隙和放电条件一致而无须移动半导体芯片4。
于是,由上述方法形成的每个凸块8不限于图1~3所示的那种柱式凸块。例如,各凸块也可以是球式凸块。
<实施例2>
下面将参照附图说明本发明的实施例2。
如图6所示,用有吸嘴(抽嘴)的半导体固定台21靠对芯片背面的吸力(抽力)使在芯片前表面安排有多个凸块6的半导体芯片4固定。每个凸块6由金(AU)等材料制成,具有圆形的头部。而且,在半导体固定台21下面设置的整平台22在待分别与各凸块6接触的台的每个部位上各有一个电极23,而每个电极23又与一个测试仪24相连。
当半导体固定台向下移动时,如图7所示,每个凸块6压到一个相对应的电极23,以便实施对凸块6的整平处理。同时,通过电极23使半导芯片4的内电路与测试仪电连接。于是,由测试仪完成对半导体器件的功能检测。例如,由测试仪来检测半导体侧引起开短路与否(对凸块的连续性测试),也检测半导体侧的运作状态(对半导体器件的电测试),然后在显示器上显示测试结果。因而,在整平处理的瞬间可了解到整平处理的过度或不足,凸块6的失效等等。
在上述实施例中,功能检测用的电极23是设置在整平台22的上表面的。但是,电极23也可以设置在半导体固定台21的下表面。在此情况下,必须将半导体芯片4置于整平台22上面,其方式是让芯片的前表面朝上。
每个用于功能检测的电极可分成两个电极块。在图8和9所示的实例中,在整平台22的一部位设有一对电极块,每个部位均与同一凸块6接触。换言之,为每个凸块6设置一对相毗邻的电接触23a和23b,每个电接触均起功能检测用的电极作用。在此情况下,也可进行一对电接触23a和23b之间的相互连贯性测试,就可更无疑地检测每个预定的凸块6实际上存在与否。
因而,当将一对电接触23a和23b之间的相互间隔例如设定为40μm时,即可检测凸块6头部的宽度的变形程度是否超过或等于40μm。
在图10所示的实例中,为半导体固定台21设置了加热丝25。相反,在图11所示的实例中,加热丝25是为整平台22而设的。当按上述设置了加热丝25时,在整平处理过程中,凸块6因受热而软化。因而,可使每个凸块6高精度地变形,那么可减小整平处理所需的压载(力)。
例如,当将凸块6的温度设定在150℃时,压载变为正常温度条件的1/2。进一步当将凸块6的温度设定在300℃时,压载变为常温条件下的1/3。所以,减少了施压设备的输出功率,也减少了在半导体芯片4中引起破裂的担心。
<实施例3>
下面将参照附图说明本发明的实施例3。
如图12,用金丝、焊锡丝等,借助球焊技术,在半导体器件SM的半导体芯片4的每个电极端上形成一个凸块6(突出电极)。因此,难以在凸块6的形成步骤中使每个凸块6的高度一致,以致不可避免地使每个凸块6具有不同的高度。
如图13所示,与半导体器件SM接合的设于电路基板17上的多个电极18中的每一个很可能具有不均匀的厚度。如上所述,即使电路基板17的每个电极18具有不均匀的厚度,或即使电路基板17有弯翘或起伏,致使电路基板17的每个电极18具有不均匀的高度,当使半导体器件SM的每个凸块6的顶部这样来变形,使半导体器件SM的每个凸块6的顶部高度与电路基板17的一个相对应的电极18的高度相适配时,也能使凸块6与电极18高可靠性的连接。
所以,在实施例3中,没有实施借助平板14使凸块6平坦的一般用于常规方法中的平坦化的步骤。但如图14所示,在半导体器件SM与电路基板17接合步骤中,通过未画出的半导体器件吸嘴来放置靠吸(抽)力而固定的半导体器件SM,其方式是,将每个凸块6放置在一个与半导体器件SM接合的电路基板17的一个相对应的电极18的位置,而电路基板17早已定位,然后使用一个汽缸或AC伺服电动机,施加大约50(克/凸块)的负载,将半导体器件SM压到电路基板17上。因此使凸块6变形,使每个凸块6的高度与电路基板17的一个相对应的电极18的高度相适配。于是,压强和施压时间最好随电极18的形状和尺寸,凸块6的材质,以及凸块6的形状和尺寸而变化。
因而,如图15所示,半导体器件SM中的每个凸块6的高度是随电路基板17的电极18的不规则的高度而适配的。
对此,当将半导体器件SM压到电路基板17上时,可给半导体器件SM加热。当将半导体器件SM加热至约300℃时,压载可减少至1/2,也可减短压载的时间。温度最好随电极18的形状和尺寸、凸块6的材质和凸块6的形状和尺寸而变。
下面将参照图16~18说明半导体器件SM与电路基板17的具体接合方法。
如图16所示,利用未示出的半导体器件吸嘴来设置靠吸力而固定的半导体器件SM,其方式是,将每个凸块6定位在一个与半导体器件SM接合的电路基板17的一个相对应的电极18相应的位置上,电路基板17早已定位,然后用AC伺服电动机或气缸施加大约50(克/凸块)的负载将半导体器件SM压到电路基板17上。因而,使凸块6变形,使每个凸块6的高度与电路基板17的一个相对应的电极18相适配。
再如图17所示,在每个凸块6的高度是与电路基板17一个相对应的电极18的高度相适配的情况下将半导体器件SM的凸块6的顶部压到在平板表面上涂敷的导电胶15或膏状焊锡的平表面上,使导电胶15或膏状焊锡转移到凸块6的顶部。
然后,如图18所示,使导电胶15或膏状焊锡已转移到凸块6顶部上的半导体器件SM定位,其方式是,将每个凸块6定位于电路基板17的一个相对应的电极18上,以便与电路基板17接合。进而,对与半导体器件SM接合的电路基板17加热所需的时间周期,以便预固化。在预固化工艺之后,将电路基板17送至下一步骤,以便用加热炉加热,于是完成接合工艺。
因为半导体器件SM的凸块6是压到与半导体器件SM接合的电路基板17的电极18上的,使得凸块6与电极18之间的接触状态是适配的,然后使半导体器件SM与电路基极17接合,可使半导体器件SM的凸块6与电路基板17的电极18紧密接触。因而,可改善半导体器件SM与电路基板17之间的接合强度,并使连接阻值稳定在20~30mΩ的范围内。
虽然已通过优选实施例说明了本发明,但本领域的技术人员将会理解,在不脱离权利要求书所提及的本发明的实质和范畴的前提下可做出各种各样的变化与改型。
Claims (1)
1.一种制造半导体器件的方法,包括用金丝作凸块材料在设置于半导体芯片表面上的第一和第二电极端上各形成一凸块的步骤;所说的第一和第二电极在所说的半导体上彼此并排地布置,所说的金丝是通过毛细管供给的,而所说的凸块形成步骤包括以下各步骤:
将金球接合到位于所说的毛细管正下方的所说的第一电极端上,以形成第一凸块,所说的金球是用切割电极在预定放电条件下将所说的金丝端部熔化而形成的;
环绕所说的毛细管移动所说的切割电极,以便能在与第一凸块的放电条件相同的放电条件下,使所说的金丝端部熔化,然后将另一金球接合到所说的第二电极端,以形成第二凸块,所说的金球是在放电条件下使所说的金丝端部熔化而形成的。
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
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JP322032/1994 | 1994-12-26 | ||
JP6322032A JPH08181144A (ja) | 1994-12-26 | 1994-12-26 | 半導体装置の実装方法 |
JP7523/1995 | 1995-01-20 | ||
JP752395A JP3365879B2 (ja) | 1995-01-20 | 1995-01-20 | 半導体装置の製造方法 |
JP00940195A JP3363639B2 (ja) | 1995-01-25 | 1995-01-25 | 集積回路装置およびその製造方法 |
JP9401/1995 | 1995-01-25 |
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CN95113148A Division CN1051641C (zh) | 1994-12-26 | 1995-12-25 | 制造半导体器件的方法 |
Publications (2)
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CN1248062A CN1248062A (zh) | 2000-03-22 |
CN1153267C true CN1153267C (zh) | 2004-06-09 |
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CN95113148A Expired - Fee Related CN1051641C (zh) | 1994-12-26 | 1995-12-25 | 制造半导体器件的方法 |
CNB991084586A Expired - Fee Related CN1153267C (zh) | 1994-12-26 | 1999-06-11 | 半导体器件的制造方法 |
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CN95113148A Expired - Fee Related CN1051641C (zh) | 1994-12-26 | 1995-12-25 | 制造半导体器件的方法 |
Country Status (6)
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US (1) | US5686353A (zh) |
EP (1) | EP0720226B1 (zh) |
KR (1) | KR100239286B1 (zh) |
CN (2) | CN1051641C (zh) |
DE (1) | DE69535551T2 (zh) |
TW (1) | TW288194B (zh) |
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1995
- 1995-12-21 US US08/576,160 patent/US5686353A/en not_active Expired - Lifetime
- 1995-12-22 EP EP95120500A patent/EP0720226B1/en not_active Expired - Lifetime
- 1995-12-22 TW TW084113772A patent/TW288194B/zh active
- 1995-12-22 DE DE69535551T patent/DE69535551T2/de not_active Expired - Fee Related
- 1995-12-25 CN CN95113148A patent/CN1051641C/zh not_active Expired - Fee Related
- 1995-12-26 KR KR1019950056321A patent/KR100239286B1/ko not_active IP Right Cessation
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1999
- 1999-06-11 CN CNB991084586A patent/CN1153267C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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EP0720226A2 (en) | 1996-07-03 |
CN1051641C (zh) | 2000-04-19 |
KR100239286B1 (ko) | 2000-01-15 |
CN1130306A (zh) | 1996-09-04 |
EP0720226A3 (en) | 1997-11-19 |
CN1248062A (zh) | 2000-03-22 |
EP0720226B1 (en) | 2007-08-08 |
DE69535551T2 (de) | 2008-04-30 |
DE69535551D1 (de) | 2007-09-20 |
KR960028730A (ko) | 1996-07-22 |
US5686353A (en) | 1997-11-11 |
TW288194B (zh) | 1996-10-11 |
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