CN1141506A - 形成半导体器件金属互连的方法 - Google Patents

形成半导体器件金属互连的方法 Download PDF

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CN1141506A
CN1141506A CN96104048A CN96104048A CN1141506A CN 1141506 A CN1141506 A CN 1141506A CN 96104048 A CN96104048 A CN 96104048A CN 96104048 A CN96104048 A CN 96104048A CN 1141506 A CN1141506 A CN 1141506A
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titanium nitride
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赵景洙
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MagnaChip Semiconductor Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations

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Abstract

本发明公开一种能提高成品率和可靠性的半导体器件的金属互连的方法,包括于先形成有源区再形成绝缘层的半导体衬底的预定部位处形成接触孔;用化学汽相淀积法在接触孔和绝缘层上依次淀积具有预定厚度的钛和氮化钛层;在N2气氛中进行热退火。最后,在扩散阻挡层上淀积低电阻率的互连金属,并在接触孔和绝缘层上形成各层的图形,由此形成有源区间的金属互连。另外,本发明还可包括在对所形成的各层构图之前淀积弧形薄膜的步骤。

Description

形成半导体器件金 属互连的方法
本发明涉及一种形成半导体器件的方法,尤其是涉及一种包括扩散阻挡金属层的半导体器件的金属互连的形成方法。
随着半导体器件集成度的提高,为使互连设计不受拘束及容易,并使电阻、电流容易可变,已研究出许多方法。
通常,铝被广泛用作半导体器件的金属互连材料。随着集成度的增加,互连线变细,所以电流密度增加。然而电流密度的增加会因电迁移、抗反射和应力转移而产生失效,由此导致可靠性的下降。为解决上述问题,已经有一种在铝(Al)互连上淀积铜(Cu)或钛(Ti)的方法,但这种方法会导致由小丘和晶须现象而产生的象绝缘失效和互连短路的严重问题。
图1是根据常规技术在形成扩散阻挡层后形成了金属互连的半导体器件的截面示意图。在常规方法中,首先在半导体衬底1上形成绝缘层2。此后,通过蚀刻绝缘层的某些部位直至露出衬底1的表面,从而在半导体衬底1的预定区域形成接触孔。接着,用物理汽相淀积法依次形成钛(Ti)扩散阻挡层3和氮化钛(TiN)4。最后用金属铝或铝合金在氮化钛层4上形成金属互连8。
然而,随着器件高集成度的发展,接触孔尺寸一般越来越小,接触孔的高宽比随接触孔尺寸的减小而增加。因而在如上所述用物理汽相淀积形成扩散阻挡层时,由于所淀积的扩散阻挡层的不平整使台阶覆盖变差。此外,在扩散阻挡层厚度增加时,接触孔的上部棱角会发生阴影效应,从而使后续工艺无法进行。另外,在采用TiCl4与NH3反应的化学汽相淀积方法来增强台阶覆盖时,存在颗粒过量产生的问题。因此,结果是器件的成品率和可靠性下降,而且,此时会因在TiN淀积期间物相变成非晶相而导致的器件内阻的增加而产生器件速度降低的问题。
因此,本发明的目的是提供一种形成半导体器件金属互连的方法,该方法能够通过增强扩散阻挡层的台阶覆盖和降低内阻及颗粒的产生来提高半导体器件的成品率和可靠性。
为实现本发明的目的,首先在其内形成有源区,然后在其上形成绝缘层的半导体衬底的预定部位形成接触孔。接着用化学汽相淀积法在接触孔和绝缘层上依次淀积均具有预定厚度的钛和氮化钛层。下一步是为改变所淀积的氮化钛层的物相和所变换的每一层中N2的含量而进行的氮气氛下的热退火。最后,在扩散阻挡层上淀积低电阻率的互连金属,由此形成使有源区相互连接的金属互连,之后,在接触孔和绝缘层上形成所有层的图形。
另一方面,本发明也可以还包括淀积弧形薄膜的步骤,该弧形薄膜(arc-thin film)可防止在所形成的各层的图形前,在互连金属上发生光的反射。
图1是表示根据传统的实例的形成金属互连的方法的剖面示意图。
图2A至2D分别是表示根据本发明实施例的形成金属互连的顺序工艺过程的剖面示意图。
下文参照图2A至2D对本发明的优选实施例进行描述。
图2A至2D是表示根据本发明实施例的形成金属互连的顺序工艺过程的剖面示意图。首先,参照图2A,在包括有源区的半导体衬底1上淀积绝缘层2。然后,采用对曝露的绝缘层进行腐蚀直至露出半导体衬底1的表面为止的光刻法,在绝缘层2的预定部位形成接触孔。然后,如图2B所示,在接触孔的内部和绝缘层2的整个表面上淀积钛层3,钛层3是采用TiCl4与NH3或NF3反应的化学汽相淀积法形成的非常薄的膜,它薄的能保持接触孔2的形状。采用化学汽相淀积法是为了增强接触孔内侧的台阶覆盖。然后,在钛层3上形成氮化钛层4。用化学汽相淀积法形成氮化钛层4,以抑制颗粒的产生。换句话说,该方法仅采用四二甲基氨基钛[Ti(N(CH3)2}4]或四二乙基氨基钛[Ti{N(C2H5)4}]原料并采用热退火法由所说两种化合物之一分解出氮化钛,其中热退火中所用气体为氮和/或氦。TiN的淀积温度范围在300~500℃,炉子的压力控制在5~10mTorr范围,所形成的是非晶层。此后,在400~600℃的氮气氛中对形成了上述各层的半导体衬底进行热退火。通过退火工艺就将氮化钛层4转变成了物理性质各不相同的三个氮化钛层5、6、7。下层或第一层是由以非晶层形态存在的氮化钛5组成,中间层或第二层是由以结晶层形态存在的氮化钛6组成,上层或第三层是由以富氮结晶层形态存在的氮化钛7组成。这里也可采用代表常规的热退火工艺的快速热退火(RTA)方法,即可在700~900℃温度范围下进行10至30秒的退火。单层的氮化钛4因处于非晶态而具有很高的电阻,但三层氮化钛5、6、7与单层氮化钛4相比却因其物理性质互不相同而具有低电阻。钛层3和氮化钛层5、6、7都充当扩散阻挡金属用以防止没有阻挡存在时会发生的金属原子扩散。此后,如图2C所示,一种例如铝、铜或铝和铜的合金等的互连金属在扩散阻挡层上形成,其中互连金属通过在扩散阻挡层上淀积任何具有低阻的金属将有源区彼此连接起来。以后用化学汽相淀积法在金属层8上形成弧形金属层(arc-metal layer)9。这里弧形金属层9是用来防止为形成金属互连图形而进行曝光时,在互连金属上光的反射。该弧形薄膜是由四二甲基氨基钛或四二乙基氨基钛组成,淀积的温度为300~450℃,根据各自的情况,形成弧形薄膜9的步骤还是可以省略的。
最后,如图2D所示,通过对所说金属层3、5、6、7、8、9的构图来构成金属互连。金属层8可用象钨这样的具有高电导率的金属代替。
如上面对发明的详细描述所述,本发明可以减小氮化钛的电阻和减少颗粒的产生,还能通过把单层的氮化钛转换成具有各自特性的三层氮化钛来增强台阶覆盖。形成这三层的方法包括:热分解包含钛和氮的原材料形成氮化钛,在氮气氛下对所淀积的氮化钛进行退火。由此,本发明具有既增强器件可靠性,提高成品率又提高信号传输速度的有益效果。
对于阅读了上述本发明所公开的内容后的本领域普通技术人员来说,这里所公开的本发明的其它特征、优点和实施例是很容易想到的。关于这一点,尽管对本发明的具体实施例做了尽可能详细地描述,但在不脱离如权利要求书所述的本发明的精神和范围的情况下,可以对这些实施例做出各种变化和改进。

Claims (13)

1、一种形成半导体器件金属互连的方法,包括以下步骤:
在形成了绝缘层的半导体衬底的预定部位处,形成接触孔;
在所说绝缘层和所说接触孔上用化学汽相淀积法依次淀积钛层和氮化钛层,这两层都具备预先确定的厚度;
在氮气氛中热退火所说衬底,其中所说氮化钛层发生相转换,形成多层氮化钛层,每层含氮量各不同,并且相态也各不相同;
在氮化钛层上淀积低电阻率的金属层;和对在接触孔和绝缘层上形成的各层进行构图。
2、根据权利要求1的方法,其中所说的钛是由TiCl4与NH3反应的化学汽相淀积法形成的。
3、根据权利要求1的方法,其中所说的氮化钛是由四二甲基氨基钛的热分解形成的。
4、根据权利要求1的方法,其中所说氮化钛是由四二乙基氨基钛的热分解形成的。
5、根据权利要求3的方法,其中所说的热分解是在300~500℃的温度、5~10mTorr的压力的条件下进行的。
6、根据权利要求4的方法,其中所说热分解是在300~500℃的温度,5~10mTorr的压力条件下进行的。
7、根据权利要求1的方法,其中进行氮化钛物相转换的热退火是在氮气氛和400~600℃的温度下进行30~60分钟完成的。
8、根据权利要求1的方法,其中进行氮化钛物相转换的热退火是在氮气氛和700~900℃温度下,进行10~30秒快速热退火完成的。
9、根据权利要求1的方法,其中所说互连金属是铝或铜。
10、根据权利要求9的方法,其中所说方法还包括在形成所说金属互连的构图步骤前为防止铜或铝的反射的弧形薄膜的步骤。
11、根据权利要求10的方法,其中所说弧形薄膜是由钛组成。
12、根据权利要求10的方法,其中所说氮化钛是由在300~450℃下热分解四二乙基氨基钛形成的。
13、根据权利要求10的方法,其中所说氮化钛是由在300~450℃下热分解四二甲基氨基钛形成的。
CN96104048A 1995-03-04 1996-03-04 形成半导体器件金属互连的方法 Expired - Fee Related CN1057868C (zh)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100385660C (zh) * 2004-12-01 2008-04-30 台湾积体电路制造股份有限公司 改善电子迁移的半导体元件与半导体元件的形成方法
US7518247B2 (en) 2002-11-29 2009-04-14 Nec Corporation Semiconductor device and its manufacturing method
CN1582492B (zh) * 2001-11-07 2010-04-28 因芬尼昂技术股份公司 具低电阻含金属薄层的制造方法
CN101459174B (zh) * 2007-12-13 2010-07-07 和舰科技(苏州)有限公司 一种半导体晶片的导电结构及其制造方法
CN101165873B (zh) * 2006-10-17 2011-07-06 瑞萨电子株式会社 半导体装置的制造方法
CN102810504A (zh) * 2011-05-31 2012-12-05 无锡华润上华半导体有限公司 厚铝生长工艺方法
CN101017793B (zh) * 2007-02-16 2013-06-05 上海集成电路研发中心有限公司 一种扩散阻挡层的制作方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100430684B1 (ko) * 1996-12-31 2004-07-30 주식회사 하이닉스반도체 반도체소자의금속배선형성방법
JP3040715U (ja) * 1997-02-19 1997-08-26 株式会社熊谷 包装袋
KR100480576B1 (ko) * 1997-12-15 2005-05-16 삼성전자주식회사 반도체장치의금속배선형성방법
KR100494320B1 (ko) * 1997-12-30 2005-08-31 주식회사 하이닉스반도체 반도체소자의확산방지막형성방법
KR100559028B1 (ko) * 1998-12-29 2006-06-15 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성 방법
KR100495856B1 (ko) * 1998-12-30 2005-09-02 주식회사 하이닉스반도체 반도체 소자의 구리 금속 배선 형성 방법
JP3562628B2 (ja) * 1999-06-24 2004-09-08 日本電気株式会社 拡散バリア膜、多層配線構造、およびそれらの製造方法
US6569751B1 (en) * 2000-07-17 2003-05-27 Lsi Logic Corporation Low via resistance system
JP4222841B2 (ja) * 2003-01-15 2009-02-12 三洋電機株式会社 半導体装置の製造方法
TW200526806A (en) * 2004-01-15 2005-08-16 Tokyo Electron Ltd Film-forming method
US7253501B2 (en) * 2004-08-03 2007-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. High performance metallization cap layer

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0174743A3 (en) * 1984-09-05 1988-06-08 Morton Thiokol, Inc. Process for transition metal nitrides thin film deposition
EP0613180A3 (en) * 1985-05-13 1994-10-19 Toshiba Kk Semiconductor device comprising interconnection electrodes.
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
EP0448763A1 (de) * 1990-03-30 1991-10-02 Siemens Aktiengesellschaft Verfahren und Vorrichtung zur Herstellung von leitenden Schichten oder Strukturen für höchstintegrierte Schaltungen
US5136362A (en) * 1990-11-27 1992-08-04 Grief Malcolm K Electrical contact with diffusion barrier
EP0514103A1 (en) * 1991-05-14 1992-11-19 STMicroelectronics, Inc. Barrier metal process for sub-micron contacts
US5242860A (en) * 1991-07-24 1993-09-07 Applied Materials, Inc. Method for the formation of tin barrier layer with preferential (111) crystallographic orientation
US5308655A (en) * 1991-08-16 1994-05-03 Materials Research Corporation Processing for forming low resistivity titanium nitride films
US5462895A (en) * 1991-09-04 1995-10-31 Oki Electric Industry Co., Ltd. Method of making semiconductor device comprising a titanium nitride film
JPH05121378A (ja) * 1991-10-29 1993-05-18 Sony Corp 半導体装置の製造方法
US5254499A (en) * 1992-07-14 1993-10-19 Micron Technology, Inc. Method of depositing high density titanium nitride films on semiconductor wafers
JP2570576B2 (ja) * 1993-06-25 1997-01-08 日本電気株式会社 半導体装置の製造方法
US5494860A (en) * 1995-03-14 1996-02-27 International Business Machines Corporation Two step annealing process for decreasing contact resistance

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1582492B (zh) * 2001-11-07 2010-04-28 因芬尼昂技术股份公司 具低电阻含金属薄层的制造方法
US7518247B2 (en) 2002-11-29 2009-04-14 Nec Corporation Semiconductor device and its manufacturing method
CN100385660C (zh) * 2004-12-01 2008-04-30 台湾积体电路制造股份有限公司 改善电子迁移的半导体元件与半导体元件的形成方法
CN101165873B (zh) * 2006-10-17 2011-07-06 瑞萨电子株式会社 半导体装置的制造方法
CN101017793B (zh) * 2007-02-16 2013-06-05 上海集成电路研发中心有限公司 一种扩散阻挡层的制作方法
CN101459174B (zh) * 2007-12-13 2010-07-07 和舰科技(苏州)有限公司 一种半导体晶片的导电结构及其制造方法
CN102810504A (zh) * 2011-05-31 2012-12-05 无锡华润上华半导体有限公司 厚铝生长工艺方法

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KR960035843A (ko) 1996-10-28
JPH08250596A (ja) 1996-09-27
JP2000082742A (ja) 2000-03-21
KR0148325B1 (ko) 1998-12-01
GB9604614D0 (en) 1996-05-01
DE19608208B4 (de) 2006-02-23
TW288171B (zh) 1996-10-11
JP3122845B2 (ja) 2001-01-09
CN1057868C (zh) 2000-10-25
DE19608208A1 (de) 1996-09-05
GB2298657B (en) 1998-09-30

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