CN113224169A - 一种折叠栅氧化镓基场效应晶体管 - Google Patents

一种折叠栅氧化镓基场效应晶体管 Download PDF

Info

Publication number
CN113224169A
CN113224169A CN202110493781.2A CN202110493781A CN113224169A CN 113224169 A CN113224169 A CN 113224169A CN 202110493781 A CN202110493781 A CN 202110493781A CN 113224169 A CN113224169 A CN 113224169A
Authority
CN
China
Prior art keywords
gate
metal
gallium oxide
drain
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110493781.2A
Other languages
English (en)
Other versions
CN113224169B (zh
Inventor
罗小蓉
魏雨夕
鲁娟
杨可萌
魏杰
蒋卓林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN202110493781.2A priority Critical patent/CN113224169B/zh
Publication of CN113224169A publication Critical patent/CN113224169A/zh
Application granted granted Critical
Publication of CN113224169B publication Critical patent/CN113224169B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22

Abstract

本发明属于功率半导体技术领域,涉及一种折叠栅氧化镓基场效应晶体管。本发明针对氧化镓材料P型掺杂困难且增强型器件难以兼顾低导通电阻的问题,提出一种兼具高阈值电压和低导通电阻的横向增强型氧化镓场效应晶体管。利用金属与氧化镓的功函数差将鳍型导电沟道夹断,从而实现关断和高耐压,获得低泄漏电流及硬雪崩击穿特性;当栅压高于阈值电压,鳍型导电沟道侧壁形成电子积累层且折叠栅结构增加沟道密度,导通电阻大大降低。本发明的有益效果为,本发明的器件兼具高阈值电压和低导通电阻的优点且易于集成。

Description

一种折叠栅氧化镓基场效应晶体管
技术领域
本发明属于功率半导体技术领域,涉及一种折叠栅氧化镓基场效应晶体管。
背景技术
氧化镓材料具有超宽禁带(Eg=4.5-4.9eV)和高击穿电场(8MV/cm),氧化镓基功率器件的Baliga优值为GaN的4倍、SiC的10倍以及Si的3444倍。因此,氧化镓有望成为高压、大功率、低损耗功率器件的优选材料,满足高功率密度、高转换效率及小型轻量化的电源系统需求。
具有误开启自保护功能的增强型器件是电力电子系统中的器件首要标配特性,也是器件实现低功率损耗的必要条件。由于氧化镓尚未实现有效的P型掺杂,氧化镓增强型MOSFET器件研制面临挑战。目前,横向增强型氧化镓MOSFET的实现主要是通过凹槽栅结构(参见文献Kelson D.Chabak,et al.,Recessed-Gate Enhancement-Modeβ-Ga2O3 MOSFETs,IEEE Electron Device Letters,vol.39,no.1,pp.67-70,2018),该结构使氧化镓MOSFET的阈值电压达到4V,其基本思想是降低沟道有效载流子浓度,但使导通电阻大幅提高,难以实现低功率损耗的目的。为了在实现增强型的同时改善沟道电阻,有研究者提出具有鳍栅结构的垂直增强型氧化镓MOSFET(Zongyang Hu,et al.,1.6kV Vertical Ga2O3 FinFETsWith Source Connected Field Plates and Normally-off Operation,IEEE ISPSD2019,pp.483-486),通过利用鳍栅两侧MIS(Metal-Insulator-Semiconductor)结构的耗尽作用夹断沟道,实现高达4V的阈值电压,当器件导通时,鳍栅侧壁形成电子积累层,构成低阻通道,有助于实现较低的导通电阻。然而,相较于横向功率器件,纵向功率器件与工艺的兼容性较差,不易于集成。因此,如何同时实现横向增强型氧化镓MOSFET的高阈值电压和低导通电阻成为目前亟待解决的关键问题之一。
发明内容
本发明针对上述存在的问题,提出一种折叠栅氧化镓基场效应晶体管,不但兼具高阈值电压和低导通电阻,而且作为横向器件,易于集成且不大幅增加工艺复杂度。
本发明的技术方案为:
一种折叠栅氧化镓基场效应晶体管,包括衬底层1、位于衬底层1上表面的缓冲层2、位于缓冲层2上表面的外延层3;沿器件横向方向,所述外延层3上部的一端具有源区4,另一端具有漏区5,所述源区4上表面部分覆盖源极金属6,所述漏区5上表面部分覆盖漏极金属7;所述源区4和漏区5之间的外延层3中具有栅区,所述栅区不与源区4和漏区5相接触,其特征在于,沿器件纵向方向,所述栅区由两个或两个以上深度相同且等间距排列的槽型区构成,所述槽型区的槽壁、槽底和槽型区之间的外延层3上表面覆盖有栅介质层9,所述栅介质层9上表面覆盖栅极金属8且栅极金属8填充所述槽型区;所述栅极金属8和源极金属6之间、漏极金属7之间具有钝化介质层10;器件纵向方向是指同时垂直于器件横向方向和器件水平方向的第三维度方向。
进一步的,所述源极金属6顶部向漏极金属7方向延伸,部分覆盖钝化介质层10并终止于栅极金属8和漏极金属7之间的钝化介质层10上表面,且不与栅极金属8和漏极金属7接触。
进一步的,所述栅极金属8顶部向漏极金属7方向延伸且不与漏极金属7相接触,所述栅极金属8的延伸部分和外延层3之间具有钝化介质层10。
进一步的,所述栅区和漏区5之间的外延层3掺杂浓度从靠近栅区一侧到靠近漏区5一侧逐渐增加。
本发明的有益效果为,本发明的器件兼具高阈值电压和低导通电阻的优点。
附图说明
图1是本发明实施例1的结构示意图;
图2是带有辅助线的本发明实施例1的结构示意图;
图3是实施例1中沿A1A2线的截面图;
图4是实施例1中沿B1B2线的截面图;
图5是实施例1中沿C1C2线的截面图;
图6是实施例1中沿D1D2线的截面图;
图7是本发明实施例2的结构示意图;
图8是本发明实施例3的结构示意图;
图9是本发明实施例4的结构示意图。
具体实施方式
下面结合附图和实施例,详细描述本发明的技术方案:
如图中所示的三维坐标系,与本发明中的描述相对应的关系是:本发明中所述的横向方向对应x轴方向,垂直方向对应y轴方向,纵向方向对应z轴方向。
实施例1:
如图1所示,包括衬底层1、位于衬底层1上表面的缓冲层2、位于缓冲层2上表面的外延层3;沿器件横向方向,所述外延层3上部的一端具有源区4,另一端具有漏区5,所述源区4上表面部分覆盖源极金属6,所述漏区5上表面部分覆盖漏极金属7;所述源区4和漏区5之间的外延层3中具有栅区,所述栅区不与源区4和漏区5相接触,其特征在于,沿器件纵向方向,所述栅区由两个或两个以上深度相同且等间距排列的槽型区构成,所述槽型区的槽壁、槽底和槽型区之间的外延层3上表面覆盖有栅介质层9,所述栅介质层9上表面覆盖栅极金属8且栅极金属8填充所述槽型区;所述栅极金属8和源极金属6之间、漏极金属7之间具有钝化介质层10。
本例的工作原理为:
本发明提出的一种折叠栅氧化镓基场效应晶体管,通过形成鳍型沟道区,在鳍两侧构建MIS结构,栅压为0V时,利用金属与氧化镓的功函数差将鳍型导电沟道夹断,从而实现关断和高耐压,获得低泄漏电流及硬雪崩击穿特性;当栅压高于阈值电压,沟道开启并且在侧壁形成电子积累层,构成低阻通道以减小导通电阻;折叠栅结构增加了沟道密度,使得器件沟道电阻减小,导通电阻大大降低。本发明的器件解决了氧化镓无法实现P型掺杂形成传统导电沟道的难题,同时提高了器件栅控能力和跨导,而且MIS结构降低了泄漏电流和关断功耗;通过选择栅极金属,可以调节阈值电压和输出电流能力。沿器件纵向方向可同时形成多个鳍型沟道区单元,便于制作大电流和大功率器件。因此,本发明的器件兼具高阈值电压和低导通电阻的优点且易于集成。
实施例2:
如图7所示,本实施例与实施例1的区别在于,源极金属6顶部向漏极金属7方向延伸,部分覆盖钝化介质层10并终止于栅极金属8和漏极金属7之间的钝化介质层10上表面,且不与栅极金属8和漏极金属7接触,形成源场板,调制电场分布,提高器件击穿电压。
实施例3:
如图8所示,本实施例与实施例1的区别在于,栅极金属8顶部向漏极金属7方向延伸且不与漏极金属7相接触,所述栅极金属8的延伸部分和外延层3之间具有钝化介质层10,形成延伸栅场板。在正向时,延伸栅场板下方的外延层表面形成电子积累层,进一步减小导通电阻;在反向时,延伸栅场板不但调制电场分布以提高器件击穿电压,而且具有辅助耗尽作用,可以增加器件外延层的掺杂浓度从而有助于降低器件的导通电阻。
实施例4:
如图9所示,本实施例与实施例1的区别在于,栅区和漏区5之间的外延层3掺杂浓度从靠近栅区一侧到靠近漏区5一侧逐渐增加。线性变化的掺杂浓度能够调制栅漏之间的电场分布,提高器件的击穿电压。

Claims (4)

1.一种折叠栅氧化镓基场效应晶体管,包括衬底层(1)、位于衬底层(1)上表面的缓冲层(2)、位于缓冲层(2)上表面的外延层(3);沿器件横向方向,所述外延层(3)上部的一端具有源区(4),另一端具有漏区(5),所述源区(4)上表面部分覆盖源极金属(6),所述漏区(5)上表面部分覆盖漏极金属(7);所述源区(4)和漏区(5)之间的外延层(3)中具有栅区,所述栅区不与源区(4)和漏区(5)相接触,其特征在于,沿器件纵向方向,所述栅区由两个或两个以上深度相同且等间距排列的槽型区构成,所述槽型区的槽壁、槽底和槽型区之间的外延层(3)上表面覆盖有栅介质层(9),所述栅介质层(9)上表面覆盖栅极金属(8)且栅极金属(8)填充所述槽型区;所述栅极金属(8)和源极金属(6)之间、漏极金属(7)之间具有钝化介质层(10)。
2.根据权利要求1所述的一种折叠栅氧化镓基场效应晶体管,其特征在于,所述源极金属(6)顶部向漏极金属(7)方向延伸,部分覆盖钝化介质层(10)并终止于栅极金属(8)和漏极金属(7)之间的钝化介质层(10)上表面,且不与栅极金属(8)和漏极金属(7)接触。
3.根据权利要求1所述的一种折叠栅氧化镓基场效应晶体管,其特征在于,所述栅极金属(8)顶部向漏极金属(7)方向延伸且不与漏极金属(7)相接触,所述栅极金属(8)的延伸部分和外延层(3)之间具有钝化介质层(10)。
4.根据权利要求1所述的一种折叠栅氧化镓基场效应晶体管,其特征在于,所述栅区和漏区(5)之间的外延层(3)掺杂浓度从靠近栅区一侧到靠近漏区(5)一侧逐渐增加。
CN202110493781.2A 2021-05-07 2021-05-07 一种折叠栅氧化镓基场效应晶体管 Active CN113224169B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110493781.2A CN113224169B (zh) 2021-05-07 2021-05-07 一种折叠栅氧化镓基场效应晶体管

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110493781.2A CN113224169B (zh) 2021-05-07 2021-05-07 一种折叠栅氧化镓基场效应晶体管

Publications (2)

Publication Number Publication Date
CN113224169A true CN113224169A (zh) 2021-08-06
CN113224169B CN113224169B (zh) 2023-02-07

Family

ID=77091276

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110493781.2A Active CN113224169B (zh) 2021-05-07 2021-05-07 一种折叠栅氧化镓基场效应晶体管

Country Status (1)

Country Link
CN (1) CN113224169B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114823858A (zh) * 2022-04-28 2022-07-29 电子科技大学 新型结构氧化镓场效应晶体管功率器件
CN116666440A (zh) * 2023-07-26 2023-08-29 浙江朗德电子科技有限公司 一种底栅极mos管及制作方法

Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769685A (en) * 1986-10-27 1988-09-06 General Motors Corporation Recessed-gate junction-MOS field effect transistor
JPH09219512A (ja) * 1995-12-02 1997-08-19 Lg Semicon Co Ltd Mos電界効果トランジスタ及びその製造方法
CN104112774A (zh) * 2014-01-14 2014-10-22 西安后羿半导体科技有限公司 一种横向双扩散金属氧化物半导体场效应管
CN104183646A (zh) * 2014-08-29 2014-12-03 电子科技大学 一种具有延伸栅结构的soi ldmos器件
CN104201206A (zh) * 2014-08-29 2014-12-10 电子科技大学 一种横向soi功率ldmos器件
US20150034958A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Co., Ltd. Hemt-compatible lateral rectifier structure
WO2016008326A1 (zh) * 2014-07-15 2016-01-21 华为技术有限公司 隧穿场效应晶体管及隧穿场效应晶体管的制备方法
CN105633137A (zh) * 2016-01-08 2016-06-01 电子科技大学 一种槽栅功率mosfet器件
CN106024858A (zh) * 2016-05-19 2016-10-12 电子科技大学 一种具有三栅结构的hk soi ldmos器件
CN106920849A (zh) * 2017-04-21 2017-07-04 吉林大学 一种散热性好的Ga2O3基金属氧化物半导体场效应晶体管及其制备方法
CN106981507A (zh) * 2017-03-29 2017-07-25 苏州捷芯威半导体有限公司 半导体器件及其制造方法
CN107464844A (zh) * 2017-07-20 2017-12-12 中国电子科技集团公司第十三研究所 氧化镓场效应晶体管的制备方法
CN108615769A (zh) * 2018-05-25 2018-10-02 中国电子科技集团公司第十三研究所 氧化镓mosfet器件的制备方法
US20180294335A1 (en) * 2017-04-07 2018-10-11 University Of Electronic Science And Technology Of China Polarization-doped enhancement mode hemt
CN109103259A (zh) * 2018-08-21 2018-12-28 电子科技大学 一种积累型dmos器件
US20190027590A1 (en) * 2017-07-20 2019-01-24 The 13Th Research Institute Of China Electronics Technology Group Corporation Method for preparing cap-layer-structured gallium oxide field effect transistor
CN109817712A (zh) * 2019-03-26 2019-05-28 电子科技大学 一种具有多导电沟道及鳍式栅的增强型hemt器件
CN109888016A (zh) * 2019-01-08 2019-06-14 上海华虹宏力半导体制造有限公司 Nldmos器件及其制造方法
CN110571275A (zh) * 2019-09-17 2019-12-13 中国科学技术大学 氧化镓mosfet的制备方法
CN110634938A (zh) * 2018-06-22 2019-12-31 中国科学院苏州纳米技术与纳米仿生研究所 氧化镓垂直结构半导体电子器件及其制作方法
CN111276541A (zh) * 2020-02-10 2020-06-12 中国科学院半导体研究所 常关型场效应晶体管及其制备方法
CN111370470A (zh) * 2020-03-12 2020-07-03 电子科技大学 氮化镓mis栅控混合沟道功率场效应晶体管及其制造方法
CN111725070A (zh) * 2020-07-16 2020-09-29 杰华特微电子(杭州)有限公司 半导体器件的制作方法及半导体器件
US20200350166A1 (en) * 2019-04-17 2020-11-05 Ferechteh Hosseini Teherani Method of manufacturing p-type gallium oxide by intrinsic doping, the thin film obtained from gallium oxide and its use

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769685A (en) * 1986-10-27 1988-09-06 General Motors Corporation Recessed-gate junction-MOS field effect transistor
JPH09219512A (ja) * 1995-12-02 1997-08-19 Lg Semicon Co Ltd Mos電界効果トランジスタ及びその製造方法
US20150034958A1 (en) * 2013-08-01 2015-02-05 Taiwan Semiconductor Manufacturing Co., Ltd. Hemt-compatible lateral rectifier structure
CN104112774A (zh) * 2014-01-14 2014-10-22 西安后羿半导体科技有限公司 一种横向双扩散金属氧化物半导体场效应管
WO2016008326A1 (zh) * 2014-07-15 2016-01-21 华为技术有限公司 隧穿场效应晶体管及隧穿场效应晶体管的制备方法
CN104183646A (zh) * 2014-08-29 2014-12-03 电子科技大学 一种具有延伸栅结构的soi ldmos器件
CN104201206A (zh) * 2014-08-29 2014-12-10 电子科技大学 一种横向soi功率ldmos器件
CN105633137A (zh) * 2016-01-08 2016-06-01 电子科技大学 一种槽栅功率mosfet器件
CN106024858A (zh) * 2016-05-19 2016-10-12 电子科技大学 一种具有三栅结构的hk soi ldmos器件
CN106981507A (zh) * 2017-03-29 2017-07-25 苏州捷芯威半导体有限公司 半导体器件及其制造方法
US20180294335A1 (en) * 2017-04-07 2018-10-11 University Of Electronic Science And Technology Of China Polarization-doped enhancement mode hemt
CN106920849A (zh) * 2017-04-21 2017-07-04 吉林大学 一种散热性好的Ga2O3基金属氧化物半导体场效应晶体管及其制备方法
CN107464844A (zh) * 2017-07-20 2017-12-12 中国电子科技集团公司第十三研究所 氧化镓场效应晶体管的制备方法
US20190027590A1 (en) * 2017-07-20 2019-01-24 The 13Th Research Institute Of China Electronics Technology Group Corporation Method for preparing cap-layer-structured gallium oxide field effect transistor
CN108615769A (zh) * 2018-05-25 2018-10-02 中国电子科技集团公司第十三研究所 氧化镓mosfet器件的制备方法
CN110634938A (zh) * 2018-06-22 2019-12-31 中国科学院苏州纳米技术与纳米仿生研究所 氧化镓垂直结构半导体电子器件及其制作方法
CN109103259A (zh) * 2018-08-21 2018-12-28 电子科技大学 一种积累型dmos器件
CN109888016A (zh) * 2019-01-08 2019-06-14 上海华虹宏力半导体制造有限公司 Nldmos器件及其制造方法
CN109817712A (zh) * 2019-03-26 2019-05-28 电子科技大学 一种具有多导电沟道及鳍式栅的增强型hemt器件
US20200350166A1 (en) * 2019-04-17 2020-11-05 Ferechteh Hosseini Teherani Method of manufacturing p-type gallium oxide by intrinsic doping, the thin film obtained from gallium oxide and its use
CN110571275A (zh) * 2019-09-17 2019-12-13 中国科学技术大学 氧化镓mosfet的制备方法
CN111276541A (zh) * 2020-02-10 2020-06-12 中国科学院半导体研究所 常关型场效应晶体管及其制备方法
CN111370470A (zh) * 2020-03-12 2020-07-03 电子科技大学 氮化镓mis栅控混合沟道功率场效应晶体管及其制造方法
CN111725070A (zh) * 2020-07-16 2020-09-29 杰华特微电子(杭州)有限公司 半导体器件的制作方法及半导体器件

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
KELSON D. CHABAK; JONATHAN P. MCCANDLESS;NEIL A.MOSER; AND ETAL.: "Recessed-Gate Enhancement-Modeβ-Ga2O3 MOSFETs", 《IEEE ELECTRON DEVICE LETTERS》 *
LV, YUANJIE,ZHOU, XINGYE,LONG, SHIBING,AND ETAL.: "Enhancement-Mode beta-Ga2O3 Metal-Oxide-Semiconductor Field-Effect Transistor with High Breakdown Voltage over 3000 V Realized by Oxygen Annealing", 《IEEE ELECTRON DEVICE LETTERS》 *
ZHOU, XUANZE,LIU, QI,XU, GUANGWEI,AND ETAL.: "Realizing High-Performance beta-Ga2O3 MOSFET by Using Variation of Lateral Doping: A TCAD Study", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 *
ZONGYANG HU; KAZUKI NOMOTO; WENSHEN LI;AND ETAL.: "1.6 kV Vertical Ga2O3 FinFETs With Source-Connected Field Plates and Normally-off Operation", 《2019 31ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD)》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114823858A (zh) * 2022-04-28 2022-07-29 电子科技大学 新型结构氧化镓场效应晶体管功率器件
CN114823858B (zh) * 2022-04-28 2024-01-26 电子科技大学 新型结构氧化镓场效应晶体管功率器件
CN116666440A (zh) * 2023-07-26 2023-08-29 浙江朗德电子科技有限公司 一种底栅极mos管及制作方法
CN116666440B (zh) * 2023-07-26 2023-12-26 浙江朗德电子科技有限公司 一种底栅极mos管及制作方法

Also Published As

Publication number Publication date
CN113224169B (zh) 2023-02-07

Similar Documents

Publication Publication Date Title
Chu GaN power switches on the rise: Demonstrated benefits and unrealized potentials
CN109920854B (zh) Mosfet器件
CN113130627B (zh) 一种集成沟道二极管的碳化硅鳍状栅mosfet
CN107482059B (zh) 一种GaN异质结纵向逆导场效应管
CN113224169B (zh) 一种折叠栅氧化镓基场效应晶体管
WO2019157819A1 (zh) 一种具有三维沟道的复合栅igbt芯片
CN112802906B (zh) 带浮栅的分离栅平面型mosfet器件
CN111739934A (zh) 一种具有结型场板的氮化镓高电子迁移率晶体管
CN111969047B (zh) 一种具有复合背势垒层的氮化镓异质结场效应晶体管
CN114447102A (zh) 具有衬底上复合半导体层的氮化镓异质结场效应晶体管
CN111370470B (zh) 氮化镓mis栅控混合沟道功率场效应晶体管及其制造方法
CN113594248A (zh) 一种具有集成续流二极管的双异质结GaN HEMT器件
CN111933711B (zh) 一种集成sbd的超结mosfet
CN113257887A (zh) 一种具有三种区域的4H-SiC金属半导体场效应晶体管
CN107393954A (zh) 一种GaN异质结纵向场效应管
CN111341850A (zh) 一种GaN纵向逆导结场效应管
CN116913951A (zh) 一种具有P型埋层的双沟道增强型GaN HEMT器件
CN114843332A (zh) 低功耗高可靠性半包沟槽栅mosfet器件及制备方法
CN111293176B (zh) 一种GaN纵向逆导结场效应管
CN111969041B (zh) 一种超结vdmos
CN212967713U (zh) 一种具有均匀掺杂沟道的屏蔽栅mosfet器件
CN113707727B (zh) 一种具有倒梯形槽的垂直GaN二极管
CN112885896B (zh) 一种hemt器件
CN109119462B (zh) 一种碳化硅沟槽mos器件
CN114068677B (zh) 一种AlGaN沟槽的增强型高压GaN基垂直HFET装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant