WO2016008326A1 - 隧穿场效应晶体管及隧穿场效应晶体管的制备方法 - Google Patents

隧穿场效应晶体管及隧穿场效应晶体管的制备方法 Download PDF

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WO2016008326A1
WO2016008326A1 PCT/CN2015/077666 CN2015077666W WO2016008326A1 WO 2016008326 A1 WO2016008326 A1 WO 2016008326A1 CN 2015077666 W CN2015077666 W CN 2015077666W WO 2016008326 A1 WO2016008326 A1 WO 2016008326A1
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gate
region
layer
field effect
effect transistor
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PCT/CN2015/077666
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English (en)
French (fr)
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杨喜超
赵静
张臣雄
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a method for fabricating a tunneling field effect transistor and a tunneling field effect transistor.
  • CMOS Complementary Metal Oxide Semiconductor
  • COMS Complementary Metal Oxide Semiconductor
  • TFET Tunnel Field Effect Transistor
  • the tunneling direction of carriers during the operation of the current TFET is not in the same direction as the gate electric field, that is, the point tunneling mechanism. Therefore, in the prior art, the point tunneling mechanism is used to cause low carrier tunneling efficiency, which causes the TFET to have a small tunneling current, and the subthreshold swing is difficult to reach 60 mV/dec.
  • a tunneling field effect transistor which adopts a line tunneling mechanism to improve carrier tunneling efficiency of a tunneling field effect transistor, has a high driving current and a steep subthreshold swing, and the device adopts a three-dimensional structure Increase the integration density of the chip.
  • a tunneling field effect transistor comprising:
  • a source region disposed on the first doping type substrate and disposed around the channel;
  • An epitaxial layer disposed on the source region and disposed around the channel;
  • a gate dielectric layer disposed on the epitaxial layer and disposed around the channel
  • a gate region disposed around the channel and disposed on the source region through the epitaxial layer
  • a drain region is disposed at an end of the channel away from the substrate.
  • the tunneling field effect transistor further includes:
  • the tunneling field effect transistor further includes:
  • a first isolation layer disposed on the source region, the first isolation layer is formed with a first through hole, and the source passes through the first through hole to connect the source region;
  • a second isolation layer is disposed on the gate region, the second isolation layer is formed with a second through hole, and the gate passes through the second through hole to connect the gate region.
  • the tunneling field effect transistor further includes:
  • first isolation layer disposed on the source region, the first isolation layer being formed with a first through hole
  • a second isolation layer disposed on the first isolation layer and the gate region, wherein the second isolation layer is formed with a second through hole corresponding to the first through hole and a corresponding portion of the gate region
  • the source is connected to the source region through the first through hole and the second through hole, and the gate is connected to the gate region through the third through hole.
  • the tunneling field effect transistor further includes:
  • a first ohmic contact layer the source being connected to the source region through the first ohmic contact layer.
  • the tunneling field effect transistor further includes:
  • a second ohmic contact layer the gate being connected to the gate region through the second ohmic contact layer.
  • the gate dielectric layer includes a first portion and a second portion of the first portion being connected, the first portion is disposed on the epitaxial layer and disposed around the channel and connected to the channel, and the second portion is disposed on the epitaxial layer One end of the second portion is connected to one end of the first portion.
  • the gate region is disposed on the second portion and one end of the gate region surrounds the first portion.
  • the source region is a second doping by the first doping type substrate A type ion is formed by doping, and the drain region is formed by ion doping of the first doping type by the channel.
  • the first doping type is a P type
  • the second doping type is an N type
  • the first doping type is N type
  • the second doping type is P type.
  • a method for fabricating a tunneling field effect transistor includes:
  • a drain region is formed at an end of the channel away from the first doping type substrate.
  • the method for fabricating the tunneling field effect transistor further includes:
  • the drain region and the gate region respectively forming a source, a drain and a gate, wherein the source, the drain and the gate are respectively connected to the source region, the drain region and the gate Zone connection.
  • the “corresponding to the source region, the drain region, and the gate region are respectively formed with a source, a drain, and a gate.
  • the source, the drain, and the gate are respectively connected to the source region, the drain region, and the gate region.
  • the method for preparing the field effect transistor further includes:
  • the “source, drain, and gate regions are respectively formed corresponding to the source region, the drain region, and the gate region.
  • the method for preparing the tunneling field effect transistor further comprises:
  • a second isolation layer having a second through hole and a third through hole, wherein the second through hole communicates with the first through hole, the third through a hole connecting the gate region;
  • the source is connected to the source region through the first through hole and the second through hole, and the gate is connected to the gate region through the third through hole.
  • the method for fabricating the tunneling field effect transistor further includes:
  • a first ohmic contact layer is formed such that the source is connected to the source region through the first ohmic contact layer.
  • the method for fabricating the tunneling field effect transistor further includes:
  • a second ohmic contact layer is formed such that the gate is connected to the gate region through the second ohmic contact layer.
  • the “providing the first doping type Between the step of the substrate and the step of forming a channel protruding from the middle of the first doping type substrate, the method for preparing the tunneling field effect transistor further includes:
  • the step of “forming a channel protruding in a middle portion of the first doping type substrate” includes:
  • the surface of the first doping type substrate covering the mask layer is etched to form a channel protruding in the middle of the first doping type substrate.
  • the “around the channel and The step of forming an epitaxial layer and a gate dielectric layer in sequence from a portion of the surface of the first doping type substrate includes:
  • the step of "around the channel and forming the gate region on the gate dielectric layer” includes:
  • the conductive layer comprising a first sub-conductive layer disposed on the dielectric layer and corresponding to the epitaxial layer stack, the first sub-conductive layer including away from the dielectric layer a reference layer of the electrical layer and the epitaxial layer;
  • the conductive layer, the dielectric layer, and the isolation layer above the reference surface are removed; the remaining conductive layer is the gate region, and the remaining dielectric layer is the gate dielectric layer.
  • the first doping type is performed at the end of the channel away from the substrate Before the step of doping to form a drain region, the method for preparing the tunneling field effect transistor further includes:
  • the mask layer is removed.
  • the gate region since the gate region is stacked on the gate dielectric layer and the epitaxial layer, when the gate region is loaded with an electrical signal, the gate region is loaded.
  • the direction of the electric field of the electrical signal is the vertical direction. It can be seen that the electric field direction of the electrical signal loaded in the gate region is consistent with the tunneling direction of the electron, that is, the line tunneling mechanism. Therefore, the tunneling efficiency of electrons in the valence band of the source region to the conduction band of the epitaxial layer is higher, and a higher on-state current and a steep subthreshold swing can be generated.
  • the drain region is located at an end of the channel and is far from the source region and the epitaxial layer, an electrical signal loaded on the drain region is formed on the source region and the epitaxial layer.
  • the effect of the tunneling junction is weaker, thereby improving the subthreshold swing of the tunneling field effect transistor.
  • the gate region, the gate dielectric layer and the epitaxial layer are sequentially stacked, thereby reducing the size of the first doping type substrate With area, the integration is improved.
  • the tunneling field effect transistor of the present invention adopts a channel perpendicular to a middle portion of the surface of the first doping type substrate, and a drain region is disposed at an end of the channel away from the first doping type substrate, further reducing The use area of the first doping type substrate is small, and the integration degree is improved.
  • the leakage current of the tunneling field effect transistor is further small.
  • FIG. 1 is a cross-sectional view of a tunneling field effect transistor in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a top plan view of a tunneling field effect transistor according to a preferred embodiment of the present invention.
  • FIG. 3 is a flow chart of preparing a tunneling field effect transistor according to a preferred embodiment of the present invention.
  • FIG. 4 is a substrate for providing a tunneling field effect transistor according to a preferred embodiment of the present invention.
  • FIG. 5 is a schematic structural view showing a mask layer disposed on a middle surface of a substrate in a preparation flow of a tunneling field effect transistor according to a preferred embodiment of the present invention
  • FIG. 6 is a schematic structural view showing a surface etching of a substrate provided with a mask layer in the middle of a surface in a process of preparing a tunneling field effect transistor according to a preferred embodiment of the present invention
  • FIG. 7 is a schematic structural view of a tunneling field effect transistor in a process of forming a source region according to a preferred embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing the structure of an epitaxial layer, an isolation layer, and a dielectric layer in a preparation process of a tunneling field effect transistor according to a preferred embodiment of the present invention.
  • FIG. 9 is a schematic structural view of a tunneling field effect transistor in a process of forming a conductive layer according to a preferred embodiment of the present invention.
  • FIG. 10 is a diagram of removing a reference in a preparation process of a tunneling field effect transistor according to a preferred embodiment of the present invention.
  • FIG. 11 is a schematic structural view of a tunneling field effect transistor in a process of preparing a second isolation layer according to a preferred embodiment of the present invention
  • FIG. 12 is a schematic structural view of a tunneling field effect transistor in a process of forming a drain region according to a preferred embodiment of the present invention
  • FIG. 13 is a schematic structural diagram of forming an electrode in a preparation process of a tunneling field effect transistor according to a preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a tunneling field effect transistor according to a preferred embodiment of the present invention.
  • 2 is a top plan view of a tunneling field effect transistor in accordance with a preferred embodiment of the present invention.
  • the tunneling field effect transistor 1 includes a first doping type substrate 10, a source region 20, an epitaxial layer 30, a gate dielectric layer 40, a gate region 50, a drain region 60, and a channel 70.
  • the first doping type substrate 10 supports the source region 20, the epitaxial layer 30, the gate dielectric layer 40, the gate region 50, the drain region 60, and the channel 70.
  • the source region 20, the epitaxial layer 30, the gate dielectric layer 40, the gate 50, the drain region 60, and the channel 70 are disposed directly or indirectly in the first doping.
  • the channel 70 is convexly disposed at a middle portion of the first doping type substrate 10.
  • the source region 20 is disposed on the first doping type substrate 10 and disposed around the channel 70.
  • the epitaxial layer 30 is stacked on the source region 20 and disposed around the channel 70.
  • the gate dielectric layer 40 is disposed on the epitaxial layer 30 and disposed around the channel.
  • the gate region 50 is disposed around the channel 70 and is disposed on the source region 20 through the epitaxial layer 30.
  • the drain region 60 is disposed at an end of the channel 70 away from the substrate 10.
  • the first doping type substrate 10 may be a silicon (Si) substrate.
  • the first doping type substrate 10 may also be a binary group of group II-IV, or group III-V, or group IV-IV of germanium (Ge) or silicon germanium, gallium arsenide, or the like.
  • germanium germanium
  • the material of the channel 70 is the same as the material of the first doping type substrate 10 .
  • the channel 70 may be formed by etching an edge of a thicker substrate to obtain a first doping type substrate 10 of the present invention and protrudingly disposed on the first doping type substrate The channel 70 in the middle of 10.
  • a hard mask may be disposed on a middle portion of a surface of a thicker substrate, and the surface of the substrate on which the mask layer is disposed may be etched.
  • the mask layer has a function of protecting the surface region of the substrate covered by the mask from being etched, when the surface of the substrate on which the mask layer is disposed is etched, the substrate is covered by the mask layer The surface and the portion below the surface are not etched away, and the surface of the substrate not covering the mask layer is gradually etched away due to no protection, thereby forming the first doping type substrate 10 and the protrusion
  • the channel 70 is disposed in the middle of the first doping type substrate 10.
  • a photoresist may be coated on a surface of a thicker substrate, the photoresist is patterned, and the desired etching is defined on the surface of the substrate. The area that is dropped and the area that does not need to be etched away.
  • the surface of the substrate is then etched to form a first doping type substrate 10 and the channel 70 protrudingly disposed in the middle of the surface of the first doping type substrate 10.
  • the first doping type substrate 10 may be, but not limited to, a rectangular parallelepiped having a certain thickness (as shown in FIG. 2).
  • the material of the mask layer may be, but not limited to, Si 3 N 4 .
  • the width of the channel 70 is on the order of nanometers.
  • the source region 20 may also be formed by disposing the surface of the channel 70 of the first doping type substrate 10 with a second doping type ion to form the source. District 20.
  • the source region 20 covers the first doping type substrate 10 and is disposed around the periphery of the channel 70.
  • the source region 20 and the channel 70 completely cover one surface of the first doping type substrate 10.
  • the height of the source region 20 in the direction perpendicular to the first doping type substrate 10 is smaller than the height of the channel 70 in the same direction.
  • the epitaxial layer 30 is disposed on the source region 20 and disposed around the channel 70.
  • the epitaxial layer 30 is stacked with the source region 20, and the epitaxial layer 30 covers a portion of the source region 20.
  • the epitaxial layer 30 is in close contact with the source region 20.
  • the contact surfaces between the epitaxial layer 30 and the source region 20 are all planar.
  • the contact surface between the epitaxial layer 30 and the source region 20 may also be non-planar, and the contact surface between the epitaxial layer 30 and the source region 20 is complementary in shape.
  • the epitaxial layer 30 is brought into close contact with the source region 20, thereby increasing the contact area between the epitaxial layer 30 and the source region 20. That is, the tunneling area when tunneling occurs between the epitaxial layer 30 and the source region 20 is increased to increase the tunneling current.
  • the epitaxial layer 30 is a semiconductor material of a different doping type from the source region 20 .
  • the material of the epitaxial layer 30 may be, but not limited to, Si, Ge, III-V compound, and the like.
  • the gate dielectric layer 40 includes a first portion 41 and a second portion 42 that is coupled to the first portion 41.
  • the first portion 41 is disposed on the epitaxial layer 30 and is directly connected to the channel 70. That is, the inner surface of the first portion 41 surrounds the outer surface of the channel 70 and the inner surface of the first portion 41 is in close contact with the outer surface of the channel 70.
  • the end surface of the first portion 41 away from the second portion 42 is lower than the end surface of the channel 70 away from the first doping type substrate 10.
  • the second portion 42 is disposed on the epitaxial layer 30, and one end of the second portion 42 is coupled to one end of the first portion 41.
  • the second portion 42 is substantially perpendicular to the first portion 41, and the first portion 41 and the second portion 42 form an "L" shape as viewed in cross section.
  • the gate region 50 is received in a space formed by the first portion 41 and the second portion 42. Specifically, the gate region 50 is stacked on the first portion 41, and the gate region is One end of 50 surrounds the second portion 42. In the present embodiment, the lower surface of the gate region 50 covers the surface of the first portion 41, the upper surface of the gate region 50 (the surface away from the first portion 41) and the second portion 42 is not flush with one end face of the first portion 41.
  • the drain region 60 is disposed at an end of the channel 70 away from the first doping type substrate 10.
  • the drain region 60 may also be formed by first doping type ion doping of the channel 70 away from the end of the first doping type substrate 10.
  • the tunneling field effect transistor 1 further includes an electrode 90.
  • the electrode 90 is connected to the source region 20, the drain region 60, and the gate region 50.
  • the electrodes connecting the source region 20, the drain region 60, and the gate region 50 are named source 91, drain 92, and gate 93, respectively.
  • the source 91, the drain 92, and the gate 93 are respectively configured to receive a voltage signal, and transmit the received voltage signal to the source region 20, the drain region 60, and the gate region 50, respectively.
  • the source 91, the drain 92, and the gate 93 also serve as three pins of the tunneling field effect transistor 1 to be electrically connected to respective pins of other devices.
  • the tunneling field effect transistor 1 further includes a first isolation layer 80, and the first isolation layer 80 is disposed A first through hole 81 is formed on the first isolation layer 80 on the source region 20.
  • the tunneling field effect transistor 1 further includes a second isolation layer 100 disposed on the first isolation layer 80 and the gate region 50.
  • the second isolation layer 100 is formed with a second through hole 101 corresponding to the first through hole 81 and a third through hole 102 corresponding to the gate region 50.
  • the first isolation layer 80 is disposed on a surface of the source region 20 that does not cover the epitaxial layer 30, and the second isolation layer 100 covers the first isolation layer 80 and covers the gate. Polar zone 50.
  • the first isolation layer 80 and the second isolation layer 100 may be an oxide protective layer such as silicon dioxide (SiO 2 ).
  • the second isolation layer 100 is used to isolate the contact between the gate region 50 and the outside, and functions to protect the gate region 50.
  • One end of the second through hole 101 is connected to one end of the first through hole 81, so that the second through hole 101 and the first through hole 81 form a communication hole, so that the source 91 is worn.
  • the second through hole 101 and the first through hole 81 are in contact with the source region 20 to load an electrical signal received by the source 91 to the source region 20.
  • the center line of the first through hole 81 coincides with the center line of the second through hole 101 to facilitate the filling of the first through hole 20 and the second through the source 91.
  • the hole 101 is in contact with the source region 20.
  • the source 91 has one end connected to the source region 20 and the other end protruding from the second isolation layer 100.
  • the drain 92 encloses the drain region 60 and is connected to the drain region 60 to load an electrical signal received by the drain 92 to the drain region 60.
  • the gate electrode 93 is connected to the gate region 50 through the third through hole 102 to load an electrical signal received by the gate electrode 93 to the gate region 50.
  • the gate 93 is connected to the gate region 50 at one end and protrudes from the second isolation layer 100 at the other end.
  • the structure of the source 91 and the gate 93 is such that the source 91 and the gate 93 are convenient to receive a voltage signal or are electrically connected to other devices.
  • the tunneling field effect transistor 1 also includes a first isolation layer and a second isolation layer, but the arrangement of the first isolation layer and the second isolation layer is slightly different from the previous embodiment.
  • the first isolation layer is disposed on the source region.
  • the first isolation layer is formed with a first through hole, and the source passes through the first through hole to connect the source region.
  • the first isolation layer is disposed on a surface of the source region that does not cover the epitaxial layer, and the source passes through the first through hole, and one end and the source region Connected, the other end protruding from the first isolation layer.
  • the second isolation layer only covers the gate region.
  • the first isolation layer and the second isolation layer may be an oxide protective layer such as SiO 2 .
  • the second isolation layer is used to isolate the contact between the gate region and the outside world, To protect the gate region.
  • the second isolation layer is formed with a second through hole such that the gate passes through the second through hole to connect the gate region.
  • the drain covers the drain region and is connected to the drain region to load an electrical signal received by the drain to the drain region.
  • One end of the gate is connected to the gate region, and the other end is protruded from the second isolation layer.
  • the structure of the source and the gate is such that the source and the gate are convenient to receive electrical signals or are electrically connected to other devices.
  • the tunneling field effect transistor 1 further includes a first ohmic contact layer (not shown) disposed between the source 91 and the source region 20, the source The pole 91 is connected to the source region 20 through the first ohmic contact layer to reduce contact resistance between the source 91 and the source region 20.
  • a first ohmic contact layer (not shown) disposed between the source 91 and the source region 20, the source The pole 91 is connected to the source region 20 through the first ohmic contact layer to reduce contact resistance between the source 91 and the source region 20.
  • the tunneling field effect transistor 1 further includes a second ohmic contact layer (not shown), the second ohmic contact layer being disposed between the gate electrode 93 and the gate region 50, A gate electrode 93 is connected to the gate region 50 through the second ohmic contact layer to reduce a contact resistance between the gate electrode 93 and the gate region 50.
  • the tunneling field effect transistor 1 further includes a third ohmic contact layer (not shown) disposed between the drain 92 and the drain region 60, the drain The pole 92 is connected to the drain region 60 through the third ohmic contact layer to reduce the contact resistance between the drain 92 and the drain region 60.
  • a third ohmic contact layer (not shown) disposed between the drain 92 and the drain region 60, the drain The pole 92 is connected to the drain region 60 through the third ohmic contact layer to reduce the contact resistance between the drain 92 and the drain region 60.
  • the first doping type is a P type and the second doping type is an N type. In another embodiment, the first doping type is an N type and the second doping type is a P type.
  • the P-type ions may include at least one of boron ions, or gallium ions, or indium ions; the N-type ions may include at least one of phosphorus ions, or arsenic ions.
  • the first doping type is P-type and the second doping type is N-type, that is, the source region 20 is doped with N-type ions, and the drain region 60 is doped with P-type ions.
  • the tunneling field effect transistor 1 is a P-type tunneling field effect transistor (PTFET).
  • the tunneling field effect transistor 1 is an N-type tunneling field effect transistor (NTFET).
  • NTFET N-type tunneling field effect transistor
  • the voltage signal loaded when the drain region 60 operates is a negative bias voltage
  • the voltage signal loaded when the source region 20 operates is a forward bias voltage
  • the voltage signal loaded when the source region 20 operates is a negative bias voltage signal.
  • the operation principle of the tunneling field effect transistor 1 will be described by taking the tunneling field effect transistor 1 as an NTFET as an example.
  • the tunneling field effect transistor 1 When the gate region 50 is not loaded with a voltage signal, the tunneling field effect transistor 1 is in a closed state.
  • the gate region 50 When the gate region 50 is loaded with an electrical signal, there is an energy band difference between the valence band of the source region 20 and the conduction band of the epitaxial layer 30 under the action of the electrical signal loaded by the gate region 50.
  • the electrons in the valence band of the source region 20 are tunneled into the conduction band of the epitaxial layer 30, thereby forming a tunneling current.
  • the source region 20 and the epitaxial layer 30 form a tunneling junction.
  • the tunneling direction of electrons in the valence band of the source region 20 to the conduction band of the epitaxial layer 30 is vertical. direction.
  • electrons that have tunneled are concentrated on the contact surface of the gate dielectric layer 40 and the epitaxial layer 30, under the action of the voltage signal loaded by the source region 20 and the voltage signal loaded by the drain region 60.
  • the electrons that have tunneled will flow to the drain region 60, thereby forming a drain current, that is, an operating current of the NTFET.
  • the direction of the electric field of the electrical signal loaded by the gate region 50 is Vertically. It can be seen that the electric field direction of the electrical signal loaded by the gate region 50 coincides with the tunneling direction of the electron, that is, the line tunneling mechanism. Therefore, the tunneling efficiency of electrons in the valence band of the source region 20 to the conduction band of the epitaxial layer 30 is high, and a high on-state current and a steep subthreshold swing can be generated (far Less than 60mV/dec).
  • the drain region 60 is located at the end of the channel 70 and is far from the source region 20 and the epitaxial layer 30, the electrical signal loaded on the drain region 60 is opposite to the source region 20 and The effect of the tunneling junction formed by the epitaxial layer 30 is weak, thereby improving the subthreshold swing of the tunneling field effect transistor 1.
  • the tunneling field effect transistor 1 since there is a certain distance between the drain region 60 and the gate region 50, when the gate region 50 is not loaded with a voltage signal, the tunneling field effect transistor 1 is in a closed state, and Since the gate region 50 surrounds the channel 70, the leakage current of the tunneling field effect transistor 1 is small.
  • FIG. 3 is a flow chart showing the preparation of a tunneling field effect transistor according to a preferred embodiment of the present invention. It can be understood that some of the steps included in this embodiment may also be omitted, and other steps may also be added as needed. Understandably, in other embodiments, The next multiple steps can be combined into one step, or one step can be split into multiple steps, and the order between the steps can be adjusted as needed.
  • the preparation process of the tunneling field effect transistor 1 includes the following steps.
  • a first doping type substrate 10 is provided, as shown in FIG.
  • the first doping type substrate 10 may be a Si substrate.
  • the first doping type substrate 10 may also be a binary group of group II-IV, or group III-V, or group IV-IV of germanium (Ge) or silicon germanium, gallium arsenide, or the like. Any one of a ternary compound semiconductor, silicon on an insulating substrate (SOI), or germanium on an insulating substrate.
  • Step S202 forming a channel 70 protruding from a middle portion of the first doping type substrate 10.
  • the material of the channel 70 is the same as the material of the first doping type substrate 10 .
  • the channel 70 may be formed by etching a thicker substrate edge to obtain the first doping type substrate of the present invention and protrudingly disposed on the first doping.
  • the channel 70 in the middle of the type of substrate Specifically, referring to FIG. 5, a mask layer b is disposed on a middle portion of a surface of a thicker substrate a. Referring to FIG. 6, the surface of the substrate a in which the mask layer b is disposed in the middle of the surface is etched to form the first doping type substrate 10 and the protrusion is disposed on the first doping.
  • the mask layer b Since the mask layer b has a function of protecting the surface region of the substrate a covered by it from being etched, when the surface of the substrate a on which the mask layer b is provided is etched, the substrate a is The surface covered by the mask layer and the area below the surface are not etched away, and the surface of the substrate not covering the mask layer b is gradually etched away due to no protection, thereby forming the first A doped type substrate 10 and the channel 70 protruding from a middle portion of the surface of the first doping type substrate 10.
  • the material of the mask layer b may be, but not limited to, Si 3 N 4 .
  • Step S203 forming a source region 20 around the first doping type substrate 10 and surrounding the channel 70.
  • the source region 20 may be formed by performing a second doping type ion doping on the surface of the first substrate 10 where the channel 70 is disposed to form the source region 20.
  • the source region 20 covers the first doping type substrate 10, disposed around the periphery of the channel 70, and an inner surface of the source region 20 is in contact with an outer surface of the channel 70.
  • the source region 20 and the channel 70 completely cover one surface of the first doping type substrate 10.
  • the source region 20 is perpendicular to the first
  • the height in the direction of the doping type substrate 10 is smaller than the height of the channel 70 in the same direction.
  • Step S204 the epitaxial layer 30 and the gate dielectric layer 40 are sequentially formed around the channel 70 and on a portion of the source region 20 remote from the first doping type substrate 10.
  • the epitaxial layer 30 is stacked with the source region 20, and the epitaxial layer 30 partially covers the source region 20. In the stacked portion of the epitaxial layer 30 and the source region 20, the epitaxial layer 30 is in close contact with the source region 20.
  • the contact surfaces between the epitaxial layer 30 and the source region 20 are all planar. In other embodiments, the contact surface between the epitaxial layer 30 and the source region 20 may also be non-planar, and the contact surface between the epitaxial layer 30 and the source region 20 is complementary in shape so that The epitaxial layer 30 is in intimate contact with the source region 20, thereby increasing the contact area between the epitaxial layer 30 and the source region 20.
  • the epitaxial layer 30 is a semiconductor material of a different doping type from the source region 20 .
  • the material of the epitaxial layer 30 may be, but not limited to, Si, Ge, III-V compound, and the like.
  • the gate dielectric layer 40 includes a first portion 41 and a second portion 42 that is coupled to the first portion 41.
  • the first portion 41 is disposed on the epitaxial layer 30 and is directly connected to the channel 70. That is, the inner surface of the first portion 41 surrounds the outer surface of the channel 70 and the inner surface of the first portion 41 is in close contact with the outer surface of the channel 70.
  • the end surface of the first portion 41 away from the second portion 42 is lower than the end surface of the channel 70 away from the first doping type substrate 10.
  • the second portion 42 is disposed on the epitaxial layer 30, and one end of the second portion 42 is coupled to one end of the first portion 41.
  • the second portion 42 is substantially perpendicular to the first portion 41, and the first portion 41 and the second portion 42 form an "L" shape as viewed in cross section.
  • Step S205 forming a gate region 50 around the channel 70 and on the gate dielectric layer 40.
  • the gate region 50 is received in a space formed by the first portion 41 and the second portion 42. Specifically, the gate region 50 is stacked on the second portion 42 and the gate is One end of the zone 50 surrounds the first portion 41.
  • the lower surface of the gate region 50 covers the surface of the second portion 42, the upper surface of the gate region 50 (the surface away from the second portion 42) and the first A portion 41 is not flush with one end face of the second portion 42.
  • the formation of the epitaxial layer 30, the gate dielectric layer 40, and the gate region 50 can be achieved by the following sub-steps. Understandably, the embodiment includes Some of the steps can also be omitted, and other steps can be added as needed. It can be understood that in other embodiments, the following multiple steps may be combined into one step, or one step may be split into multiple steps, and the order between the steps may be adjusted as needed.
  • an epitaxial layer 30 is formed around the channel 70 and a portion of the source region 20 remote from the first substrate 10.
  • the formation of the epitaxial layer 30 can be formed by epitaxy, such as Chemical Vapor Deposition (CVD) technology, Molecular beam epitaxy (MBE) technology.
  • the material of the epitaxial layer 30 may be, but not limited to, a semiconductor material such as Si, Ge, III-V or the like.
  • an isolation layer c is formed on the surface of the source region 20 not covering the epitaxial layer 30.
  • the isolation layer c covers the surface of the source region 20 that does not cover the epitaxial layer 30.
  • the epitaxial layer 30, the outer surface of the trench 70 not covered, and the outer surface of the mask layer a not covered are covered with a dielectric layer d.
  • the material of the dielectric layer d may be, but not limited to, Si 3 N 4 , SiO 2 , or a high K material.
  • Step (IV) the surface of the dielectric layer d is covered with a conductive layer e, and the conductive layer e includes a first sub-conductive layer disposed on the dielectric layer d and corresponding to the epitaxial layer 30 E1, the first sub-conducting layer e1 includes a reference surface e11 away from the dielectric layer d and the epitaxial layer 30.
  • the material of the conductive layer e may be, but not limited to, polysilicon, metal, or the like.
  • step (V) the conductive layer e, the dielectric layer d and the isolation layer c above the reference surface e11 are removed with reference to the reference surface e11.
  • the remaining dielectric layer d is the gate dielectric layer 40
  • the remaining conductive layer e is the gate region 50
  • the remaining isolation layer c is the first isolation layer. 80.
  • the reference plane e11 is first referenced by a planarization process, and the conductive layer e and the isolation layer c above the reference plane e11 are removed.
  • the dielectric layer d above the reference surface e11 is etched away by a etch back process to expose a portion of the channel 70 and the mask layer a.
  • a first through hole 81 corresponding to the source region 20 is opened on the first isolation layer 80.
  • a drain region 60 is formed at an end of the channel 70 away from the first doping type substrate 10.
  • the formation process of the drain region 60 may be: removing the mask layer a, and performing a portion of the channel 70 away from the end of the first doping type substrate 10.
  • the first doping type is doped to form the drain region 60.
  • the tunneling field effect crystal is crystal preferably, after the step S205, before the step S206, the tunneling field effect crystal.
  • the tube preparation process also includes:
  • a second isolation layer 100 having a second through hole 101 and a third through hole 102 formed in the gate region 50, the second isolation layer 100 covering the first isolation layer 80 and the gate region 50.
  • the second isolation layer 100 is used to isolate the contact between the gate region 50 and the outside, and functions to protect the gate region 50.
  • One end of the second through hole 101 is connected to one end of the first through hole 81, so that the second through hole 101 and the first through hole 81 form a communication hole.
  • the center line of the first through hole 81 coincides with the center line of the second through hole 101.
  • the third through hole 102 is disposed corresponding to the gate region 50.
  • Step S207 a source 91, a drain 92, and a gate 93 are formed corresponding to the source region 20, the drain region 60, and the gate region 50, respectively.
  • the source 91 is connected to the source region 20 through the first through hole 81 and the second through hole 101, and the gate 93 is connected to the gate region 50 through the third through hole 102.
  • the drain 92 is connected to the drain region 60.
  • the second isolation layer covers only the gate region.
  • the second isolation layer defines a second via hole corresponding to the gate region. The source is connected to the source region through the first through hole, and the gate is connected to the gate region through the second through hole.
  • the method for preparing the tunneling field effect transistor 1 further includes:
  • the first ohmic contact layer is disposed between the source 91 and the source region 20, and the source 91 passes through the first ohmic contact layer
  • the source region 20 is connected to reduce the contact resistance between the source 91 and the source region 20.
  • the method for preparing the tunneling field effect transistor 1 further includes:
  • the second ohmic contact layer is disposed between the gate electrode 93 and the gate region 50, and the gate electrode 93 passes through the second ohmic contact layer
  • the gate region 50 is connected to reduce the contact resistance between the gate electrode 93 and the gate region 50.
  • the method for preparing the tunneling field effect transistor 1 further includes:
  • the third ohmic contact layer is disposed between the drain 92 and the drain region 60, and the drain electrode 92 passes through the third ohmic contact layer
  • the drain region 60 is connected to reduce the contact resistance between the drain 92 and the drain region 60.
  • the tunneling field effect transistor 1 of the present invention since the gate region 50 is stacked on the gate dielectric layer 40 and the epitaxial layer 30, when the gate region 50 is charged Signal At the time, the direction of the electric field of the electrical signal loaded by the gate region 50 is a vertical direction. It can be seen that the electric field direction of the electrical signal loaded by the gate region 50 coincides with the tunneling direction of the electron, that is, the line tunneling mechanism. Therefore, the tunneling efficiency of electrons in the valence band of the source region 20 to the conduction band of the epitaxial layer 30 is high, and a high on-state current and a steep subthreshold swing can be generated (far Less than 60mV/dec).
  • the drain region 60 is located at the end of the channel 70 and is far from the source region 20 and the epitaxial layer 30, the electrical signal loaded on the drain region 60 is opposite to the source region 20 and The effect of the tunneling junction formed by the epitaxial layer 30 is weak, thereby improving the subthreshold swing of the tunneling field effect transistor 1.
  • the gate region 50, the gate dielectric layer 40 and the epitaxial layer 30 are sequentially stacked, thereby reducing the use area of the first doping type substrate 10 and improving the integration degree.
  • the tunneling field effect transistor 1 of the present invention employs a channel 70 perpendicular to the middle of the surface of the first doping type substrate 10, and is disposed at an end of the channel 70 away from the first doping type substrate 10.
  • the drain region 60 further reduces the use area of the first doping type substrate 10, improving the degree of integration.
  • the tunneling field effect transistor 1 of the present invention since there is no overlapping region between the drain region 60 and the gate region 50 of the tunneling field effect transistor 1 of the present invention and the gate region 50 surrounds the channel 70, the tunneling field effect The leakage current of the transistor 1 is smaller.

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Abstract

一种隧穿场效应晶体管其包括：第一掺杂类型衬底（10）；沟道（70），凸出设置于第一掺杂类型衬底中部；源区（20），设置于第一掺杂类型衬底上，且围绕沟道设置；外延层（30），设置于源区上，围绕沟道设置；栅介质层（40），设置于外延层上，且围绕沟道设置；栅极区（50），围绕设置于栅介质层上；以及漏区（60），设置在沟道远离衬底的端部。隧穿场效应晶体管具有较高的驱动电流，陡直的亚阈值摆幅，较小的泄漏电流以及较高的芯片集成密度。

Description

隧穿场效应晶体管及隧穿场效应晶体管的制备方法
本发明要求2014年7月15日递交的发明名称为“隧穿场效应晶体管及隧穿场效应晶体管的制备方法”的申请号201410336815.7的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种隧穿场效应晶体管及隧穿场效应晶体管的制备方法。
背景技术
互补金属氧化物半导体器件(Complementary Metal Oxide Semiconductor,CMOS)是微电子集成电路的核心组成器件，其尺寸和工作电压遵循摩尔(Moore)定律，以获得更优异的性能和更高的集成密度。然而，随着COMS的尺寸的减小，其功耗也在持续增加。部分原因是短沟道效应引起的泄露电流的增加，同时也归咎于器件的供电电压越来越难以缩减。其中，CMOS器件的供电电压难以缩减主要是由于CMOS器件的亚阈值摆幅较大，一般高于60mv/dec。而隧穿场效应晶体管(Tunnel Field Effect Transistor,TFET)被认为是替代CMOS器件的较好的器件。然而，目前TFET的工作时的载流子的隧穿方向与栅电场不在同一个方向上，即点隧穿机制。因此，现有技术中，采用点隧穿机制导致载流子隧穿效率较低，使得TFET存在隧穿电流小的缺点，并且亚阈值摆幅较难达到60mV/dec。
发明内容
提供一种隧穿场效应晶体管，采用线隧穿机制提高了隧穿场效应晶体管的载流子隧穿效率，具有较高的驱动电流和较陡直的亚阈值摆幅，并且器件采用立体结构，提高了芯片的集成密度。
一方面，提供了一种隧穿场效应晶体管，所述隧穿场效应晶体管包括：
第一掺杂类型衬底；
沟道，凸出设置于所述第一掺杂类型衬底中部；
源区，设置于所述第一掺杂类型衬底上，且围绕所述沟道设置；
外延层，设置于所述源区上，围绕所述沟道设置；
栅介质层，设置于所述外延层上，且围绕所述沟道设置；
栅极区，围绕所述沟道设置，且通过所述外延层设置于所述源区上；以及
漏区，设置在所述沟道远离所述衬底的端部。
在第一种可能的实现方式中，所述隧穿场效应晶体管还包括：
电极，所述电极对应连接所述源区、漏区及栅极区，以形成所述源极、漏极及栅极。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述隧穿场效应晶体管还包括：
第一隔离层，设置于所述源区上，所述第一隔离层形成有第一贯孔，所述源极穿过所述第一贯孔以连接所述源区；
第二隔离层，设置于所述栅极区上，所述第二隔离层形成有第二贯孔，所述栅极穿过所述第二贯孔以连接所述栅极区。
结合第一种可能的实现方式，在第三种可能的实现方式中，所述隧穿场效应晶体管还包括：
第一隔离层，设置于所述源区上，所述第一隔离层形成有第一贯孔；
第二隔离层，设置于所述第一隔离层及所述栅极区上，所述第二隔离层形成有对应所述第一贯孔的第二贯孔以及对应所述栅极区的第三贯孔；
所述源极穿过所述第一贯孔及所述第二贯孔连接所述源区，所述栅极穿过所述第三贯孔连接所述栅极区。
结合第一至第三种可能的实现方式中的任意一项可能的实现方式，在第四种可能的实现方式中，所述隧穿场效应晶体管还包括：
第一欧姆接触层，所述源极通过所述第一欧姆接触层与所述源区连接。
结合第一至第四种可能的实现方式中的任意一项可能的实现方式，在第五种可能的实现方式中，所述隧穿场效应晶体管还包括：
第二欧姆接触层，所述栅极通过所述第二欧姆接触层与所述栅极区连接。
结合第一方面，及第一方面的第一种至第五种可能的实现方式的任意一种可能的实现方式，在第六种可能的实现方式中，所述栅介质层包括第一部分及与所述第一部分连接的第二部分，所述第一部分设置于所述外延层上且环绕所述沟道设置且与所述沟道连接，所述第二部分设置于所述外延层上且所述第二部分的一端连接所述第一部分的一端。
结合第六种可能的实现方式，在第七种可能的实现方式中，所述栅极区设置于所述第二部分上且所述栅极区一端环绕所述第一部分。
结合第一方面及第一方面的第一至第七种可能的实现方式，在第八种可能的实现方式中，所述源区为由所述第一掺杂类型衬底进行第二掺杂类型离子掺杂而形成，所述漏区由所述沟道进行第一掺杂类型离子掺杂而形成。
结合第八种可能的实现方式，在第九种可能的实现方式中，所述第一掺杂类型为P型，所述第二掺杂类型为N型；或者所述第一掺杂类型为N型，所述第二掺杂类型为P型。
第二方面，提供了一种隧穿场效应晶体管的制备方法，所述隧穿场效应晶体管的制备方法包括：
提供第一掺杂类型衬底；
形成凸出设置于所述第一掺杂类型衬底中部的沟道；
在所述第一掺杂类型衬底上，且围绕所述沟道形成源区；
围绕所述沟道且在源区远离所述第一掺杂类型衬底的部分表面依次形成外延层及栅介质层；
围绕所述沟道且在所述栅介质层上形成栅极区；以及
在所述沟道远离所述第一掺杂类型衬底的端部形成漏区。
在第二方面的第一种可能的实现方式中，所述隧穿场效应晶体管的制备方法还包括：
对应所述源区、漏区及栅极区分别形成与源极、漏极及栅极，所述源极、所述漏极及所述栅极分别与所述源区、漏区及栅极区连接。
结合第二方面的第一种可能的实现方式，在第二种可能的实现方式中，所述“对应所述源区、漏区及栅极区分别形成与源极、漏极及栅极，所述源极、所述漏极及所述栅极分别与所述源区、漏区及栅极区连接”步骤之前，所述隧 穿场效应晶体管的制备方法还包括：
在源区未形成所述外延层及栅介质层的表面形成开设有第一贯孔的第一隔离层；
在所述栅极区上形成开设有第二贯孔的第二隔离层；所述源极穿过所述第一贯孔与所述源区连接，所述栅极穿过所述第二贯孔与所述栅极区连接。
结合第二方面的第一种可能的实现方式，在第三种可能的实现方式中，在所述“对应所述源区、漏区及栅极区分别形成与源极、漏极及栅极，所述源极、所述漏极及所述栅极分别与所述源区、漏区及栅极区连接”步骤之前，所述隧穿场效应晶体管的制备方法还包括：
在源区未形成所述外延层及所述栅介质层的表面形成开设有第一贯孔的第一隔离层；
在所述第一隔离层及所述栅极区形成开设有第二贯孔及第三贯孔的第二隔离层，所述第二贯孔连通所述第一贯孔，所述第三贯孔连接所述栅极区；
所述源极穿过所述第一贯孔及所述第二贯孔连接所述源区，所述栅极穿过所述第三贯孔连接所述栅极区。
结合第二方面的第一种至第三种可能的实现方式的任意一种可能的实现方式，在第四种可能的实现方式中，所述隧穿场效应晶体管的制备方法还包括：
形成第一欧姆接触层，以使所述源极通过所述第一欧姆接触层与所述源区连接。
结合第二方面的第一种至第四种可能的实现方式的任意一种可能的实现方式，在第五种可能的实现方式中，所述隧穿场效应晶体管的制备方法还包括：
形成第二欧姆接触层，以使所述栅极通过所述第二欧姆接触层与所述栅极区连接。
结合第二方面，及第二方面的第一种至第五种可能的实现方式的任意一种可能的实现方式，在第六种可能的实现方式中，在所述“提供第一掺杂类型衬底”步骤及所述“形成凸设于所述第一掺杂类型衬底中部的沟道”步骤之间，所述隧穿场效应晶体管的制备方法还包括：
在所述第一掺杂类型衬底表面的中部形成掩膜层，所述掩膜层用于保护所述被其覆盖的第一掺杂类型衬底的表面；
所述“形成凸出设置于所述第一掺杂类型衬底中部的沟道”步骤包括：
对表面的中部覆盖掩膜层的第一掺杂类型衬底的表面进行蚀刻，以形成凸出设置于所述第一掺杂类型衬底中部的沟道。
结合第二方面，及第二方面的第一种至第六种可能的实现方式的任意一种可能的实现方式，在第七种可能的实现方式中，所述“围绕所述沟道且在源区远离所述第一掺杂类型衬底的部分表面依次形成外延层及栅介质层”步骤包括：
围绕所述沟道且在源区远离所述第一掺杂类型衬底的部分表面形成所述外延层；
形成覆盖所述外延层，所述沟道表面及所述掩膜层表面的介电层；
所述“围绕所述沟道且在所述栅介质层上形成所述栅极区”步骤包括：
覆盖所述介电层形成导电层，所述导电层包括设置在所述介电层上且与所述外延层层叠对应的第一子导电层，所述第一子导电层包括远离所述介电层及所述外延层的参考面；
移除所述参考面以上的导电层，介电层，以及隔离层；剩余的导电层即为栅极区，剩余的介电层即为栅介电层。
结合第二方面的第六种或第七种可能的实现方式，在第八种可能的实现方式中，在所述“对所述沟道远离所述衬底的端部进行第一掺杂类型掺杂以形成漏区”步骤之前，所述隧穿场效应晶体管的制备方法还包括：
移除所述掩膜层。
根据各实现方式提供的隧穿场效应晶体管，由于所述栅极区层叠设置在所述栅介质层及所述外延层上，当所述栅极区加载电信号时，所述栅极区加载的电信号的电场的方向为竖直方向。由此可见，所述栅极区加载的电信号的电场方向与所述电子的隧穿方向一致，即为线隧穿机制。因此，所述源区的价带中的电子隧穿至所述外延层的导带时的隧穿效率较高，可以产生较高的开态电流和陡直的亚阈值摆幅。同时，由于漏区位于所述沟道的端部，距离所述源区及所述外延层较远，因此，所述漏区上加载的电信号对所述源区及所述外延层形成的隧穿结的影响较弱，从而改善了所述隧穿场效应晶体管的亚阈值摆幅。且所述栅极区、栅介质层及外延层依次层叠，从而减小了第一掺杂类型衬底的使 用面积，提高了集成度。
进一步地，本发明隧穿场效应晶体管采用垂直于所述第一掺杂类型衬底表面中部的沟道，在沟道远离所述第一掺杂类型衬底的端部设置漏区，进一步减小了第一掺杂类型衬底的使用面积，提高了集成度。
再进一步地，由于本发明隧穿场效应晶体管的漏区和栅极区之间不存在重叠区域且所述栅极区环绕所述沟道，因此，所述隧穿场效应晶体管的泄露电流更小。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的隧穿场效应晶体管的剖视图；
图2为本发明一较佳实施方式的隧穿场效应晶体管的俯视图；
图3为本发明一较佳实施方式的隧穿场效应晶体管的制备流程图；
图4为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中提供一衬底；
图5为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中将衬底表面中部设置掩膜层后的结构示意图；
图6为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中对表面中部设置掩膜层的衬底进行表面蚀刻后的结构示意图；
图7为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中形成源区后的结构示意图；
图8为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中形成外延层、隔离层、介电层的后结构示意图。
图9为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中形成导电层后的结构示意图；
图10为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中移除参 考面以上的导电层，介电层及隔离层后的结构示意图；
图11为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中设置第二隔离层后的结构示意图；
图12为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中形成漏区后的结构示意图；
图13为本发明一较佳实施方式的隧穿场效应晶体管的制备流程中形成电极后的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1和图2，图1为本发明一较佳实施方式的隧穿场效应晶体管的剖视图。图2为本发明一较佳实施方式的隧穿场效应晶体管的俯视图。所述隧穿场效应晶体管1包括第一掺杂类型衬底10、源区20、外延层30、栅介质层40、栅极区50、漏区60及沟道70。所述第一掺杂类型衬底10支撑所述源区20、所述外延层30、所述栅介质层40、所述栅极区50、所述漏区60及所述沟道70。换句话说，所述源区20、所述外延层30、所述栅介质层40、所述栅极50、所述漏区60及所述沟道70直接或间接设置在所述第一掺杂类型衬底10上。所述沟道70凸出设置于所述第一掺杂类型衬底10的中部。所述源区20设置于所述第一掺杂类型衬底10上，且围绕所述沟道70设置。所述外延层30层叠设置于所述源区20上，且围绕所述沟道70设置。所述栅介质层40设置于所述外延层30上，且围绕所述沟道设置。所述栅极区50围绕所述沟道70设置，且通过所述外延层30设置于所述源区20上。所述漏区60设置于所述沟道70远离所述衬底10的端部。
在本实施方式中，所述第一掺杂类型衬底10可以为硅(Si)衬底。在其他实施方式中，所述第一掺杂类型衬底10也可以为锗(Ge)或硅锗、镓砷等II-IV族、或III-V族、或IV-IV族的二元或三元化合物半导体、绝缘衬底上的 硅(Silicon on Insulator,SOI)、或者绝缘衬底上的锗中的任意一种。
在一实施方式中，所述沟道70的材质与所述第一掺杂类型衬底10的材质相同。所述沟道70可由以下方式形成：可对一厚度较厚的衬底的边缘进行蚀刻而得到本发明的第一掺杂类型衬底10及凸出设置于所述第一掺杂类型衬底10中部的所述沟道70。具体地，可对一厚度较厚的衬底的一表面的中部设置一掩膜层(hard mask)，再对设置掩膜层的所述衬底的表面进行蚀刻。由于掩膜层具有保护其所覆盖的衬底的表面区域不被蚀刻的作用，因此，对所述设置掩膜层的衬底的表面进行蚀刻时，所述衬底被所述掩膜层覆盖的表面及所述表面以下的部分不会被蚀刻掉，而未覆盖掩膜层的衬底的表面则由于没有保护而被逐渐蚀刻掉，从而形成了第一掺杂类型衬底10及凸出设置于所述第一掺杂类型衬底10中部的所述沟道70。可以理解地，在其他实施方式中，可对一厚度较厚的衬底的一表面涂布光刻胶，对所述光刻胶图案化，在所述衬底的表面定义出所述需要蚀刻掉的区域及不需要蚀刻掉的区域。再对所述衬底的表面进行蚀刻，以形成第一掺杂类型衬底10及凸出设置于所述第一掺杂类型衬底10表面中部的所述沟道70。所述第一掺杂类型衬底10可为但不仅限于具有一定厚度的长方体(如图2所示)。所述掩膜层的材料可以为但不局限于Si3N4。在一实施方式中，所述沟道70的宽度的数量级为纳米级别。
在一实施方式中，所述源区20也可由以下方式形成：对所述第一掺杂类型衬底10设置所述沟道70的表面进行第二掺杂类型离子掺杂而形成所述源区20。所述源区20覆盖所述第一掺杂类型衬底10，围绕所述沟道70的周围设置。所述源区20及所述沟道70完全覆盖所述第一掺杂类型衬底10的一个表面。所述源区20在垂直所述第一掺杂类型衬底10方向上的高度小于所述沟道70在同方向上的高度。
所述外延层30设置在所述源区20上，围绕所述沟道70设置。在本实施方式中，所述外延层30与所述源区20层叠设置，且所述外延层30覆盖部分所述源区20。在所述外延层30与所述源区20的层叠部分，所述外延层30与所述源区20紧密接触。在本实施方式中，所述外延层30及所述源区20之间的接触面均为平面。在其他实施方式中，所述外延层30及所述源区20之间的接触面也可为非平面，所述外延层30与所述源区20之间的接触面形状互补， 以使得所述外延层30与所述源区20紧密接触，从而增大了所述外延层30与所述源区20之间的接触面积。即增大了所述外延层30与所述源区20之间发生隧穿时的隧穿面积，以提高隧穿电流。所述外延层30为与所述源区20不同掺杂类型的半导体材料，比如，所述外延层30的材料可以为但不仅限于Si、Ge、III-V族化合物等。
所述栅介质层40包括第一部分41及与所述第一部分41连接的第二部分42。所述第一部分41设置在所述外延层30上，且与所述沟道70直接连接。即，所述第一部分41的内表面环绕所述沟道70的外表面且所述第一部分41的内表面与所述沟道70的外表面紧密接触。在本实施方式中，所述第一部分41的远离所述第二部分42的端面低于所述沟道70远离所述第一掺杂类型衬底10的端面。所述第二部分42设置在所述外延层30上，且所述第二部分42的一端连接所述第一部分41的一端。所述第二部分42大致垂直所述第一部分41，从剖面图上来看，所述第一部分41及所述第二部分42形成“L”形。
所述栅极区50收容于所述第一部分41及所述第二部分42形成的空间内，具体地，所述栅极区50层叠设置在所述第一部分41上，且所述栅极区50的一端环绕所述第二部分42。在本实施方式中，所述栅极区50的下表面覆盖在所述第一部分41的表面，所述栅极区50的上表面(远离所述第一部分41的表面)与所述第二部分42未与所述第一部分41连接的一个端面平齐。
所述漏区60设置在所述沟道70远离所述第一掺杂类型衬底10的端部。在一实施方式中，所述漏区60也可由所述沟道70远离所述第一掺杂类型衬底10的端部进行第一掺杂类型离子掺杂而形成。
所述隧穿场效应晶体管1还包括电极90。所述电极90对应连接所述源区20、漏区60及栅极区50。为了方便描述，连接所述源区20、所述漏区60及所述栅极区50的电极分别命名为源极91、漏极92及栅极93。所述源极91、漏极92及栅极93分别用于接收电压信号，并将接收到的电压信号分别传递至所述源区20、所述漏区60及所述栅极区50。所述源极91、漏极92及栅极93也作为所述隧穿场效应晶体管1的三个引脚，以与其他器件的相应引脚电连接。
所述隧穿场效应晶体管1还包括第一隔离层80，所述第一隔离层80设置 于所述源区20上，所述第一隔离层80上形成有第一贯孔81。所述隧穿场效应晶体管1还包括第二隔离层100，所述第二隔离层100设置于所述第一隔离层80及所述栅极区50上。所述第二隔离层100形成有对应所述第一贯孔81的第二贯孔101及对应所述栅极区50的第三贯孔102。在本实施方式中，所述第一隔离层80设置在所述源区20未覆盖所述外延层30的表面，所述第二隔离层100覆盖所述第一隔离层80且覆盖所述栅极区50。所述第一隔离层80及所述第二隔离层100可以为氧化物保护层，比如二氧化硅(SiO2)。所述第二隔离层100用于隔离所述栅极区50与外界之间的接触，起到保护所述栅极区50的作用。所述第二贯孔101的一端连接所述第一贯孔81的一端，使得所述第二贯孔101与所述第一贯孔81形成一个联通的孔，以使所述源极91穿过所述第二贯孔101及所述第一贯孔81与所述源区20接触，以将所述源极91接收到的电信号加载至所述源区20。在本实施方式中，所述第一贯孔81的中心线与所述第二贯孔101的中心线重合，以方便所述源极91填充所述第一贯孔20及所述第二贯孔101与所述源区20接触。在本实施方式中，所述源极91一端与所述源区20连接，另一端凸出于所述第二隔离层100。所述漏极92包覆所述漏区60且与所述漏区60连接，以将所述漏极92接收的电信号加载至所述漏区60。所述栅极93穿过所述第三贯孔102与所述栅极区50连接，以将所述栅极93接收的电信号加载至所述栅极区50。所述栅极93一端与所述栅极区50连接，另一端凸出于所述第二隔离层100。所述源极91及所述栅极93的这种结构以使得所述源极91及所述栅极93方便接收电压信号，或与其他器件电连接。
在其他实施方式中，所述隧穿场效应晶体管1中也包括第一隔离层及第二隔离层，但是所述第一隔离层及第二隔离层的设置与前述实施方式稍微不同。具体地，所述第一隔离层设置于所述源区上。所述第一隔离层形成有第一贯孔，所述源极通过所述第一贯孔以连接所述源区。具体地，在本实施方式中，所述第一隔离层设置在所述源区未覆盖所述外延层的表面，且所述源极穿过所述第一贯孔，一端与所述源区连接，另一端凸出于所述第一隔离层。所述第二隔离层仅仅覆盖所述栅极区。所述第一隔离层及所述第二隔离层可为氧化物保护层，比如SiO2。所述第二隔离层用于隔离所述栅极区与外界之间的接触，起 到保护所述栅极区的作用。所述第二隔离层形成有第二贯孔，以使得所述栅极穿过所述第二贯孔以连接所述栅极区。所述漏极包覆所述漏区且与所述漏区连接，以将所述漏极接收的电信号加载至所述漏区。所述栅极一端与所述栅极区连接，另一端凸出于所述第二隔离层。所述源极及所述栅极的这种结构以使得所述源极及所述栅极方便接收电信号，或与其他器件电连接。
优选地，所述隧穿场效应晶体管1还包括第一欧姆接触层(图未示)，所述第一欧姆接触层设置在所述源极91与所述源区20之间，所述源极91通过所述第一欧姆接触层与所述源区20连接，以减小所述源极91与所述源区20之间的接触电阻。
优选地，所述隧穿场效应晶体管1还包括第二欧姆接触层(图未示)，所述第二欧姆接触层设置在所述栅极93与所述栅极区50之间，所述栅极93通过所述第二欧姆接触层与所述栅极区50连接，以减小所述栅极93与所述栅极区50之间的接触电阻。
优选地，所述隧穿场效应晶体管1还包括第三欧姆接触层(图未示)，所述第三欧姆接触层设置在所述漏极92与所述漏区60之间，所述漏极92通过所述第三欧姆接触层与所述漏区60连接，以减小所述漏极92与所述漏区60之间的接触电阻。
在一实施方式中，所述第一掺杂类型为P型，所述第二掺杂类型为N型。在另一实施方式中，所述第一掺杂类型为N型，第二掺杂类型为P型。这里，所述P型离子可以包括硼离子、或镓离子、或铟离子中的至少一种；所述N型离子可以包括磷离子、或砷离子中的至少一种。当所述第一掺杂类型为P型，第二掺杂类型为N型时，即，所述源区20掺杂了N型离子，漏区60掺杂了P型离子，此时，所述隧穿场效应晶体管1为P型隧穿场效应晶体管(PTFET)。当所述第一掺杂类型为N型，第二掺杂类型为P型时，即所述源区20掺杂了P型离子，漏区60掺杂了N型离子，此时，所述隧穿场效应晶体管1为N型隧穿场效应晶体管(NTFET)。对PTFET而言，所述漏区60工作时加载的电压信号为负向偏置电压，所述源区20工作时加载的电压信号为正向偏置电压。对NTFET而言，所述漏区60工作时加载的电压信号为正向偏置电压，所述源区20工作时加载的电压信号为负向偏置电压信号。
在此，以所述隧穿场效应晶体管1为NTFET为例对所述隧穿场效应晶体管1的工作原理进行说明。
当所述栅极区50没有加载电压信号时，所述隧穿场效应晶体管1处于关闭状态。当所述栅极区50加载电信号时，在栅极区50加载的电信号的作用下，所述源区20的价带和所述外延层30的导带之间存在能带差，这样，所述源区20的价带中的电子便会隧穿至所述外延层30的导带中，从而形成了隧穿电流。所述源区20与所述外延层30形成了隧穿结。本发明中，由于所述源区20与所述外延层30层叠设置，因此，所述源区20的价带中的电子隧穿至所外延层30的导带中的隧穿方向为竖直方向。此时，发生隧穿的电子集中在所述栅介质层40与所述外延层30的接触面上，在所述源区20加载的电压信号及所述漏区60加载的电压信号的作用下，这些发生隧穿的电子便会流向所述漏区60，从而形成了漏极电流，即所述NTFET的工作电流。
需要说明的是，由于在本发明中，由于所述栅极区50层叠设置在所述栅介质层40及所述外延层30上，所述栅极区50加载的电信号的电场的方向为竖直方向。由此可见，所述栅极区50加载的电信号的电场方向与所述电子的隧穿方向一致，即为线隧穿机制。因此，所述源区20的价带中的电子隧穿至所述外延层30的导带时的隧穿效率较高，可以产生较高的开态电流和陡直的亚阈值摆幅(远小于60mV/dec)。同时，由于漏区60位于所述沟道70的端部，距离所述源区20及所述外延层30较远，因此，所述漏区60上加载的电信号对所述源区20及所述外延层30形成的隧穿结的影响较弱，从而改善了所述隧穿场效应晶体管1的亚阈值摆幅。
此外，由于所述漏区60与所述栅极区50之间存在一定的距离，当所述栅极区50没有加载电压信号时，所述隧穿场效应晶体管1处于关闭状态时，并且，由于所述栅极区50环绕所述沟道70，所述隧穿场效应晶体管1的泄露电流较小。
下面结合图1及图2对本发明一实施方式中隧穿场效应晶体管的制备流程进行介绍。请一并参阅图3及图4至图13。图3本发明一较佳实施方式的隧穿场效应晶体管的制备流程图。可以理解地，本实施例中包含的部分步骤也可以省略，其他步骤也可以根据需要增加。可以理解地，在其他实施方式中，以 下多个步骤可合并成一个步骤，或者一个步骤可拆分成多个步骤，步骤之间的顺序可以根据需要进行调整。所述隧穿场效应晶体管1的制备流程包括以下步骤。
步骤S201，提供第一掺杂类型衬底10，如图4所示。在本实施方式中，所述第一掺杂类型衬底10可以为Si衬底。在其他实施方式中，所述第一掺杂类型衬底10也可以为锗(Ge)或硅锗、镓砷等II-IV族、或III-V族、或IV-IV族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator,SOI)、或者绝缘衬底上的锗中的任意一种。
步骤S202，形成凸设于所述第一掺杂类型衬底10中部的沟道70。在一实施方式中，所述沟道70的材质与所述第一掺杂类型衬底10的材质相同。
在本步骤中，所述沟道70可以由以下方式形成：对一厚度较厚的衬底边缘进行蚀刻而得到本发明的第一掺杂类型衬底及凸出设置于所述第一掺杂类型衬底中部的所述沟道70。具体地，请参阅图5，对一厚度较厚的衬底a的一表面的中部设置一掩膜层b。请一并参阅图6，对表面的中部设置掩膜层b的所述衬底a的表面进行蚀刻，从而形成所述第一掺杂类型衬底10及凸出设置于所述第一掺杂类型衬底10中部的所述沟道70。由于所述掩膜层b具有保护其覆盖的衬底a的表面区域不被蚀刻的作用，因此，对所述设置掩膜层b的衬底a的表面进行蚀刻时，所述衬底a被所述掩膜层覆盖的表面及所述表面以下的区域不被蚀刻掉，而未覆盖所述掩膜层b的衬底的表面则由于没有保护而被逐渐蚀刻掉，从而形成了所述第一掺杂类型衬底10及凸出设置于所述第一掺杂类型衬底10表面中部的所述沟道70。所述掩膜层b的材料可以为但不局限于Si3N4。
步骤S203，在所述第一掺杂类型衬底上10，且围绕所述沟道70形成源区20。
请一并参阅图7，所述源区20可由以下方式形成：对所述第一衬底10设置所述沟道70的表面进行第二掺杂类型离子掺杂而形成所述源区20。所述源区20覆盖所述第一掺杂类型衬底10，围绕所述沟道70的周围设置，且所述源区20的内表面与所述沟道70的外表面接触。所述源区20及所述沟道70完全覆盖所述第一掺杂类型衬底10的一个表面。所述源区20在垂直所述第一 掺杂类型衬底10方向上的高度小于所述沟道70在同方向上的高度。
步骤S204，围绕所述沟道70且在所述源区20远离所述第一掺杂类型衬底10的部分表面依次形成所述外延层30及栅介质层40。
在本实施方式中，所述外延层30与所述源区20层叠设置，且所述外延层30部分覆盖所述源区20。在所述外延层30与所述源区20的层叠部分，所述外延层30与所述源区20紧密接触。在本实施方式中，所述外延层30及所述源区20之间的接触面均为平面。在其他实施方式中，所述外延层30及所述源区20之间的接触面也可为非平面，所述外延层30与所述源区20之间的接触面形状互补，以使得所述外延层30与所述源区20紧密接触，从而增大了所述外延层30与所述源区20之间的接触面积。即增大了所述外延层30与所述源区20之间发生隧穿时的隧穿面积，以提高隧穿电流。所述外延层30为与所述源区20不同掺杂类型的半导体材料，比如，所述外延层30的材料可以为但不仅限于Si、Ge、III-V族化合物等。
所述栅介质层40包括第一部分41及与所述第一部分41连接的第二部分42。所述第一部分41设置在所述外延层30上，且与所述沟道70直接连接。即，所述第一部分41的内表面环绕所述沟道70的外表面且所述第一部分41的内表面与所述沟道70的外表面紧密接触。在本实施方式中，所述第一部分41的远离所述第二部分42的端面低于所述沟道70远离所述第一掺杂类型衬底10的端面。所述第二部分42设置在所述外延层30上，且所述第二部分42的一端连接所述第一部分41的一端。所述第二部分42大致垂直所述第一部分41，从剖面图上来看，所述第一部分41及所述第二部分42形成“L”形。
步骤S205，围绕所述沟道70且在所述栅介质层40上形成栅极区50。
所述栅极区50收容于所述第一部分41及所述第二部分42形成的空间内，具体地，所述栅极区50层叠设置在所述第二部分42上，且所述栅极区50的一端环绕所述第一部分41。在本实施方式中，所述栅极区50的下表面覆盖在所述第二部分42的表面，所述栅极区50的上表面(远离所述第二部分42的表面)与所述第一部分41未与所述第二部分42连接的一个端面平齐。
具体地，请一并参阅图8至图10，在所述外延层30、所述栅介质层40及所述栅极区50的形成可通过以下子步骤实现。可以理解地，本实施例中包含 的部分步骤也可以省略，其他步骤也可以根据需要增加。可以理解地，在其他实施方式中，以下多个步骤可合并成一个步骤，或者一个步骤可拆分成多个步骤，步骤之间的顺序可以根据需要进行调整。
步骤(I)，围绕所述沟道70且在源区20远离所述第一衬底10的部分表面形成外延层30。具体地，所述外延层30的形成可用外延的方式形成，比如化学气相沉积(Chemical Vapor Deposition，CVD)技术，分子束外延(Molecular beam epitaxy，MBE)技术。所述外延层30的材料可以为但不仅限于Si，Ge，III-V族等半导体材料。
步骤(II)，在源区20未覆盖所述外延层30的表面形成一隔离层c。所述隔离层c覆盖所述源区20未覆盖所述外延层30的表面。
步骤(III)，在所述外延层30、所述沟道70未被覆盖的外表面及所述掩膜层a未被覆盖的外表面覆盖一层介电层d。所述介电层d的材料可以为但不仅限于Si3N4，SiO2，或高K材料。
步骤(IV)，在所述介质层d的表面覆盖一层导电层e，所述导电层e包括设置在所述介电层d上且与所述外延层30层叠对应的第一子导电层e1，所述第一子导电层e1包括远离所述介电层d及所述外延层30的参考面e11。所述导电层e的材料可以为但不仅限于多晶硅，金属等。
步骤(V)，以所述参考面e11为参考，移除所述参考面e11以上的导电层e，介电层d以及隔离层c。从而形成如图10所示的结构，留下来的介电层d即为栅介电层40，留下来的导电层e即为栅极区50，留下的隔离层c即为第一隔离层80。具体地，在此步骤中，先利用平整化工艺将所述参考面e11为参考，移除所述参考面e11以上的导电层e及隔离层c。接着，再利用回刻工艺，将所述参考面e11以上的所述介电层d刻掉，露出部分沟道70及掩膜层a。接着，在所述第一隔离层80上开设对应所述源区20的第一贯孔81。
步骤S206，在所述沟道70远离所述第一掺杂类型衬底10的端部形成漏区60。具体地，在此步骤中，所述漏区60的形成过程可以为：移除所述掩膜层a，对所述沟道70远离所述第一掺杂类型衬底10的端部进行部分第一掺杂类型掺杂以形成所述漏区60。
优选地，在所述步骤S205之后，在步骤S206之前，所述隧穿场效应晶体 管的制备流程还包括：
在所述栅极区50上形成开设有第二贯孔101及第三贯孔102的第二隔离层100，所述第二隔离层100覆盖所述第一隔离层80及所述栅极区50。所述第二隔离层100用于隔离所述栅极区50与外界之间的接触，起到保护所述栅极区50的作用。所述第二贯孔101一端连接所述第一贯孔81的一端，使得所述第二贯孔101与所述第一贯孔81形成一个联通的孔。在本实施方式中，所述第一贯孔81的中心线与所述第二贯孔101的中心线重合。所述第三贯孔102对应所述栅极区50设置。
步骤S207，对应所述源区20、所述漏区60及所述栅极区50分别形成源极91、漏极92及栅极93。所述源极91穿过所述第一贯孔81及所述第二贯孔101连接所述源区20，所述栅极93穿过所述第三贯孔102连接所述栅极区50。所述漏极92连接所述漏区60。
在其他实施方式中，所述第二隔离层仅仅覆盖所述栅极区，此时，所述第二隔离层对应所述栅极区开设第二贯孔。所述源极穿过所述第一贯孔连接所述源区，所述栅极穿过所述第二贯孔连接所述栅极区。
优选地，所述隧穿场效应晶体管1的制备方法还包括：
形成第一欧姆接触层(图未示)，所述第一欧姆接触层设置在所述源极91与所述源区20之间，所述源极91通过所述第一欧姆接触层与所述源区20连接，以减小所述源极91与所述源区20之间的接触电阻。
优选地，所述隧穿场效应晶体管1的制备方法还包括：
形成第二欧姆接触层(图未示)，所述第二欧姆接触层设置在所述栅极93与所述栅极区50之间，所述栅极93通过所述第二欧姆接触层与所述栅极区50连接，以减小所述栅极93与所述栅极区50之间的接触电阻。
优选地，所述隧穿场效应晶体管1的制备方法还包括：
形成第三欧姆接触层(图未示)，所述第三欧姆接触层设置在所述漏极92与所述漏区60之间，所述漏极92通过所述第三欧姆接触层与所述漏区60连接，以减小所述漏极92与所述漏区60之间的接触电阻。
相较于现有技术，本发明隧穿场效应晶体管1中，由于所述栅极区50层叠设置在所述栅介质层40及所述外延层30上，当所述栅极区50加载电信号 时，所述栅极区50加载的电信号的电场的方向为竖直方向。由此可见，所述栅极区50加载的电信号的电场方向与所述电子的隧穿方向一致，即为线隧穿机制。因此，所述源区20的价带中的电子隧穿至所述外延层30的导带时的隧穿效率较高，可以产生较高的开态电流和陡直的亚阈值摆幅(远小于60mV/dec)。同时，由于漏区60位于所述沟道70的端部，距离所述源区20及所述外延层30较远，因此，所述漏区60上加载的电信号对所述源区20及所述外延层30形成的隧穿结的影响较弱，从而改善了所述隧穿场效应晶体管1的亚阈值摆幅。且所述栅极区50、栅介质层40及外延层30依次层叠，从而减小了第一掺杂类型衬底10的使用面积，提高了集成度。
进一步地，本发明隧穿场效应晶体管1采用垂直于所述第一掺杂类型衬底10表面中部的沟道70，在沟道70远离所述第一掺杂类型衬底10的端部设置漏区60，进一步减小了第一掺杂类型衬底10的使用面积，提高了集成度。
再进一步地，由于本发明隧穿场效应晶体管1的漏区60和栅极区50之间不存在重叠区域且所述栅极区50环绕所述沟道70，因此，所述隧穿场效应晶体管1的泄露电流更小。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (19)

  1. 一种隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管包括：
    第一掺杂类型衬底；
    沟道，凸出设置于所述第一掺杂类型衬底中部；
    源区，设置于所述第一掺杂类型衬底上，且围绕所述沟道设置；
    外延层，设置于所述源区上，围绕所述沟道设置；
    栅介质层，设置于所述外延层上，且围绕所述沟道设置；
    栅极区，设置于所述栅介质层上；以及
    漏区，设置在所述沟道远离所述衬底的端部。
  2. 如权利要求1所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：
    电极，所述电极对应连接所述源区、漏区及栅极区，以形成所述源极、漏极及栅极。
  3. 如权利要求2所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：
    第一隔离层，设置于所述源区上，所述第一隔离层形成有第一贯孔，所述源极穿过所述第一贯孔以连接所述源区；
    第二隔离层，设置于所述栅极区上，所述第二隔离层形成有第二贯孔，所述栅极穿过所述第二贯孔以连接所述栅极区。
  4. 如权利要求2所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：
    第一隔离层，设置于所述源区上，所述第一隔离层形成有第一贯孔；
    第二隔离层，设置于所述第一隔离层及所述栅极区上，所述第二隔离层形成有对应所述第一贯孔的第二贯孔以及对应所述栅极区的第三贯孔；
    所述源极穿过所述第一贯孔及所述第二贯孔连接所述源区，所述栅极穿过 所述第三贯孔连接所述栅极区。
  5. 如权利要求2至4任意一项所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：
    第一欧姆接触层，所述源极通过所述第一欧姆接触层与所述源区连接。
  6. 如权利要求2至5任意一项所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：
    第二欧姆接触层，所述栅极通过所述第二欧姆接触层与所述栅极区连接。
  7. 如权利要求1至6任意一项所述的隧穿场效应晶体管，其特征在于，所述栅介质层包括第一部分及与所述第一部分连接的第二部分，所述第一部分设置于所述外延层上且环绕所述沟道设置且与所述沟道连接，所述第二部分设置于所述外延层上且所述第二部分的一端连接所述第一部分的一端。
  8. 如权利要求7所述的隧穿场效应晶体管，其特征在于，所述栅极区设置于所述第二部分上且所述栅极区一端环绕所述第一部分。
  9. 如权利要求1至8任意一项所述的隧穿场效应晶体管，其特征在于，所述源区为由所述第一掺杂类型衬底进行第二掺杂类型离子掺杂而形成，所述漏区由所述沟道进行第一掺杂类型离子掺杂而形成。
  10. 如权利要求9所述的隧穿场效应晶体管，其特征在于，所述第一掺杂类型为P型，所述第二掺杂类型为N型；或者所述第一掺杂类型为N型，所述第二掺杂类型为P型。
  11. 一种隧穿场效应晶体管的制备方法，其特征在于，所述隧穿场效应晶体管的制备方法包括：
    提供第一掺杂类型衬底；
    形成凸出设置于所述第一掺杂类型衬底中部的沟道；
    在所述第一掺杂类型衬底上，且围绕所述沟道形成源区；
    围绕所述沟道且在源区远离所述第一掺杂类型衬底的部分表面依次形成外延层及栅介质层；
    围绕所述沟道且在所述栅介质层上形成栅极区；以及
    在所述沟道远离所述第一掺杂类型衬底的端部形成漏区。
  12. 如权利要求11所述的隧穿场效应晶体管的制备方法，其特征在于，所述隧穿场效应晶体管的制备方法还包括：
    对应所述源区、漏区及栅极区分别形成与源极、漏极及栅极，所述源极、所述漏极及所述栅极分别与所述源区、漏区及栅极区连接。
  13. 如权利要求12所述的隧穿场效应晶体管的制备方法，其特征在于，在所述“对应所述源区、漏区及栅极区分别形成与源极、漏极及栅极，所述源极、所述漏极及所述栅极分别与所述源区、漏区及栅极区连接”步骤之前，所述隧穿场效应晶体管的制备方法还包括：
    在源区未形成所述外延层及栅介质层的表面形成开设有第一贯孔的第一隔离层；
    在所述栅极区上形成开设有第二贯孔的第二隔离层；所述源极穿过所述第一贯孔与所述源区连接，所述栅极穿过所述第二贯孔与所述栅极区连接。
  14. 如权利要求12所述的隧穿场效应晶体管的制备方法，其特征在于，在所述“对应所述源区、漏区及栅极区分别形成与源极、漏极及栅极，所述源极、所述漏极及所述栅极分别与所述源区、漏区及栅极区连接”步骤之前，所述隧穿场效应晶体管的制备方法还包括：
    在源区未形成所述外延层及所述栅介质层的表面形成开设有第一贯孔的第一隔离层；
    在所述第一隔离层及所述栅极区形成开设有第二贯孔及第三贯孔的第二隔离层，所述第二贯孔连通所述第一贯孔，所述第三贯孔连接所述栅极区；
    所述源极穿过所述第一贯孔及所述第二贯孔连接所述源区，所述栅极穿过所述第三贯孔连接所述栅极区。
  15. 如权利要求12-14任意一项所述的隧穿场效应晶体管的制备方法，其特征在于，所述隧穿场效应晶体管的制备方法还包括：
    形成第一欧姆接触层，以使所述源极通过所述第一欧姆接触层与所述源区连接。
  16. 如权利要求12-15任意一项所述的隧穿场效应晶体管的制备方法，其特征在于，所述隧穿场效应晶体管的制备方法还包括：
    形成第二欧姆接触层，以使所述栅极通过所述第二欧姆接触层与所述栅极区连接。
  17. 如权利要求11至16任意一项所述的隧穿场效应晶体管的制备方法，其特征在于，在所述“提供第一掺杂类型衬底”步骤及所述“形成凸设于所述第一掺杂类型衬底中部的沟道”步骤之间，所述隧穿场效应晶体管的制备方法还包括：
    在所述第一掺杂类型衬底表面的中部形成掩膜层，所述掩膜层用于保护所述被其覆盖的第一掺杂类型衬底的表面；
    所述“形成凸出设置于所述第一掺杂类型衬底中部的沟道”步骤包括：
    对表面的中部覆盖掩膜层的第一掺杂类型衬底的表面进行蚀刻，以形成凸出设置于所述第一掺杂类型衬底中部的沟道。
  18. 如权利要求11至17任意一项所述的隧穿场效应晶体管的制备方法，其特征在于，所述“围绕所述沟道且在源区远离所述第一掺杂类型衬底的部分表面依次形成外延层及栅介质层”步骤包括：
    围绕所述沟道且在源区远离所述第一掺杂类型衬底的部分表面形成所述外延层；
    形成覆盖所述外延层，所述沟道表面及所述掩膜层表面的介电层；
    所述“围绕所述沟道且在所述栅介质层上形成所述栅极区”步骤包括：
    覆盖所述介电层形成导电层，所述导电层包括设置在所述介电层上且与所述外延层层叠对应的第一子导电层，所述第一子导电层包括远离所述介电层及所述外延层的参考面；
    移除所述参考面以上的导电层，介电层，以及隔离层；剩余的导电层即为栅极区，剩余的介电层即为栅介电层。
  19. 如权利要求17或18所述的隧穿场效应晶体管的制备方法，其特征在于，在所述“对所述沟道远离所述衬底的端部进行第一掺杂类型掺杂以形成漏区”步骤之前，所述隧穿场效应晶体管的制备方法还包括：
    移除所述掩膜层。
PCT/CN2015/077666 2014-07-15 2015-04-28 隧穿场效应晶体管及隧穿场效应晶体管的制备方法 WO2016008326A1 (zh)

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