WO2016119682A1 - 隧穿场效应晶体管及其制备方法 - Google Patents

隧穿场效应晶体管及其制备方法 Download PDF

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Publication number
WO2016119682A1
WO2016119682A1 PCT/CN2016/072183 CN2016072183W WO2016119682A1 WO 2016119682 A1 WO2016119682 A1 WO 2016119682A1 CN 2016072183 W CN2016072183 W CN 2016072183W WO 2016119682 A1 WO2016119682 A1 WO 2016119682A1
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layer
gate
region
source region
drain
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PCT/CN2016/072183
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English (en)
French (fr)
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赵静
杨喜超
张臣雄
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]

Definitions

  • the invention relates to a tunneling field effect transistor and a preparation method thereof.
  • TFET tunneling field-effect transistor
  • the source region is heavily P-doped and the drain region is heavily doped with N-type; for P-type TFETs, the source region is heavily doped with N-type and the drain region is heavily doped with P-type.
  • the difference in source and drain doping types results in a TFET forming a different operating mechanism than the MOSFET, ie, the carrier quantum tunneling mechanism, which can also be referred to as band tunneling.
  • the electrons at the bottom of the conduction band of the source region tunnel into the valence band of the drain region under the gate electric field to form a tunneling current, and tunnel the electron flow to the drain region to form a drain current under the action of the drain voltage.
  • the TFET Due to the different working mechanism of the MOSFET, the TFET is not limited by kT/q, and its subthreshold swing SS ⁇ 60mV/dec can reduce the static leakage current of the device.
  • the tunneling direction of carriers during operation of the TFET is not in the same direction as the gate electric field, that is, the point tunneling mechanism. Therefore, in the prior art, the point tunneling mechanism is used to cause a low probability of carrier tunneling, so that the TFET has a disadvantage of a small tunneling current.
  • the overlapping area between the source region and the gate region is limited, so that the tunneling area is small, and the tunneling current density is proportional to the tunneling area and the tunneling probability, so Lead to lower tunneling current.
  • the invention provides a tunneling field effect transistor and a preparation method thereof, which can increase a tunneling area and effectively increase a tunneling current.
  • the tunneling field effect transistor is provided to include a source region, two drain regions, and two gate regions;
  • Two of the drain regions are respectively disposed at opposite sides of the source region in a first direction, and a channel layer is disposed between the source region and the two drain regions, and the channel layer forms the a channel between the source region and the drain region;
  • Two of the gate regions are respectively disposed at opposite sides of the source region in a second direction, the second direction is perpendicular to the first direction; and the source region and the two gate regions are respectively disposed between a first epitaxial layer and a gate dielectric layer; the first epitaxial layer is disposed between the source region and the gate dielectric layer, and the first epitaxial layer forms a pn tunneling junction with the source region; A side of the dielectric layer remote from the first epitaxial layer is coupled to the gate region, the gate dielectric layer for isolating the first epitaxial layer from the gate region.
  • the first direction is an up-and-down direction with respect to the source area
  • the second direction is a left-right direction relative to the source area
  • the two drain regions include a first drain region and a second drain region; the first drain region is located directly below the source region, and the second drain region is located directly above the source region;
  • the total size of the two gate regions and the source region is equal to or smaller than the size of the first drain region, and the source region is located directly above the intermediate position of the first drain region.
  • the two gate regions are respectively disposed directly above the two ends of the first drain region.
  • the channel layer includes a first channel layer and a second channel layer, and the first channel layer is disposed in the source region Between the first drain region and the first drain region, the second channel layer is disposed between the source region and the second drain region; the first channel layer, the source region, and the second channel The layer and the second drain region have the same size in the second direction and are aligned in the first direction.
  • the first drain region is convexly formed at a position corresponding to the source region to form a boss.
  • a fourth possible implementation two of the gate regions
  • the shape structure is the same and is symmetrically arranged with respect to the source region.
  • the gate region is L-shaped, and the two arms are respectively a first portion and a second portion, and the first portion is opposite to the source The second portion extends from a bottom end of the first portion away from the source.
  • an isolation layer is disposed between the two gate regions and the first drain region, and the isolation layer The first drain zone is isolated.
  • the gate region extends at one end in the third direction toward the other gate region to form a gate connection portion, and the connection portion is located on a side of the source region in a third direction.
  • the third direction is perpendicular to the first direction and the second direction; the two gate regions are connected by the gate connection portion and form a first slot;
  • the gate dielectric layer extends toward the other gate dielectric layer at one end in the third direction to form a dielectric connection portion, and the two gate dielectric layers are connected through the dielectric connection portion to form a second trench;
  • the first epitaxial layer extends toward the other first epitaxial layer at one end in the third direction to form an epitaxial connection portion, and the two first epitaxial layers are connected through the epitaxial connection portion to form a third trench;
  • the medium connecting portion, the epitaxial connecting portion and the gate connecting portion are located on the same side of the source region in a third direction; the medium connecting portion is located between the gate connecting portion and the epitaxial connecting portion, The dielectric connection portion isolates the gate connection portion from the epitaxial connection portion; the epitaxial connection portion is located between the gate connection portion and the source region, and between the epitaxial connection portion and the source region Forming a pn tunneling junction;
  • Two of the gate dielectric layers are embedded in the first trench, two first epitaxial layers are embedded in the second trench, and the source region is embedded in the third trench.
  • the two drain regions have the same shape structure; the two drain regions are symmetrically disposed with respect to the source region.
  • the tunneling field effect transistor further includes a substrate, and the substrate and the gate connection portion are respectively disposed in the third direction The opposite sides of the source zone;
  • the total size of the two drain regions, the channel layer and the source region is equal to or smaller than the size of the substrate; in the second direction, the two gate regions, the gate Medium layer, said first An epitaxial layer and the source region have an overall size equal to or smaller than the size of the substrate.
  • a second epitaxial layer is formed between the first epitaxial layer and the source region; the first epitaxial layer and the second epitaxial layer
  • the doping type of the layer is opposite, the doping type of the second epitaxial layer is the same as the doping type of the source region, and the doping concentration of the second epitaxial layer is greater than the doping concentration of the source region to A steep pn tunnel junction is formed between the first epitaxial layer and the source region.
  • the tunneling field effect transistor further includes an electrode contact structure, wherein the gate region, the drain region, and the source region are respectively connected with an electrode contact structure to respectively form a gate and a drain. Extreme and source.
  • a method of fabricating a tunneling field effect transistor comprising the steps of:
  • the drain region is two, and the two drain regions are respectively disposed at opposite sides of the source region in a second direction, the source region and two a channel layer is disposed between the drain regions, and the channel layer forms a channel between the source region and the drain region;
  • first epitaxial layer Forming a first epitaxial layer, a gate dielectric layer, and a gate region, wherein the two gate regions are respectively disposed at opposite sides of the source region in a second direction, and the second direction is perpendicular to the first direction; a first epitaxial layer and a gate dielectric layer are disposed between the source region and the two gate regions; the first epitaxial layer is disposed between the source region and the gate dielectric layer, and the first epitaxial layer Forming a pn tunneling junction with the source region; a side of the gate dielectric layer remote from the first epitaxial layer is coupled to the gate region, the gate dielectric layer for using the first epitaxial layer and the The gate area is isolated.
  • the two drain regions include a first drain region and a second drain region;
  • the channel layer includes a first channel layer and a second channel layer, the first channel a layer is disposed between the source region and the first drain region, and the second channel layer is disposed between the source region and the second drain region;
  • the upper region of the first drain region includes a first region and two second regions, and the first region is located between the two second regions in the second direction Etching the portion of the hard mask layer on the second region, leaving only the portion of the hard mask layer in the first region;
  • the hard mask layer is removed.
  • the fifth semiconductor layer, the fourth semiconductor layer, and the third semiconductor are etched in the step of using the hard mask layer as a mask. a layer, and a second semiconductor layer, such that only the portion of the fourth layer remaining on the first region", before the step of "removing the hard mask layer", further comprising the step of: hard mask layer As a mask, the first semiconductor layer is etched such that a first semiconductor layer forms a land at an intermediate portion in the second direction.
  • the step of “preparing the formation of the first epitaxial layer, the gate dielectric layer, and the gate region” includes the following steps:
  • first epitaxial layer and a gate dielectric layer Forming a first epitaxial layer and a gate dielectric layer on both sides of the source region, the first epitaxial layer and the gate dielectric layer being located above the isolation layer;
  • a gate region is formed on a side of each of the gate dielectric layers away from the source region, the gate region being located above the isolation layer.
  • the step of “forming a drain region and a source region on the substrate” includes the following steps:
  • the source region and the drain region are both formed by an ion implantation process.
  • the step is “made The steps of forming the first epitaxial layer, the gate dielectric layer and the gate region include the following steps:
  • a semiconductor layer on the semiconductor strip wherein the semiconductor strip is formed with a semiconductor layer at both sides in the second direction such that the semiconductor layer has a third trench opening toward the source region, the source region Located in the third trench; etching both ends of the semiconductor layer in the first direction to prepare two first epitaxial layers and epitaxial portions thereof; in the first direction, the first epitaxial layer a gap exists between the end portion and the drain region, and a size of the first epitaxial layer is greater than or equal to a size of the source region;
  • the gate region material is at both ends in the first direction to prepare two gate regions and a gate connection portion thereof; in the first direction, the gate region is the same size as the gate dielectric layer and the first epitaxial layer.
  • the method for fabricating a tunneling field effect transistor further includes the steps of: forming an electrode contact structure, wherein each of the drain region, the source region, and the gate region is connected with an electrode contact structure to form a drain Pole, source and gate.
  • the two drain regions and the two gate regions are surrounded by the source region, so that the source region is completely under the control of the two gate regions, and the source region and the gate region overlap each other.
  • the current-carrying electrons are tunneled by the electric field of the gate region; the first epitaxial layer is disposed between the source region and the gate dielectric layer, and the tunneling type is linear tunneling, the tunneling area is large, and the electric field direction of the gate region is The electron tunneling direction of the source region is on a line, and the tunneling probability is large, thereby effectively increasing the tunneling current.
  • FIG. 1 is a schematic cross-sectional view of a tunneling field effect transistor according to a first embodiment of the present invention
  • FIG. 2 is a flow chart of a method of fabricating the tunneling field effect transistor of FIG. 1;
  • FIG. 3 is a cross-sectional view corresponding to step S11 of the method for fabricating the tunneling field effect transistor of FIG. 1;
  • step S12 is a cross-sectional view corresponding to step S12 of the method for fabricating the tunneling field effect transistor of FIG. 1;
  • FIG. 5 is a cross-sectional view corresponding to step S126 of the method for fabricating the tunneling field effect transistor of FIG. 1;
  • step S127 is a flow chart of step S127 of the method of fabricating the tunneling field effect transistor of FIG. 1;
  • step S129 is a cross-sectional view corresponding to step S129 of the method of fabricating the tunneling field effect transistor of FIG. 1;
  • FIG. 9 is a cross-sectional view corresponding to step S1321 of the method of fabricating the tunneling field effect transistor of FIG. 1;
  • step S1322 of the method for fabricating the tunneling field effect transistor of FIG. 1;
  • step S1323 is a cross-sectional view corresponding to step S1323 of the method for fabricating the tunneling field effect transistor of FIG. 1;
  • Figure 12 is a cross-sectional view corresponding to step S1331 of the method of fabricating the tunneling field effect transistor of Figure 1;
  • Figure 13 is a cross-sectional view corresponding to step S1332 of the method of fabricating the tunneling field effect transistor of Figure 1;
  • Figure 14 is a cross-sectional view corresponding to step S1333 of the method of fabricating the tunneling field effect transistor of Figure 1;
  • step S14 is a cross-sectional view corresponding to step S14 of the method for fabricating the tunneling field effect transistor of FIG.
  • FIG. 16 is a perspective exploded view of a tunneling field effect transistor according to a second embodiment of the present invention.
  • FIG. 17 is a flow chart showing a method of fabricating the tunneling field effect transistor of FIG. 16;
  • Figure 18 is a cross-sectional view corresponding to step S21 of the method of fabricating the tunneling field effect transistor of Figure 16;
  • Figure 19 is a cross-sectional view corresponding to step S2212 of the method of fabricating the tunneling field effect transistor of Figure 16;
  • FIG. 20 is a perspective view corresponding to step S2213 of the method for fabricating the tunneling field effect transistor of FIG. 16;
  • FIG. 21 is a cross-sectional view corresponding to step S221 of the method of fabricating the tunneling field effect transistor of FIG. 16;
  • Figure 22 is a cross-sectional view corresponding to step S2222 of the method of fabricating the tunneling field effect transistor of Figure 16;
  • step S2231 is a cross section corresponding to step S2231 of the method for fabricating the tunneling field effect transistor of FIG. Figure
  • Figure 24 is a cross-sectional view corresponding to step S2232 of the method of fabricating the tunneling field effect transistor of Figure 16;
  • Figure 25 is a cross-sectional view corresponding to step S2233 of the method of fabricating the tunneling field effect transistor of Figure 16;
  • FIG. 26 and FIG. 27 are cross-sectional views of two angles corresponding to step S23 of the method for fabricating the tunneling field effect transistor of FIG.
  • FIG. 28 is a cross-sectional view of a tunneling field effect transistor according to a third embodiment of the present invention.
  • Figure 29 is a cross-sectional view showing a tunneling field effect transistor according to a fourth embodiment of the present invention.
  • the tunneling field effect transistor includes a source region 11, two drain regions 12, 13, and two gate regions 14, 15.
  • the first direction Y is the vertical direction with respect to the source region 11
  • the second direction X is the horizontal direction with respect to the source region 11.
  • the source region 11 is in the shape of a square to facilitate the preparation of the source region 11.
  • the two drain regions 12, 13 include a first drain region 12 and a second drain region 13. The first drain region is located directly below the first drain region 12, and the second drain region 13 is located directly above the source region 11, such that the first drain region 12 and the second drain region 13 are respectively disposed in the source region along the first direction Y. 11 opposite sides.
  • the shape of the two gate regions 14, 15 is substantially the same, and the two gate regions 14, 15 are respectively disposed at opposite sides of the source region 11 in the second direction X.
  • the first drain region 12, the second drain region 13, and the two gate regions 14, 15 are surrounded by the source region 11, so that the source region 11 is completely under the control of the gate region, and the source region 11 and the gate regions 14, 15 have
  • the current-carrying electrons in the overlapping regions (shown by the dotted line in Fig. 1) are tunneled by the electric field of the gate region, thereby increasing the tunneling current.
  • the overall size of the two gate regions 14, 15 and the source region 11 may be equal to or smaller than the size of the first drain region 12, and the source region 11 is located at the middle of the first drain region 12.
  • the two gate regions 14 and 15 are respectively disposed directly above the two ends of the first drain region 11.
  • the first drain region 11 can be used to support and support the entire tunneling field effect transistor.
  • a channel layer is disposed between both the first drain region 12 and the second drain region 13 and the source region 11, that is, there are two channel layers, which are the first channel layer 102 and the second channel layer 103, respectively.
  • the first channel layer 102 is disposed between the source region 11 and the first drain region 12 to form a channel between the source region 11 and the first drain region 12.
  • the second channel layer 103 is disposed between the source region 11 and the second drain region 13 to form a channel between the source region 11 and the second drain region 13.
  • the first channel layer 102, the source region 11, the second channel layer 103, and the second drain region 13 are sequentially superposed over the first drain region.
  • the first channel layer 102, the source region 11, the second channel layer 103, and the second drain region 13 have the same size in the second direction X, and are aligned in the first direction, thereby facilitating the first etching of the four portions. Forming, which is conducive to processing and preparation. Further, a bump 121 is formed upwardly at a position corresponding to the source region 11 on the first drain region 12, and the first channel layer 102, the source region 11, the second channel layer 103, and the second drain region 13 are both disposed. On the boss 121, thereby facilitating the processing of the components located on both sides in the second direction X of the source region 11, it is convenient to provide the isolation layer 122 to isolate the source region 11 from the gate regions 14, 15. Preferably, both the boss 121 and the first channel layer 102 have the same size in the second direction X, so that the both sides of the source region 11 are timed to form the boss 121.
  • the two gate regions 14, 15 have the same shape and are symmetrically disposed with respect to the source region 11.
  • the gate region 14 is taken as an example for specific description.
  • the gate region is L-shaped, and the two arms are respectively a first portion 141 and a second portion 142.
  • the first portion 141 is disposed opposite to the source, and the gate region is formed on the first portion 141.
  • the second portion 142 extends from the bottom end of the first portion 141 in a direction away from the source 11, and the second portion 142 is connected to the gate 140.
  • the second portion 142 facilitates the placement of the gate 140.
  • An isolation layer 122 is disposed between the two gate regions 14, 15 and the first drain region 12.
  • the isolation layer 122 isolates the gate regions 14, 15 from the first drain region 11 to avoid electrical connection between the gate region and the first drain region. connection.
  • a side wall 16 is further disposed on the side of the gate region 14 away from the source region 11.
  • the gate region 142 and the gate electrode 140 are embedded in the sidewall wall 16.
  • the sidewall region 14 can be used to tunnel the gate region 14 and other components outside the field effect transistor.
  • one end of the gate 140 is exposed outside the sidewall 16 to provide electrical connection to other components to apply a voltage to the gate region 14.
  • the gate region 14 may also be a flat plate parallel to the surface of the source region 11, that is, the gate region 14 includes only the aforementioned first portion 141.
  • a first epitaxial layer 17 and a gate dielectric layer 18 are disposed between the source region 11 and each of the gate regions 14, 15.
  • Source for example, the structure between the region 11 and the gate region 14 is disposed between the source region 11 and the gate dielectric layer 18, the tunneling type is linear tunneling, and the first epitaxial layer 17 and the source region 11 are The intervening contact surface forms a tunneling surface for electron tunneling, and the tunneling area of the opposite point tunneling is large; the first epitaxial layer 17 is disposed between the source region 11 and the gate region 14, and the electric field of the electric signal loaded in the gate region 14
  • the direction is opposite to the tunneling direction of the electrons, that is, the electric field direction of the electric signal loaded by the gate region 14 is parallel to the tunneling direction of the electrons, so that the electric field direction of the gate region 14 and the electron tunneling direction of the source region 11 are in a line, tunneling
  • the probability is large, so that the tunneling current is effectively increased.
  • the surface of the source region 11 facing the first epitaxial layer 17 is completely connected to the first epitaxial layer 17 so that the first epitaxial layer 17 is completely shielded from the left and right sides of the source region 11, and the external surface area of the source region 11 can be utilized to form tunneling. Face, which facilitates tunneling.
  • the size of the first epitaxial layer 17 is equal to the total height of the first channel layer 102, the source region 11 and the second channel layer 103, so as to be processed.
  • the tunneling field effect transistor further includes a substrate 19 and an electrode contact structure, and the substrate 19 is disposed at the bottom of the first drain 12.
  • the substrate 19 is disposed at the bottom of the first drain 12.
  • the entire tunneling field effect transistor can be supported, and the processing of the source region 11, the gate regions 14, 15 and the like can be facilitated.
  • Each of the gate region, the drain region, and the source region and the upper portion are respectively connected with an electrode contact structure to respectively form a gate, a drain and a source, thereby realizing electrical connection between the tunneling field effect transistor and other components.
  • the gate 140 corresponding to the gate region 14 is illustrated.
  • the gate 140 is disposed on the sidewall and is connected to the second portion 142 of the gate region 14.
  • the gate 140 It can also be connected to the first portion 141 of the gate region.
  • the source 110 is disposed at the right side of the source region 11, that is, the source 110 is disposed on one side of the source region where the gate region 15 is provided.
  • the gate region 15, the gate dielectric layer 18, and the first epitaxial layer 17 are respectively provided with corresponding holes (not shown), and the source 110 is embedded in the sidewall. And wearing a hole, one end of the source 110 is connected to the source area 11, and the other end is exposed outside the side wall.
  • the portion of the source 110 located at the vacant hole and the gate region 15, the gate dielectric layer 18 and the first epitaxial layer 17 are filled with a sidewall material to avoid contact.
  • the drain includes a first drain 120 and a second drain 130, wherein the first drain 120 is connected to the first drain region 12, and the second drain 130 is connected to the second drain region 130.
  • the first drain 120 is columnar and electrically connected
  • the drain region 12 is embedded in the sidewall 16 and the insulating layer 122 to achieve isolation between the first drain 120 and other components.
  • the right side of the first drain 120 is located outside the sidewall 16 for convenience.
  • a drain 120 is electrically connected to the outside.
  • the material of the side wall 16 may be the same as the material of the insulating layer 122, and may be silicon nitride or the like.
  • the first drain 120 and the source 110 are disposed on the same side of the source region 11.
  • the second portion of the gate region 15 can be A corresponding evacuation structure is formed by etching, and an insulating material such as a sidewall is filled between the drain 120 and the gate region 15 to isolate the first drain 120 from the gate region 15.
  • the drain connected to the second drain region 13 is a second drain 130.
  • the second drain 130 is provided with a receiving groove (not shown).
  • the opening of the receiving slot faces the source region 11, and the second drain region 13 is disposed.
  • the drain surrounds the drain region 12, achieving a reliable connection between the two.
  • FIG. 2 is a flowchart of a method for fabricating a tunneling field effect transistor according to a first embodiment of the present invention.
  • the method of fabricating the tunneling field effect transistor includes, but is not limited to, the following steps.
  • a substrate 19 is provided.
  • the material of the substrate is silicon.
  • the substrate can be a rectangular substrate.
  • the substrate may also be a binary or ternary compound semiconductor of a group II-IV, or a group III-V, or a group IV-IV of germanium (Ge) or silicon germanium, gallium arsenide, or the like, and an insulating substrate. Any of silicon (Silicon on Insulator, SOI) or germanium on Insulator (GeOI) on an insulating substrate.
  • Step S12 forming a drain region and a source region on the substrate 19, the drain region being two, and the two drain regions are respectively disposed at opposite sides of the source region in a second direction, A channel layer is disposed between the source region and the two drain regions, and the channel layer forms a channel between the source region and the drain region.
  • the drain region includes a first drain region and a second drain region
  • the channel layer includes a first channel layer and a second channel layer
  • the first channel layer is disposed in the source region and the first drain region
  • Between the second channel layer is disposed between the source region and the second drain region.
  • the step S12 may specifically include the following sub-steps.
  • Step S121 as shown in FIG. 4, a first semiconductor layer 12a is formed on the substrate 19, and the first semiconductor layer 12a is used to prepare the first drain region 12.
  • the first semiconductor layer 12a may be an in-situ doped N-type heavily doped semiconductor layer formed by deposition, and the material thereof may be a silicon material, or may be a germanium, a germanium silicon material, a III-V material, or a III-V group. Any of chemical compounds and the like.
  • a second semiconductor layer 102a is formed on the first semiconductor layer 12a, and the second semiconductor layer 102a is used to prepare the first channel layer 102.
  • the second semiconductor layer may be deposited by deposition
  • the semiconductor layer may be made of a silicon material, or may be any of tantalum, niobium silicon material, group III-V material, or group III-V compound.
  • a third semiconductor layer 11a is formed on the second semiconductor layer 102a, and the third semiconductor layer 11a is used to prepare the source region 11.
  • the third semiconductor layer may be a P-type heavily doped semiconductor layer formed by deposition, and the material thereof may be a silicon material, or may be a germanium, a germanium silicon material, a III-V material, or a III-V compound. Any one.
  • a fourth semiconductor layer 103a is formed on the third semiconductor layer 11a, and the fourth semiconductor layer 103a is used to prepare the second channel layer 103.
  • the third semiconductor layer may be a deposited semiconductor layer formed by deposition, and the material may be a silicon material, or may be a germanium, a germanium silicon material, a III-V material, or a III-V compound. Any one.
  • Step S125 forming a fifth semiconductor layer 13a on the fourth semiconductor layer 103a for preparing a second drain region.
  • the fifth semiconductor layer may be an N-type heavily doped semiconductor layer formed by deposition, and the material thereof may be a silicon material, or may be a germanium, a germanium silicon material, a III-V material, or a III-V compound. Any one.
  • the semi-finished structure of the tunneling field effect transistor prepared through this step is as shown in FIG.
  • the above deposition process may be performed by an epitaxial process such as low pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD), or molecular beam epitaxy (MBE), or by an ion implantation process.
  • LPCVD low pressure chemical vapor deposition
  • PVD physical vapor deposition
  • MBE molecular beam epitaxy
  • the doped N-type impurities so as to include arsenic ions, phosphorus ions, etc., and the P-type impurities generally include: boron ions, boron fluoride ions, and the like.
  • Step S126 depositing a hard mask layer 100a on the fifth semiconductor layer, etching portions of the hard mask layer at both ends in the second direction, leaving only a portion of the hard mask layer intermediate in the second direction.
  • the preparation of the hard mask layer can be achieved by low pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD).
  • Step S127 etching the fifth semiconductor layer 13a, the fourth semiconductor layer 103a, the third semiconductor layer 11a, and the second semiconductor layer 102a with the hard mask layer as a mask, so that the four layers remain only in the hard mask layer.
  • the hard mask layer is used to prevent the influence of the etching liquid on the material under the mask layer during etching.
  • the fifth semiconductor layer is prepared to form the second drain region 13
  • the fourth semiconductor layer is formed to form the second channel layer 103
  • the third semiconductor layer is formed to form the source region 11
  • the second semiconductor layer is prepared.
  • a first channel layer 102 is formed.
  • step S1208 the first semiconductor layer 12a is etched with the hard mask layer as a mask, so that the first semiconductor layer forms a bump 121 at an intermediate portion in the second direction X.
  • the boss 121 may not be formed on the first region A of the first semiconductor layer, that is, the upper surface of the first drain region 12 is a plane.
  • step S129 the hard mask layer is removed, and the structure formed after removing the hard mask layer is as shown in FIG. 7.
  • Step S13 preparing a first epitaxial layer, a gate dielectric layer and a gate region, wherein the two gate regions 14, 15 are respectively disposed at opposite sides of the source region 11 in a second direction, and the second direction X is perpendicular
  • the first direction Y is defined; the first epitaxial layer 17 and the gate dielectric layer 18 are disposed between the source region 11 and the two gate regions 14 and 15.
  • the first epitaxial layer 17 is disposed between the source region 11 and the gate dielectric layer 18.
  • the first epitaxial layer 17 forms a pn tunneling junction with the source region 11; and a side of the gate dielectric layer 18 away from the first epitaxial layer 17 and the gate region 14 Connected, a gate dielectric layer 18 is used to isolate the first epitaxial layer 17 from the gate region 14.
  • This step may specifically include the following sub-steps.
  • Step S131 as shown in FIG. 8, an isolation layer 122 is formed on the two second regions B on the first drain region 12, and the isolation layer 122 is used to insulate the drain region 12 and the gate regions 14, 15.
  • the isolation layer 122 can be an insulating hard mask layer.
  • a hard mask layer may be deposited over the entirety of the first drain region 12 and the fifth semiconductor layer, and then the hard mask layer on the fifth semiconductor layer is etched away, leaving only the second region B A hard mask layer is prepared to form an isolation layer.
  • the upper surface of the isolation layer 122 has a height equal to or lower than the upper surface height of the first channel 102 to ensure a corresponding area between the gate region and the source region 11.
  • the upper surface height of the isolation layer is lower than the upper surface height of the first channel, and the upper surface of the isolation layer is flush with the upper surface of the boss 121.
  • step S132 a first epitaxial layer 17 and a gate dielectric layer 18 are formed on both sides of the source region 11, and the first epitaxial layer 17 and the gate dielectric layer 18 are located above the isolation layer 122.
  • This step specifically includes the following steps.
  • a sixth semiconductor layer 17a is formed for preparing the first epitaxial layer 17.
  • the sixth semiconductor layer covers the left and right sides of the first channel, the source region 11, the second channel, and the second drain, and the upper surface of the second drain.
  • the sixth semiconductor layer may be any of silicon, germanium, germanium silicon, and a group III-V material having a doping type n-type, and the doping concentration may be undoped, lightly doped, or heavily doped.
  • the sixth semiconductor layer may form a p-n tunneling junction with the source region 11.
  • the sixth semiconductor layer can be formed by an epitaxial process.
  • a dielectric layer 18a is formed for preparing the gate dielectric layer 18.
  • the dielectric layer covers the top of the sixth semiconductor layer and is on the left and right sides.
  • the dielectric layer may be a high K dielectric material, silicon oxide, HfSiON or other oxide material.
  • the dielectric layer can be formed by epitaxy or a deposition process.
  • Step S1322 etching the sixth semiconductor layer 17a and the dielectric layer 18a to form the first epitaxial layer 17 and the gate dielectric layer 18.
  • the portion of the sixth semiconductor layer and the dielectric layer located directly above the second drain region is etched away, and only the portions where the two are located directly above the isolation layer are retained.
  • the upper end surface height of the first epitaxial layer 17 prepared is higher than the upper surface height of the source region 11
  • the upper end surface height of the gate dielectric layer 18 is equal to or higher than the upper surface height of the source region 11
  • the height of an epitaxial layer 17 is higher than the height of the upper end surface of the gate dielectric layer 18 to ensure tunneling probability.
  • the height of the upper end surface of the first epitaxial layer 17 prepared is equal to the height of the upper surface of the second trench, that is, the two are flush; the height of the upper end surface of the gate dielectric layer 18 is equal to the height of the upper surface of the source region 11.
  • Step S133 forming a gate region on a side of each of the gate dielectric layers 18 away from the source region 11, the gate region being located above the isolation layer. This step specifically includes the following steps.
  • a first sidewall 161 is formed on the isolation layer. As shown in FIG. 12, the height of the upper surface of the first sidewall 161 is equal to or lower than the height of the upper surface of the first trench 102. In this embodiment, the height of the upper surface of the first side wall 161 is equal to the height of the upper surface of the first channel 102, that is, the two are flush. The purpose of this step is to make the lower surface height of the gate regions 14, 15 equal to or lower than the lower surface height of the source region 11.
  • a gate region is formed on each of the first sidewalls 161.
  • the two gate regions 14, 15 are both L-shaped, and the two arms are respectively a first portion and a second portion.
  • the first portion is disposed corresponding to the source region 11, and the gate region is formed in the first portion.
  • the second portion extends from the first portion away from the source region.
  • the upper end surface of the first portion of the gate regions 14, 15 is flush with the upper end surface of the gate dielectric layer 18, so that in the present embodiment, the gate region of the gate regions 14, 15 and the second surface of the source region 11 have the same area. To maximize the probability of tunneling.
  • a second sidewall 162 is formed on each of the gate regions 14, 15 as shown in FIG.
  • the side wall includes a first side wall 161 and a second side wall 162.
  • the side wall is formed in two parts, so that the grid area is embedded in the side wall.
  • the material of the first side wall and the second side wall may be the same, and the material thereof may be silicon oxide, silicon nitride, high K dielectric or other insulating material.
  • the second sidewall 162 covers the gate region and the upper end surface of the gate dielectric layer to prevent the two from contacting the subsequent second drain.
  • Step S14 forming an electrode contact structure.
  • each of the gate regions 14, 15, the first drain region 12, the second drain region 13, and the source region 11 are connected with an electrode contact structure to correspondingly form the gate electrode 140.
  • 150, the first drain 120, the second drain 130, and the source 130 are formed in a sequence that can be formed in no particular order.
  • This step is a subsequent metallization process in order to form a complete vertical tunneling transistor structure.
  • FIG. 16 is an exploded perspective view of a tunneling field effect transistor according to a second preferred embodiment of the present invention.
  • the tunneling field effect transistor includes a source region 21, two drain regions 22, and two gate regions 23.
  • the two drain regions 22 are respectively disposed at opposite sides of the source region 21 along the first direction Y
  • the two gate regions 23 are respectively disposed at opposite sides of the source region 21 along the second direction X.
  • the two drain regions 22 have the same shape and structure.
  • the two drain regions 22 are symmetrically disposed with respect to the source region 21, and a channel layer 24 is disposed between each of the drain regions 22 and the source region 21, and the channel layer 24 forms a channel between the source region 21 and the drain region 22.
  • a first epitaxial layer 25 and a gate dielectric layer 26 are disposed between the two gate regions 23 and the source region 21.
  • the first epitaxial layer 25 is disposed between the source region 21 and the gate dielectric layer 26, and the tunneling type is linear tunneling.
  • a contact surface between the first epitaxial layer 25 and the source region 21 forms a tunneling surface for generating electron tunneling, and a tunneling area of the opposite point tunneling is large; and the first epitaxial layer 25 is disposed between the source region 21 and the gate region 23
  • the direction of the electric field of the electrical signal loaded in the gate region 23 is opposite to the tunneling direction of the electron, that is, the direction of the electric field of the electrical signal loaded by the gate region 23 is parallel to the tunneling direction of the electron, so that the electric field direction of the gate region 23 and the source region 21 are
  • the electron tunneling direction is on a line, and the tunneling probability is large, thereby effectively increasing the tunneling current.
  • one end of the gate region 23 in the third direction Z extends toward the other gate region to form a gate connection portion 232.
  • the connection portion is located on the side of the source region 21 in a third direction, and the third direction Z is perpendicular to The first direction Y and the second direction X; the two gate regions 23 are connected by the gate connection portion 232 and form a first groove 231, so that the two gate regions 23 can be integrated, and the two gate regions 23 can be integrally formed, which is convenient for two.
  • the gate region 23 is formed at one time.
  • One end of the gate dielectric layer 26 in the third direction Z extends toward the other gate dielectric layer 26 to form a dielectric connection portion 262.
  • the two gate dielectric layers 26 are connected through the dielectric connection portion 262 and form a second trench 261 so that the two gates
  • the dielectric layer 26 can also be integrally formed.
  • One end of the first epitaxial layer 25 in the third direction Z extends toward the other first epitaxial layer 25 to form an epitaxial connection portion 252, and the two first epitaxial layers 25 are connected by the epitaxial connection portion 252 and form a third trench 251;
  • the two first epitaxial layers 25 can also be integrally formed.
  • the dielectric connecting portion 262, the epitaxial connecting portion 252 and the gate connecting portion 232 are located on the same side of the source region 21 in the third direction Z; the dielectric connecting portion 262 is located between the gate connecting portion 232 and the epitaxial connecting portion 252, and the dielectric connecting portion 262 will
  • the gate connection portion 232 is isolated from the epitaxial connection portion 252; the epitaxial connection portion 252 is located between the gate connection portion 232 and the source region 21, and a pn tunnel junction is formed between the epitaxial connection portion 252 and the source region 21.
  • the two gate dielectric layers 26 are embedded in the first trenches 231, the two first epitaxial layers 25 are embedded in the second trenches 261, and the source regions 21 are embedded in the third trenches 251.
  • the overlap region between the gate region 23 and the source region 21 can be further increased by the gate connection portion 232, and the tunnel surface can be formed by using the outer surface of the source region 21 on the side of the third direction Z to increase the tunneling area and improve the tunnel. Wear current.
  • the structure is simple, and the preparation of the gate region 23, the first epitaxial layer 25 and the gate dielectric layer 26 is facilitated.
  • the source region 21 is in the shape of a square to facilitate processing of the source region 21.
  • the size of the gate region 23 is larger than the size of the source region 21 such that the two gate regions 23 completely cover the three outer surfaces of the source region 21 to make full use of the tunneling of the outer surface of the source region 21.
  • the tunneling field effect transistor further includes a substrate 29, and the substrate 29 and the gate connection portion 232 are respectively disposed at opposite sides of the source region 21 in the third direction Z.
  • the total size of the two drain regions 22, the channel layer 24 and the source region 21 is equal to or smaller than the size of the substrate 29; in the second direction X, the two gate regions 23, the gate dielectric layer 26, The overall size of an epitaxial layer 25 and source region 21 is equal to or smaller than the size of the substrate 29.
  • the substrate 29 is made to support the entire tunneling field effect transistor, and the preparation of the source region 21, the gate region 23, and the drain region 22 is facilitated.
  • the tunneling field effect transistor further includes an electrode contact structure (not shown), and each of the gate region, the drain region, and the source region and the upper portion are respectively connected with an electrode contact structure to respectively form a gate, a drain and The source is such that electrical connection of the tunneling field effect transistor to other components is achieved.
  • the present invention also provides a method for fabricating a tunneling field effect transistor of the second preferred embodiment, such as Figure 16 is a flow chart of the preparation method.
  • the method of fabricating the tunneling field effect transistor includes the following steps.
  • a substrate 29 is provided.
  • the material of the substrate is silicon.
  • the substrate may have a square shape.
  • the material of the substrate 29 may be silicon, germanium, SOI (Silicon-On-Insulator, silicon on the insulating substrate 29), or GeOI (Silicon-On-Insulator, germanium on the insulating substrate 29). )Wait.
  • Step S22 forming a drain region and a source region on the substrate, the drain region is two, and the two drain regions are respectively disposed at opposite sides of the source region in the second direction, and between the source region and the two drain regions.
  • a channel layer is provided, and the channel layer forms a channel between the source region and the drain region. This step may specifically include the following sub-steps.
  • Step S221 forming a semiconductor strip 291 above the substrate 29, the length direction of which is the first direction Y, and the semiconductor strip is located at the middle of the substrate in the second direction X.
  • This step further includes the following steps.
  • Step S2212 as shown in FIG. 19, forming a first hard mask layer 200a on the substrate 29, and etching the first hard mask layer 200a, leaving only the intermediate portion in the second direction X, The two directions are perpendicular to the first direction.
  • the first hard mask layer can be formed by a deposition process.
  • Step S2213 as shown in FIG. 20, etching the substrate 29 with the first hard mask layer as a mask, and forming a semiconductor strip 291 on the substrate 29, the semiconductor strip being located in the middle of the second direction X of the substrate 29. . Since the semiconductor strip 291 is formed on the substrate 29, in the present embodiment, the third direction Z is vertical.
  • step S2214 the remaining first hard mask layer is removed.
  • the semiconductor strip 291 can be prepared by the above steps.
  • the semiconductor strip can also be formed by other means, for example, by fin formation in a FinFET (Fin Field-Effect Transistor) device.
  • the method is to form a semiconductor strip.
  • Step S222 forming a source region 21 in a middle portion of the semiconductor strip in the first direction Y. This step further includes the following steps.
  • Step S2221 as shown in FIG. 21, a second hard mask layer 200b is formed on the semiconductor strip 291, the intermediate portion of the second hard mask layer in the first direction Y is etched, and the semiconductor strips at the portion are exposed.
  • the second hard mask layer can be formed by deposition.
  • step S2222 as shown in FIG. 22, with the second hard mask layer 200b as a mask, the source region 21 is formed by ion implantation in the middle portion of the semiconductor strip 291 in the first direction Y.
  • P++ ion implantation is performed to form a P-type heavily doped source region 21.
  • step S2223 the remaining second hard mask layer 200b is removed.
  • the source region 21 can be formed by the step S222.
  • the source region 21 can be formed by forming a groove in the middle portion of the first direction Y of the semiconductor strip and depositing in the groove. A source region 21 is formed.
  • Step S223 forming a drain region 22 at opposite ends of the semiconductor strip in the first direction Y, and a portion of the semiconductor strip between the drain region 22 and the source region 21 is formed with a channel layer.
  • This step further includes the following steps.
  • Step S2231 as shown in FIG. 23, forming a third hard mask layer on the semiconductor strip, and etching a portion of the third hard mask layer at both ends in the first direction Y; and in the first direction Y, the remaining The size of the third hard mask layer is larger than the size of the source region 21.
  • the third hard mask layer can be formed by deposition.
  • the drain region 22 is formed by ion implantation at both ends of the semiconductor strip in the first direction Y with the third hard mask layer as a mask.
  • N++ ion implantation is performed to form an N-type heavily doped drain region 22.
  • Step S2233 removes the remaining third hard mask layer.
  • drain regions 22 can be formed, and the source region 21 has the drain region 22 at both sides in the first direction Y, and the portion of the semiconductor strip where no ion implantation is performed is located in the source region 21 and the drain region.
  • a channel layer is formed between portions of the regions 22.
  • the drain region 22 may be formed by forming a recess in both ends of the first direction Y of the semiconductor, and depositing a drain region 22 in the recess.
  • the source region is first formed to form a drain region.
  • the drain region may be formed first, and then the source region may be formed, that is, the order of step S222 and step S223 may be interchanged.
  • Step S23 as shown in FIG. 26 and FIG. 27, a first epitaxial layer 25, a gate dielectric layer 26, and a gate region 23 are formed.
  • the source region 21 is formed with a gate region 23 on both sides in the second direction X.
  • the epitaxial layer 25 and the gate dielectric layer 26 are formed between the gate region 23 and the source region 21, and a side of the gate dielectric layer 26 remote from the first epitaxial layer 25 is connected to the gate region 23.
  • the first epitaxial layer 25, the gate dielectric layer 26, and the gate region 23 are sequentially stacked on the source region of the semiconductor strip, and the first epitaxial layer 25 is formed on both sides of the source region in the second direction X.
  • this step further includes the following steps.
  • Step S231 forming a semiconductor layer on the semiconductor strip, and causing the semiconductor layer to have a third trench 251 opening toward the source region 21, and the source region is located in the third trench 251.
  • a semiconductor layer is used to prepare the first epitaxial layer 25. Specifically, both ends of the semiconductor layer in the first direction Y are etched to prepare two first epitaxial layers 25 and their epitaxial junctions 252. In the first direction, there is a gap between the end of the first epitaxial layer and the drain region 22, and the size of the first epitaxial layer 25 is greater than or equal to the size of the source region 21.
  • the doping type of the semiconductor layer is n-type, which may be undoped, lightly doped, or heavily doped.
  • the material of the first semiconductor layer may be any one of silicon, germanium, germanium silicon, a group III-V material, or a group III-V compound.
  • the semiconductor layer can be formed by an epitaxial process.
  • Step S232 forming a dielectric layer on the first epitaxial layer 25, and causing the dielectric layer to have a second trench 261 having an opening toward the source region 21, and the first epitaxial layer 25 is located in the second trench 261.
  • the dielectric layer is used to form a dual gate dielectric layer 26 and its dielectric connection 261.
  • the dielectric layer can be formed by a deposition process.
  • the dielectric layer can be a high K dielectric material, silicon oxide, HfSiON, or other oxide material.
  • the dielectric layer is etched at both ends in the first direction Y to form a gate dielectric layer 26, and in the first direction Y, the gate dielectric layer 26 and the first epitaxial layer 25 are the same size.
  • Step S233 covering the gate region material on the gate dielectric layer 26, and causing the gate region material to have a first trench 233 opening toward the source region 21, and the gate dielectric layer 26 is located in the first trench 233.
  • Both ends of the gate region material in the first direction Y are etched to form two gate regions 23 and their gate connections 231.
  • the gate region 23 has the same size as the gate dielectric layer 26 and the first epitaxial layer 25.
  • the gate material can be metal or polysilicon.
  • the gate region material may be overlaid on the gate dielectric layer 26 by a deposition process.
  • Forming the first epitaxial layer 25, the gate dielectric layer 26, and the gate region 23 can be prepared by step S23.
  • the semiconductor layer, the dielectric layer and the gate region material are sequentially formed on the semiconductor strip, and the semiconductor layer has a third trench 251, the semiconductor strip is located in the third trench 251, and the dielectric layer has a first a second trench 261, the semiconductor layer is located in the second trench 261, the gate region material has a first trench 233, the dielectric layer is located in the first trench 233, in the first region of the gate region material, the dielectric layer, and the semiconductor layer Both ends of Y are simultaneously etched to form the gate region 23, the gate dielectric layer 26, and the first epitaxial layer 25 in one time, thereby simplifying the process and facilitating the preparation.
  • step S24 an electrode contact structure is formed, and each of the drain region, the source region, and the gate region is connected with an electrode contact structure to form a drain, a source, and a gate correspondingly.
  • the electrode contact structure can be formed by a metal contact process.
  • the deposition process may be by low pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD), and the epitaxial process may be an MBE epitaxial process.
  • the material of the hard mask layer may be any one of silicon oxide, silicon nitride, and silicon oxynitride materials.
  • FIG. 28 is a cross-sectional view showing a tunneling field effect transistor according to a third preferred embodiment of the present invention.
  • the overall structure of the third embodiment is substantially the same as that of the first embodiment, and only differences will be described herein, and other parts will not be described again.
  • the first epitaxial layer 38 has the same size as the source region 31 in the first direction; and the overall size and channel of the two first epitaxial layers 38 and the source region 31 in the second direction.
  • the layers 303 are the same in size, and the two first epitaxial layers 38 and the source regions 21 are integrally aligned with the channel layer 303, so that the two first epitaxial layers 38 are located between the two channel layers 303, so that Reduce the size of the entire device in the second direction.
  • the first drain 320 connected to the first drain region 32 is disposed on a surface of the first drain region 32 away from the source region 31, thereby facilitating fabrication of the first drain 320.
  • FIG. 29 is a cross-sectional view showing a tunneling field effect transistor according to a fourth preferred embodiment of the present invention.
  • the overall structure of the fourth embodiment is substantially the same as that of the third embodiment, and only differences will be described herein, and other parts will not be described again.
  • the second epitaxial layer 49 is formed between the first epitaxial layer 48 and the source region 41.
  • the first epitaxial layer 48 is opposite to the doping type of the second epitaxial layer 49, the doping type of the second epitaxial layer 49 is the same as the doping type of the source region 41, and the doping of the second epitaxial layer 49 is The concentration is greater than the doping concentration of the source region 41. In this way, a very steep concentration gradient can be formed on the source region 41, that is, a steep p-n tunneling junction is formed between the source region 41 and the first epitaxial layer 48, thereby increasing the tunneling probability and increasing the tunneling current.
  • a second epitaxial layer is first formed on the source region, and then the first epitaxial layer is formed.
  • a second epitaxial layer may be disposed between the first epitaxial layer and the source region, and the source region and the first epitaxial layer A steep p-n tunneling junction is formed to increase the tunneling probability and increase the tunneling current.

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Abstract

一种隧穿场效应晶体管，源区（11）、两个漏区（12，13）及两个栅区（14，15）；两个漏区沿第一方向（Y）分别设置于源区相对的两侧处，两个栅区沿第二方向（X）分别设置于源区相对的两侧处，源区与两栅区之间均设有第一外延层（17）及栅介质层（18）；第一外延层与源区形成p-n隧穿结；两漏区及两栅区包围在源区周围，可使得源区完全处于两栅区的控制下，源区与栅区有重叠的区域内的载流电子都会受到栅区电场的作用而发生隧穿；第一外延层设置在源区与栅介质层之间，其隧穿类型为线性隧穿，隧穿面积大，栅区电场方向和源区的电子隧穿方向处于一条线上，隧穿几率大，从而有效提高隧穿电流。另，还提供了上述隧穿场效应晶体管的制备方法。

Description

隧穿场效应晶体管及其制备方法 技术领域
本发明涉及一种隧穿场效应晶体管及其制备方法。
背景技术
自第一块集成电路诞生以来，集成电路技术一直沿着“摩尔定理”的轨迹发展，目前半导体晶体管的尺寸已经做到28nm、22nm，而且晶体管尺寸会不断减小，需求更低的供电电压和阈值电压，但传统的MOS结构已经达到了极限，低阈值电压的产生越来越困难。这是因为阈值电压降低，开关比(Ion/Ioff，其中Ion为开态电流，Ioff为关态电流，栅极电压大于阈值电压得到Ion，栅极电压小于阈值电压得到Ioff)也要降低，会导致较长的开关时间。
同时由于传统MOSFET的亚阈值摆幅斜率SS受到热电势kT/q的限制而无法随着器件尺寸的缩小而同步缩小，使得器件泄露电流增大，整个芯片的能耗不断上升，芯片功耗密度急剧增大，严重阻碍了芯片在系统集成中的应用。为了适应集成电路的发展趋势，隧穿场效应晶体管(TFET,tunneling field-effect transistor)被提出。隧穿场效应晶体管(TFET)本质上为栅控制的p-i-n二极管，其源区和漏区的掺杂类型相反。对于N型TFET来说，源区为P型重掺杂，漏区为N型重掺杂；对于P型TFET来说，源区为N型重掺杂，漏区为P型重掺杂。源区和漏区掺杂类型不同导致TFET形成了不同于MOSFET的工作机制，即载流子量子隧穿机制，也可以称为带带隧穿。对于N型TFET来说，源区导带底的电子在栅电场作用下隧穿到漏区价带中，形成隧穿电流，在漏极电压的作用下隧穿电子流向漏区形成漏极电流。由于与MOSFET工作机制不同，所以TFET不受到kT/q限制，其亚阈值摆幅SS<60mV/dec，可以降低器件静态泄露电流。
目前TFET的工作时的载流子的隧穿方向与栅电场不在同一个方向上，即点隧穿机制。因此，现有技术中，采用点隧穿机制导致载流子隧穿几率较低，使得TFET存在隧穿电流小的缺点。同时，源区与栅区之间的重叠区域有限，使得隧穿面积较小，而隧穿电流密度与隧穿面积以及隧穿几率成正比，所以， 导致较低的隧穿电流。
发明内容
本发明提供一种隧穿场效应晶体管及其制备方法，能够增加隧穿面积，有效提高隧穿电流。
一方面，提供了所述隧穿场效应晶体管包括源区、两个漏区及两个栅区；
两个所述漏区沿第一方向分别设置于所述源区相对的两侧处，所述源区与两所述漏区之间均设有沟道层，所述沟道层形成所述源区与所述漏区之间的沟道；
两个所述栅区沿第二方向分别设置于所述源区相对的两侧处，所述第二方向垂直所述第一方向；所述源区与两所述栅区之间均设有第一外延层及栅介质层；所述第一外延层设置在所述源区与所述栅介质层之间，所述第一外延层与所述源区形成p-n隧穿结；所述栅介质层上远离所述第一外延层的一面与所述栅区连接，所述栅介质层用于将所述第一外延层与所述栅区隔离。
在第一种可能的实现方式中，所述第一方向为相对所述源区的上下方向，所述第二方向为相对所述源区的左右方向；
两所述漏区包括第一漏区和第二漏区；所述第一漏区位于所述源区的正下方，所述第二漏区位于所述源区的正上方；
在所述第二方向上，两所述栅区及所述源区的总体尺寸等于或小于所述第一漏区的尺寸，所述源区位于所述第一漏区中间位置的正上方，两所述栅区分别设置于所述第一漏区两端处的正上方。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述沟道层包括第一沟道层与第二沟道层，所述第一沟道层设置在所述源区与第一漏区之间，所述第二沟道层设置在所述源区与所述第二漏区之间；所述第一沟道层、所述源区、所述第二沟道层及所述第二漏区在所述第二方向上的尺寸相同，且在所述第一方向上对齐设置。
结合第一种可能的实现方式，在第三种可能的实现方式中，所述第一漏区上与所述源区相对应的位置处向上凸起形成凸台。
结合第一种可能的实现方式，在第四种可能的实现方式中，两所述栅区 的形状结构相同，且相对所述源区对称设置。
结合第四种可能的实现方式，在第五种可能的实现方式中，所述栅区为L形，其两支臂分别为第一部分及第二部分，所述第一部分与所述源极相对设置，所述第二部分自所述第一部分的底端朝远离所述源极的方向延伸。
结合第五种可能的实现方式，在第六种可能的实现方式中，两所述栅区与所述第一漏区之间均设有隔离层，所述隔离层将所述栅区与所述第一漏区隔离。
在第七种可能的实现方式中，所述栅区在第三方向上的一端朝另一栅区延伸形成有栅连接部，所述连接部在第三方向上位于所述源区的一侧，所述第三方向同时垂直于所述第一方向及第二方向；两所述栅区通过所述栅连接部相连并形成一第一槽；
所述栅介质层在第三方向上的一端朝另一栅介质层延伸形成介质连接部，两所述栅介质层通过所述介质连接部相连并形成一第二槽；
所述第一外延层在第三方向上的一端朝另一第一外延层延伸形成外延连接部，两所述第一外延层通过所述外延连接部相连并形成一第三槽；
所述介质连接部、所述外延连接部与所述栅连接部在第三方向上位于所述源区的同一侧；所述介质连接部位于所述栅连接部与所述外延连接部之间，所述介质连接部将所述栅连接部与所述外延连接部隔离；所述外延连接部位于所述栅连接部与所述源区之间，所述外延连接部与所述源区之间形成p-n隧穿结；
两所述栅介质层嵌入在所述第一槽中，两所述第一外延层嵌入在所述第二槽中，所述源区嵌入在所述第三槽中。
结合第七种可能的实现方式，在第八种可能的实现方式中，两个所述漏区的形状结构相同；两个所述漏区相对所述源区对称设置。
结合第七种可能的实现方式，在第九种可能的实现方式中，所述隧穿场效应晶体管还包括衬底，所述衬底与所述栅连接部在所述第三方向上分别设置于所述源区相对的两侧处；
在第一方向上，两所述漏区、所述沟道层及所述源区的总体尺寸等于或小于所述衬底的尺寸；在第二方向上，两所述栅区、所述栅介质层、所述第 一外延层及所述源区的总体尺寸等于或小于所述衬底的尺寸。
结合前述任一种实现方式，在第十种可能的实现方式中，所述第一外延层与所述源区之间形成有第二外延层；所述第一外延层与所述第二外延层的掺杂类型相反，所述第二外延层的掺杂类型与所述源区的掺杂类型相同，所述第二外延层的掺杂浓度大于所述源区的掺杂浓度，以在所述第一外延层与所述源区之间形成陡峭的p-n隧穿结。
在第十一种可能的实现方式中，隧穿场效应晶体管还包括电极接触结构，所述栅区、漏区、及源区上均分别对应连接有电极接触结构，以分别形成栅极、漏极及源极。
另一方面，提供了一种隧穿场效应晶体管的制备方法，包括以下步骤：
提供一衬底；
在所述衬底上形成漏区及源区，所述漏区为两个，两个所述漏区沿第二方向分别设置于所述源区相对的两侧处，所述源区与两所述漏区之间均设有沟道层，所述沟道层形成所述源区与所述漏区之间的沟道；
制备形成第一外延层、栅介质层及栅区，两个所述栅区沿第二方向分别设置于所述源区相对的两侧处，所述第二方向垂直所述第一方向；所述源区与两所述栅区之间均设有第一外延层及栅介质层；所述第一外延层设置在所述源区与所述栅介质层之间，所述第一外延层与所述源区形成p-n隧穿结；所述栅介质层上远离所述第一外延层的一面与所述栅区连接，所述栅介质层用于将所述第一外延层与所述栅区隔离。
在第一种可能的实现方式中，两所述漏区包括第一漏区和第二漏区；所述沟道层包括第一沟道层与第二沟道层，所述第一沟道层设置在所述源区与第一漏区之间，所述第二沟道层设置在所述源区与所述第二漏区之间；
在步骤“在所述衬底上形成漏区及源区”中包括以下步骤：
在衬底上形成第一半导体层，用以制备第一漏区；
在所述第一半导体层上形成第二半导体层，用以制备所述第一沟道层；
在所述第二半导体层上形成第三半导体层，用以制备所述源区；
在所述第三半导体层上形成第四半导体层，用以制备所述第二沟道层；
在所述第四半导体层上形成第五半导体层，用以制备所述第二漏区；
在所述第五半导体层上沉积一硬掩膜层，第一漏区的上方区域包括第一区及两个第二区，第一区位于在第二方向上位于两个第二区之间，刻蚀硬掩膜层在第二区上的部分，仅保留硬掩膜层在第一区的部分；
以所述硬掩膜层为掩膜，刻蚀所述第五半导体层、第四半导体层、第三半导体层、及第二半导体层，使该四层仅保留位于所述第一区上的部分；
移除所述硬掩膜层。
结合第一种可能的实现方式，在第二种可能的实现方式中，在步骤“以所述硬掩膜层为掩膜，刻蚀所述第五半导体层、第四半导体层、第三半导体层、及第二半导体层，使该四层仅保留位于所述第一区上的部分”之后、所述步骤“移除所述硬掩膜层”之前，还包括步骤：以硬掩膜层为掩膜，刻蚀所述第一半导体层，以使得第一半导体层在所述第二方向上的中间部位形成一凸台。
结合第一种可能的实现方式，在第三种可能的实现方式中，在所述步骤“制备形成第一外延层、栅介质层及栅区”中包括以下步骤：
在所述第一漏区上制备两隔离层，两所述隔离层沿第二方向分别设置在所述源区的两侧处；
在所述源区的两侧均形成第一外延层及栅介质层，所述第一外延层及所述栅介质层位于所述隔离层的上方；
在各所述栅介质层远离所述源区的一侧形成栅区，所述栅区位于所述隔离层上方。
在第四种可能的实现方式中，在所述步骤“在所述衬底上形成漏区及源区”中包括以下步骤：
在所述衬底上方形成一半导体条；
在所述半导体条位于所述第一方向的中部形成源区；
在所述半导体条位于所述第一方向上相对的两端处形成分别形成一漏区，所述半导体条位于所述漏区与所述源区之间的部分形成所述沟道层。
结合第三种可能的实现方式，在第四种可能的实现方式中，所述源区及所述漏区均通过离子注入工艺形成。
结合第三种可能的实现方式，在第五种可能的实现方式中，所述步骤“制 备形成第一外延层、栅介质层及栅区”中包括以下步骤：
在半导体条上形成半导体层，所述半导体条位于第二方向上的两侧处均形成有半导体层，以使得所述半导体层具有一开口朝向所述源区的第三槽，所述源区位于所述第三槽中；刻蚀所述半导体层在第一方向上的两端，以制备形成两第一外延层及其外延连接部；在第一方向上，所述第一外延层的端部与所述漏区之间存在间距，且所述第一外延层的尺寸大于或等于所述源区的尺寸；
在所述第一外延层上形成电介质层，所述第一外延层位于第二方向上的两侧处均形成有所述电介质层，以使得所述电介质层具有一开口朝向所述源区的第二槽，且所述第一外延层位于所述第二槽中；刻蚀所述电介质层在第一方向上的两端，以制备形成两栅介质层及介质连接部；在所述第一方向上，所述栅介质层与所述第一外延层二者的尺寸相同；
在所述栅介质层上覆盖栅区材料，使得所述栅区材料形成一开口朝向所述源区的第一槽，且所述栅介质层位于该所述第一槽中；刻蚀所述栅区材料在第一方向上的两端，以制备形成两栅区及其栅连接部；在第一方向上，所述栅区与栅介质层、第一外延层三者的尺寸相同。
在第六种可能的实现方式中，所述隧穿场效应晶体管的制备方法还包括步骤：形成电极接触结构，各漏区、源区、及栅区均连接有电极接触结构，以对应形成漏极、源极及栅极。
根据本发明的隧穿场效应晶体管及其制备方法，两漏区及两栅区包围在源区周围，可使得源区完全处于两栅区的控制下，源区与栅区有重叠的区域内的载流电子都会受到栅区电场的作用而发生隧穿；第一外延层设置在源区与栅介质层之间，其隧穿类型为线性隧穿，隧穿面积大，栅区电场方向和源区的电子隧穿方向处于一条线上，隧穿几率大，从而有效提高隧穿电流。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图1是本发明第一实施方式提供的隧穿场效应晶体管的剖面示意图；
图2是图1的隧穿场效应晶体管的制备方法的流程图；
图3是图1的隧穿场效应晶体管的制备方法的步骤S11对应的剖面图；
图4是图1的隧穿场效应晶体管的制备方法的步骤S12对应的剖面图；
图5是图1的隧穿场效应晶体管的制备方法的步骤S126对应的剖面图；
图6是图1的隧穿场效应晶体管的制备方法的步骤S127的流程图；
图7是图1的隧穿场效应晶体管的制备方法的步骤S129对应的剖面图；
图8是图1的隧穿场效应晶体管的制备方法的步骤S131对应的剖面图；
图9是图1的隧穿场效应晶体管的制备方法的步骤S1321对应的剖面图；
图10是图1中隧穿场效应晶体管的制备方法的步骤S1322的流程图；
图11是图1中隧穿场效应晶体管的制备方法的步骤S1323对应的剖面图；
图12是图1中隧穿场效应晶体管的制备方法的步骤S1331对应的剖面图；
图13是图1中隧穿场效应晶体管的制备方法的步骤S1332对应的剖面图；
图14是图1中隧穿场效应晶体管的制备方法的步骤S1333对应的剖面图；
图15是图1中隧穿场效应晶体管的制备方法的步骤S14对应的剖面图
图16是本发明第二实施方式提供的隧穿场效应晶体管的立体分解示意图；
图17是图16中隧穿场效应晶体管的制备方法的流程图；
图18是图16中隧穿场效应晶体管的制备方法的步骤S21对应的剖面图；
图19是图16中隧穿场效应晶体管的制备方法的步骤S2212对应的剖面图；
图20是图16中隧穿场效应晶体管的制备方法的步骤S2213对应的立体图；
图21是图16中隧穿场效应晶体管的制备方法的步骤S2221对应的剖面图；
图22是图16中隧穿场效应晶体管的制备方法的步骤S2222对应的剖面图；
图23是图16中隧穿场效应晶体管的制备方法的步骤S2231对应的剖面 图；
图24是图16中隧穿场效应晶体管的制备方法的步骤S2232对应的剖面图；
图25是图16中隧穿场效应晶体管的制备方法的步骤S2233对应的剖面图
图26、图27是图16中隧穿场效应晶体管的制备方法的步骤S23对应的两个视角的剖面图
图28是本发明第三实施方式提供的隧穿场效应晶体管的剖面图；
图29是本发明第四实施方式提供的隧穿场效应晶体管的剖面图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1及图2，为本发明第一较佳实施方式提供的隧穿场效应晶体管的剖面结构示意图。隧穿场效应晶体管包括源区11，两个漏区12、13及两个栅区14、15。本实施方式中，第一方向Y为相对源区11的上下方向，第二方向X为相对源区11的左右方向。源区11为方体状，以方便源区11的制备。两个漏区12、13包括第一漏区12和第二漏区13。第一漏区位于第一漏区12的正下方，第二漏区13位于源区11的正上方，以使得第一漏区12与第二漏区13沿第一方向Y分别设置在源区11相对的两侧处。两个栅区14、15的形状结构大致相同，两个栅区14、15沿第二方向X分别设置在源区11相对的两侧处。第一漏区12、第二漏区13、及两个栅区14、15包围在源区11周围，可使得源区11完全处于栅区的控制下，源区11与栅区14、15有重叠的区域内(如图1中虚线框所示)的载流电子都会受到栅区电场的作用而发生隧穿，从而提高隧穿电流。
本实施方式中，在第二方向X上，两栅区14、15及源区11的总体尺寸可以等于或小于第一漏区12的尺寸，源区11位于第一漏区12中间位置的正 上方，两栅区14、15分别设置于第一漏区11两端处的正上方，利用第一漏区11可以对整个隧穿场效应晶体管起到承载及支撑作用。
第一漏区12及第二漏区13二者与源区11之间均设有沟道层，即存在两个沟道层，分别为第一沟道层102和第二沟道层103。第一沟道层102设置在源区11与第一漏区12之间，以形成源区11与第一漏区12之间的沟道。第二沟道层103设置在源区11与第二漏区13之间，以形成源区11与第二漏区13之间的沟道。第一沟道层102、源区11、第二沟道层103及第二漏区13依次叠加于第一漏区上方。
第一沟道层102、源区11、第二沟道层103及第二漏区13在第二方向X上的尺寸相同，且在第一方向上对齐设置，从而便于将这四部分一次蚀刻成型，利于加工制备。进一步，第一漏区12上与源区11相对应的位置处向上凸起形成凸台121，第一沟道层102、源区11、第二沟道层103及第二漏区13均设置在所述凸台121上，从而利于位于源区11第二方向X上两侧的各部件的加工制备，方便设置隔离层122以将源区11与栅区14、15隔离。作为优选，凸台121与第一沟道层102二者在第二方向X上的尺寸相同，以便于对源区11的两侧进行时刻从而加工成型凸台121。
两栅区14、15的形状相同，且相对源区11对称设置。本实施方式中以其中栅区14为例进行具体描述。栅区为L形，其两支臂分别为第一部分141及第二部分142，第一部分141与源极相对设置，且栅区面形成于第一部分141。第二部分142自第一部分141的底端朝远离源极11的方向延伸，第二部分142连接有栅极140，利用第二部分142可便于设置栅极140。
两栅区14、15与第一漏区12之间均设有隔离层122，隔离层122将栅区14、15与第一漏区11隔离，以避免栅区与第一漏区之间电连接。
栅区14上远离源区11的一侧还设置有边墙16，栅区142及栅极140嵌入在边墙16中，利用边墙可以将栅区14与隧穿场效应晶体管外的其他部件隔离，栅极140的一端露在边墙16外，以便实现与其他部件的电连接，从而向栅区14施加电压。此处，在另外的实施方式中，栅区14也可以为平行于源区11表面的平板状，即栅区14仅包括前述第一部分141。
源区11与各栅区14、15之间均设有第一外延层17及栅介质层18。以源 区11与栅区14之间的结构为例，第一外延层17设置在源区11与栅介质层18之间，其隧穿类型为线性隧穿，第一外延层17与源区11之间的接触面形成产生电子隧穿的隧穿面，相对点隧穿的隧穿面积大；第一外延层17设置源区11与栅区14之间，在栅区14加载的电信号的电场方向与电子的隧穿方向相反，即栅区14加载的电信号的电场方向与电子的隧穿方向平行，使得栅区14电场方向和源区11的电子隧穿方向处于一条线上，隧穿几率大，从而有效提高隧穿电流。栅介质层18上远离第一外延层17的一面与栅区连接，栅介质层18可以将栅区14与第一外延层17隔离。
源区11朝向第一外延层17的表面完全与第一外延层17连接，以使第一外延层17完全遮挡于源区11的左右两侧，可以充分利用源区11的外表面积形成隧穿面，从而利于隧穿。
本实施方式中，在第一方向Y上，第一外延层17的尺寸等于第一沟道层102、源区11及第二沟道层103三者的总高度，以便于加工制备。
进一步，隧穿场效应晶体管还包括衬底19及电极接触结构，衬底19设置在第一漏极12的底部。通过衬底19可对整个隧穿场效应晶体管起到支撑作用，且方便源区11、栅区14、15等的加工制备。各栅区，漏区，及源区、上均分别对应连接有电极接触结构，以分别形成栅极，漏极及源极，从而实现隧穿场效应晶体管与其他元器件的电连接。
本实施方式中，仅图示出栅区14对应的栅极140，栅极140设置在边墙上，且连接至栅区14的第二部分142，当然在其他的实施方式中，栅极140亦可连接至栅区的第一部分141上。
源极110设置在源区11的右侧处，即源极110设置在源区上设有栅区15的一侧。为避免源极110接触到栅区15，栅区15、栅介质层18、第一外延层17上均设有相应的避空孔(图中未标示)，源极110嵌入在边墙中，且穿设避空孔，源极110的一端连接至源区11，另一端露在边墙外。源极110位于避空孔的部分与栅区15、栅介质层18及第一外延层17之间均填充有边墙材质，以避免接触。
漏极包括第一漏极120及第二漏极130，其中第一漏极120连接至第一漏区12，第二漏极130连接至第二漏区130。第一漏极120为柱状，其电连接 于漏区12，且嵌入在边墙16及绝缘层122中，以实现第一漏极120与其他部件之间的隔离，第一漏极120的右侧处位于边墙16外，以方便第一漏极120与外部实现电连接。边墙16的材质可以与绝缘层122的材质相同，可以为氮化硅等。本实施方式中，第一漏极120与源极110设置在源区11的同一侧，为避免第一漏极120与栅区15的第二部分的接触，栅区15的第二部分上可以通过刻蚀形成相应的避空结构，并在漏极120与栅区15之间填充边墙等绝缘材质，以使第一漏极120与栅区15相隔离。
连接至第二漏区13的漏极为第二漏极130，第二漏极130上设有容置槽(图中未标示)，容置槽的开口朝向源区11，第二漏区13设置在容置槽中，从而使得漏极将漏区12包围，实现二者的可靠连接。
请参阅图2，为本发明提供的第一实施方式的隧穿场效应晶体管的制备方法的流程图。隧穿场效应晶体管的制备方法包括但不限于如下步骤。
步骤S11，提供一衬底19。本实施例中，衬底的材质为硅。如图3所示，衬底可为矩形衬底。在其他实施方式中，衬底也可以为锗(Ge)或硅锗、镓砷等II-IV族、或III-V族、或IV-IV族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator,SOI)、或者绝缘衬底上的锗(Germanium on Insulator,GeOI)中的任意一种。
步骤S12，在所述衬底19上形成漏区及源区，所述漏区为两个，两个所述漏区沿第二方向分别设置于所述源区相对的两侧处，所述源区与两所述漏区之间均设有沟道层，所述沟道层形成所述源区与所述漏区之间的沟道。本实施例中，所述漏区包括第一漏区和第二漏区，沟道层包括第一沟道层与第二沟道层，第一沟道层设置在源区与第一漏区之间，第二沟道层设置在源区与第二漏区之间。该步骤S12具体可以包括以下子步骤。
步骤S121，如图4所示，在衬底19上形成第一半导体层12a，第一半导体层12a用以制备第一漏区12。第一半导体层12a可以为沉积形成的原位掺杂的N型重掺杂半导体层，其材料可以是硅材料，也可以是锗、锗硅材料、III-V族材料、或III-V族化合材料等中的任意一种。
步骤S122，在第一半导体层12a上形成第二半导体层102a，第二半导体层102a用以制备第一沟道层102。第二半导体层可以为沉积形成的本证掺杂 的半导体层，其材料可以是硅材料，也可以是锗、锗硅材料、III-V族材料、或III-V族化合材料等中的任意一种。
步骤S123，在第二半导体层102a上形成第三半导体层11a，第三半导体层11a用以制备源区11。第三半导体层可以为沉积形成的P型重掺杂的半导体层，其材料可以是硅材料，也可以是锗、锗硅材料、III-V族材料、或III-V族化合材料等中的任意一种。
步骤S124，在第三半导体层11a上形成第四半导体层103a，第四半导体层103a用以制备第二沟道层103。第三半导体层可以为沉积形成的本证掺杂的半导体层，其材料可以为是硅材料，也可以是锗、锗硅材料、III-V族材料、或III-V族化合材料等中的任意一种。
步骤S125，在第四半导体层103a上形成第五半导体层13a，用以制备第二漏区。第五半导体层可以为沉积形成的N型重掺杂的半导体层，其材料可以是硅材料，也可以是锗、锗硅材料、III-V族材料、或III-V族化合材料等中的任意一种。经过该步骤制备出的隧穿场效应晶体管的半成品结构如图4所示。
以上沉积工艺可以通过低压化学气相沉积(LPCVD)或者物理气相沉积(PVD)、或者分子束外延(MBE)等外延工艺实现，或者通过离子注入工艺实现。掺杂的N型杂质以便包括砷离子、磷离子等等，P型杂质一般包括：硼离子、氟化硼离子等等。
步骤S126，在第五半导体层上沉积一硬掩膜层100a，刻蚀硬掩膜层在第二方向上两端的部分，仅保留硬掩膜层在第二方向上中间的部分。如图5所示。硬掩膜层的制备可以通过低压化学气相沉积(LPCVD)或者物理气相沉积(PVD)实现。
步骤S127，以硬掩膜层为掩膜，刻蚀第五半导体层13a、第四半导体层103a、第三半导体层11a、及第二半导体层102a，使该四层仅保留位于硬掩膜层正下方的部分，从而形成如图6所示的结构。该硬掩膜层是为了防止刻蚀时，刻蚀液体对掩膜层下方材料的影响。通过该步骤，如图6所示，第五半导体层制备形成第二漏区13，第四半导体层制备形成第二沟道层103，第三半导体层制备形成源区11，第二半导体层制备形成第一沟道层102。
步骤S128，以硬掩膜层为掩膜，刻蚀第一半导体层12a，以使得第一半导体层在第二方向X上的中间部位形成一凸台121。此处，在另外的实施方式中，也可以不在第一半导体层的第一区A上形成凸台121，即使得第一漏区12的上表面为一平面。
步骤S129，移除硬掩膜层，移除硬掩膜层后形成的结构如图7所示。
步骤S13，制备形成第一外延层、栅介质层及栅区，两个所述栅区14、15沿第二方向分别设置于所述源区11相对的两侧处，第二方向X垂直所述第一方向Y；源区11与两栅区14、15之间均设有第一外延层17及栅介质层18。第一外延层17设置在源区11与栅介质层18之间，第一外延层17与源区11形成p-n隧穿结；栅介质层18上远离第一外延层17的一面与栅区14连接，栅介质层18用于将第一外延层17与栅区14隔离。该步骤具体可以包括以下子步骤。
步骤S131，如图8所示，在第一漏区12上的两个第二区B处分别制备一隔离层122，隔离层122用于绝缘漏区12与栅区14、15。该隔离层122可以为绝缘的硬掩膜层。在本步骤中，可以在第一漏区12及第五半导体层的整体上方沉积硬掩膜层，然后刻蚀掉位于第五半导体层上的硬掩膜层，仅保留位于第二区B上的硬掩膜层，从而制备形成隔离层。
隔离层122的上表面高度等于或低于第一沟道102的上表面高度，以保证栅区与源区11之间的对应面积。本实施方式中，隔离层的上表面高度低于第一沟道的上表面高度，且隔离层的上表面与凸台121的上表面平齐。
步骤S132，在源区11的两侧均形成第一外延层17及栅介质层18，第一外延层17及栅介质层18位于隔离层122的上方。该步骤具体包括以下步骤。
步骤S1321，形成一第六半导体层17a，用于制备第一外延层17。如图9所示，第六半导体层覆盖于第一沟道、源区11、第二沟道及第二漏极四者整体的左右两侧及第二漏极的上表面。第六半导体层可以采用硅、锗、锗硅、及III-V族材料中的任一种，其掺杂类型n型，掺杂浓度可以是未掺杂、轻掺杂或者重掺杂。该第六半导体层可以与源区11形成一个p-n隧穿结。该第六半导体层可以通过外延工艺形成。
步骤S1321，形成一电介质层18a，用于制备栅介质层18。如图10所示， 电介质层覆盖于第六半导体层的顶部及其在左右两侧。电介质层可以采用高K电介质材料、硅氧化物、HfSiON或者其他氧化物材料等。该电介质层可以通过外延或者沉积工艺形成。
步骤S1322，刻蚀第六半导体层17a及电介质层18a，以制备形成第一外延层17及栅介质层18。本步骤中刻蚀掉第六半导体层及电介质层位于第二漏区正上的部分，仅保留二者位于隔离层正上方上的部分。如图11所示，制备形成的第一外延层17的上端面高度高于源区11的上表面高度，栅介质层18的上端面高度等于或高于源区11的上表面高度，且第一外延层17的高度高于栅介质层18的上端面高度，以保证隧穿几率。本实施方式中，制备形成的第一外延层17的上端面高度等于第二沟道的上表面高度，即二者平齐；栅介质层18的上端面高度等于源区11的上表面高度。
步骤S133，在各栅介质层18远离源区11的一侧形成栅区，栅区位于所述隔离层上方。本步骤中具体包括以下步骤。
步骤S1331，在隔离层上形成第一边墙161，如图12所示，第一边墙161的上表面高度等于或低于第一沟道102的上表面高度。本实施方式中，第一边墙161的上表面高度等于第一沟道102的上表面高度，即二者平齐。该步骤的目的是为了使栅区14、15的下表面高度等于或低于源区11的下表面高度。
步骤S1332，在各第一边墙161上分别形成一栅区。如图13所示，两栅区14、15均为L形，其两支臂分别为第一部分及第二部分，第一部分与源区11对应设置，且栅区面形成于第一部分。第二部分自第一部分朝远离源区的方向延伸。栅区14、15的第一部分上端面与栅介质层18的上端面平齐，以使得本实施例中，栅区14、15的栅区面与源区11的第二表面二者面积相同，以最大化隧穿几率。
步骤S1333，在各栅区14、15上分别形成第二边墙162，如图14所示。在本实施方式中，边墙包括第一边墙161及第二边墙162，边墙分成两部分形成，可以使得栅区嵌入在边墙中。第一边墙与第二边墙的材质可以相同，其材料可以是硅氧化物、氮化硅、高K电介质或其他绝缘材料。第二边墙162覆盖在栅区及栅介质层的上端面，以避免二者对后续的第二漏极相接触。
步骤S14，形成电极接触结构，如图15所示，各栅区14、15，第一漏区12、第二漏区13，及源区11均连接有电极接触结构，以对应形成栅极140、150，第一漏极120、第二漏极130及源极130。栅极140、150，第一漏极120、第二漏极130及源极130制备形成顺序可以不分先后。
对所述栅极进行氩离子束刻蚀，在所述栅极的表面进行钴和氮化钛离子束沉淀后，进行快速退火，去除氮化钛离子束和钴离子束，然后进行沉积钝化层。此步骤为后续的金属化工艺，目的是为了形成一个完整的垂直隧穿晶体管结构。
请参阅图16，为本发明第二较佳实施方式提供的隧穿场效应晶体管的分解示意图。隧穿场效应晶体管包括源区21，两漏区22及两栅区23。两个漏区22沿第一方向Y分别设置于源区21相对的两侧处，两栅区23沿第二方向X分别设置于源区21相对的两侧处。
具体地，本实施例中，两个漏区22的形状结构相同。两个漏区22相对源区21对称设置，且各漏区22与源区21之间均设沟道层24，沟道层24形成源区21与漏区22之间的沟道。
两栅区23与源区21之间均设有第一外延层25及栅介质层26，第一外延层25设置在源区21与栅介质层26之间，其隧穿类型为线性隧穿，第一外延层25与源区21之间的接触面形成产生电子隧穿的隧穿面，相对点隧穿的隧穿面积大；第一外延层25设置源区21与栅区23之间，在栅区23加载的电信号的电场方向与电子的隧穿方向相反，即栅区23加载的电信号的电场方向与电子的隧穿方向平行，使得栅区23电场方向和源区21的电子隧穿方向处于一条线上，隧穿几率大，从而有效提高隧穿电流。栅介质层26上远离第一外延层25的一面与栅区23连接，栅介质层26可以将栅区23与第一外延层25隔离。
本实施方式中，栅区23在第三方向Z上的一端朝另一栅区延伸形成有栅连接部232，连接部在第三方向上位于源区21的一侧，第三方向Z同时垂直于第一方向Y及第二方向X；两栅区23通过栅连接部232相连并形成一第一槽231，从而可以使得两栅区23为一体式结构，两栅区23可以一体成型，方便两栅区23一次加工成型。
栅介质层26在第三方向Z上的一端朝另一栅介质层26延伸形成介质连接部262，两栅介质层26通过介质连接部262相连并形成一第二槽261，以使得两个栅介质层26也可以一体成型。
第一外延层25在第三方向Z上的一端朝另一第一外延层25延伸形成外延连接部252，两第一外延层25通过外延连接部252相连并形成一第三槽251；以使得两个第一外延层25也可以一体成型。
介质连接部262、外延连接部252与栅连接部232在第三方向Z上位于源区21的同一侧；介质连接部262位于栅连接部232与外延连接部252之间，介质连接部262将栅连接部232与外延连接部252隔离；外延连接部252位于栅连接部232与源区21之间，外延连接部252与源区21之间形成p-n隧穿结。两栅介质层26嵌入在第一槽231中，两第一外延层25嵌入在第二槽261中，源区21嵌入在第三槽251中。
利用栅连接部232可以进一步增加栅区23与源区21之间的重叠区域，充分利用源区21在第三方向Z一侧的外表面也形成隧穿面，从而增加隧穿面积，提高隧穿电流。同时该结构简单，便于栅区23、第一外延层25及栅介质层26的制备成型。
源区21为方体状，以便于源区21的加工制备。在第一方向Y上，栅区23的尺寸大于源区21的尺寸，从而使得两栅区23完全覆盖于源区21的三个外表面，以充分利用源区21的外表面发生隧穿。
隧穿场效应晶体管还包括衬底29，衬底29与栅连接部232在第三方向Z分别设置于源区21相对的两侧处。在第一方向Y上，两漏区22、沟道层24及源区21的总体尺寸等于或小于衬底29的尺寸；在第二方向X上，两栅区23、栅介质层26、第一外延层25及源区21的总体尺寸等于或小于衬底29的尺寸。以使得衬底29对整个隧穿场效应晶体管起到支撑作用，且便于源区21、栅区23、及漏区22的制备。
进一步，隧穿场效应晶体管还包括电极接触结构(图中未示出)，各栅区，漏区，及源区、上均分别对应连接有电极接触结构，以分别形成栅极，漏极及源极，从而实现隧穿场效应晶体管与其他元器件的电连接。
本发明还提供了第二较佳实施方式的隧穿场效应晶体管的制备方法，如 图16所示该制备方法的流程图。隧穿场效应晶体管的制备方法包括以下步骤。
步骤S21，提供一衬底29，本实施例中，衬底的材质为硅。如图18所示，衬底可为方体状。在其他实施方式中，衬底29的材料可以是硅、锗、SOI(Silicon-On-Insulator，绝缘衬底29上的硅)、或GeOI(Silicon-On-Insulator，绝缘衬底29上的锗)等。
步骤S22，在所述衬底上形成漏区及源区，漏区为两个，两个漏区沿第二方向分别设置于源区相对的两侧处，源区与两漏区之间均设有沟道层，沟道层形成源区与漏区之间的沟道。该步骤具体可以包括以下子步骤。
步骤S221，在所述衬底29上方形成一半导体条291，其长度方向为第一方向Y，半导体条位于衬底在第二方向X上的中部。本步骤进一步包括以下步骤。
步骤S2212，如图19所示，在所述衬底29上形成第一硬掩膜层200a，并刻蚀第一硬掩膜层200a，仅保留其在第二方向X上的中间部分，第二方向垂直于第一方向。第一硬掩膜层可通过沉积工艺形成。
步骤S2213，如图20所示，以第一硬掩膜层为掩膜，刻蚀衬底29，在衬底29上形成一半导体条291，半导体条位于衬底29第二方向X上的中部。由于半导体条291形成在衬底29之上，故，在本实施方式中，第三方向Z即为竖向。
步骤S2214，除去余下的第一硬掩膜层。
通过以上步骤可以制备形成半导体条291，当然，在其他实施方式中，也可以通过其他方式形成半导体条，例如，通过FinFET(Fin Field-Effect Transistor；鳍式场效晶体管)器件中鳍条的形成方法来形成半导体条。
步骤S222，在所述半导体条位于第一方向Y的中部形成源区21。本步骤进一步包括以下步骤。
步骤S2221，如图21所示，在半导体条291上形成第二硬掩膜层200b，刻蚀第二硬掩膜层在第一方向Y上的中间部分，并露出该部位的半导体条。第二硬掩膜层可以通过沉积方式形成。
步骤S2222，如图22所示，以第二硬掩膜层200b为掩膜，在半导体条291在第一方向Y的中间部分通过离子注入方式形成源区21。本实施例中， 进行P++离子注入，以形成P型重掺杂的源区21。
步骤S2223，去除余下的第二硬掩膜层200b。
通过步骤S222，可以制备形成源区21，当然，在其他的实施方式中，源区21的形成方式也可以是，在半导体条第一方向Y的中间部分开设凹槽，再在凹槽中沉积形成源区21。
步骤S223，在所述半导体条位于第一方向Y上相对的两端处形成分别形成一漏区22，且所述半导体条位于漏区22与源区21之间的部分形成有沟道层。本步骤进一步包括以下步骤。
步骤S2231，如图23所示，在半导体条上形成第三硬掩膜层，并刻蚀第三硬掩膜层在第一方向Y上两端的部分；且在第一方向Y上，余下的第三硬掩膜层的尺寸大于源区21的尺寸。第三硬掩膜层可以通过沉积方式形成。
步骤S2232，如图24所示，以第三硬掩膜层为掩膜，在半导体条第一方向Y上的两端处通过离子注入方式形成漏区22。本实施方式中，进行N++离子注入，形成N型重掺杂的漏区22。
步骤S2233，如图25所示，去除余下的第三硬掩膜层。
通过以上步骤S223，可以形成两个漏区22，并使得源区21在第一方向Y上的两侧处均具有漏区22，半导体条上未进行离子注入的部分即位于源区21与漏区22之间部分形成沟道层。当然，在其他的实施方式中，漏区22的形成方式也可以是，在半导体第一方向Y的两端部分开设凹槽，再在凹槽中沉积形成漏区22。
在步骤22中，先形成源区再制备形成漏区，当然在其他实施方式中，也可以是，先形成漏区，再制备形成源区，即步骤S222与步骤S223的次序可以互换。
步骤S23，如图26、图27所示，制备形成第一外延层25、栅介质层26及栅区23，源区21在第二方向X上的两侧均形成有栅区23，第一外延层25及栅介质层26形成在栅区23与源区21之间，栅介质层26上远离第一外延层25的一面与栅区23连接。该步骤中，所述半导体条的源区上依次叠加形成第一外延层25、栅介质层26及栅区23，且在源区第二方向X上的两侧均形成有第一外延层25、栅介质层26及栅区23，使得源区21在第二方向X上 相对的两侧处均设置有栅区23，第二方向X垂直于第一方向Y。进一步具体地，本步骤进一步包括以下步骤。
步骤S231，在所述半导体条上形成半导体层，并使得半导体层具有一开口朝向源区21的第三槽251，源区位于该第三槽251中。半导体层用于制备形成第一外延层25。具体地，刻蚀半导体层在第一方向Y上的两端，以制备形成两第一外延层25及其外延连接部252。在第一方向上，第一外延层的端部与漏区22之间存在间距，且第一外延层25的尺寸大于或等于源区21的尺寸。
半导体层的掺杂类型为n型，其可以是未掺杂，轻掺杂，或者重掺杂。第一半导体层的材料可以是硅、锗、锗硅、III-V族材料、或III-V族化合材料等中的任意一种。半导体层可以通过外延工艺形成。
步骤S232，在第一外延层25上形成电介质层，并使得电介质层具有一开口朝向源区21的第二槽261，且第一外延层25位于该第二槽261中。该电介质层用于制备形成两栅介质层26及其介质连接部261。电介质层可以通过沉积工艺形成。电介质层可以是高K电介质材料，硅氧化物，HfSiON，或者其他氧化物材料等。刻蚀电介质层在第一方向Y上的两端，以制备形成栅介质层26，在第一方向Y上，栅介质层26与第一外延层25二者的尺寸相同。
步骤S233，在栅介质层26上覆盖栅区材料，并使得栅区材料具有一开口朝向源区21的第一槽233，且栅介质层26位于该第一槽233中。刻蚀栅区材料在第一方向Y上的两端，以制备形成两栅区23及其栅连接部231。在第一方向Y上，栅区23与栅介质层26、第一外延层25三者的尺寸相同。栅区材料可以是金属或者多晶硅。栅区材料可以通过沉积工艺覆盖在栅介质层26上。
通过步骤S23，可以制备形成第一外延层25、栅介质层26及栅区23。此处，作为另外的实施方式，在半导体条上依次形成半导体层、电介质层及栅区材料，且使得半导体层具有一第三槽251，半导体条位于第三槽251中，电介质层具有一第二槽261，半导体层位于第二槽261中，栅区材料具有一第一槽233，电介质层位于第一槽233中，在对栅区材料、电介质层、及半导体层三者在第一方向Y上的两端同时进行刻蚀，以一次性制备形成栅区23、栅介质层26、及第一外延层25，从而简化工艺，便于制备成型。
步骤S24，形成电极接触结构，各漏区、源区、及栅区均连接有电极接触结构，以对应形成漏极、源极及栅极。电极接触结构可以通过金属接触工艺制备形成。
在本制备方法的实施方法中，沉积工艺可以通过低压化学气相沉积(LPCVD)或者物理气相沉积(PVD)，外延工艺可以为MBE外延工艺。硬掩膜层的材料可以是氧化硅、氮化硅、及氮氧化硅材料中的任意一种。
如图28所示，为本发明第三较佳实施方式提供的隧穿场效应晶体管的剖面示意图。本第三实施方式的整体结构与第一实施方式大体相同，此处仅对具有区别之处进行描述，其他部分不再赘述。
本第三实施方式中，在第一方向上，第一外延层38与源区31的尺寸相同；在第二方向上，两个第一外延层38与源区31三者整体尺寸与沟道层303的尺寸相同，且两个第一外延层38与源区21三者整体与沟道层303对齐设置，可以使得两个第一外延层38位于两个沟道层303之间，从而可以减小整个器件在第二方向上的尺寸。
连接至第一漏区32的第一漏极320设置在第一漏区32远离源区31的表面上，从而便于第一漏极320的制备成型。
如图29所示，为本发明第四较佳实施方式提供的隧穿场效应晶体管的剖面示意图。本第四实施方式的整体结构与第三实施方式大体相同，此处仅对具有区别之处进行描述，其他部分不再赘述。
本第四实施方式中，在第一外延层48与源区41之间形成有第二外延层49。第一外延层48与第二外延层49的掺杂类型相反，所述第二外延层49的掺杂类型与所述源区41的掺杂类型相同，所述第二外延层49的掺杂浓度大于所述源区41的掺杂浓度。这样可以源区41上形成一个非常陡峭的浓度梯度，即源区41与第一外延层48之间形成一个陡峭的p-n隧穿结，进而可以增大隧穿几率，提高隧穿电流。该隧穿场效应晶体管在制备过程中，在制备第一外延层之前，首先在源区上制备成型第二外延层，再制备形成第一外延层即可。
此处，在第一实施方式与第二实施方式提供的隧穿场效应晶体管中，第一外延层与源区之间均可以设置一上述第二外延层，以源区与第一外延层之 间形成一个陡峭的p-n隧穿结，增大隧穿几率，提高隧穿电流。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (20)

  1. 一种隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管包括源区、两个漏区及两个栅区；
    两个所述漏区沿第一方向分别设置于所述源区相对的两侧处，所述源区与两所述漏区之间均设有沟道层，所述沟道层形成所述源区与所述漏区之间的沟道；
    两个所述栅区沿第二方向分别设置于所述源区相对的两侧处，所述第二方向垂直所述第一方向；所述源区与两所述栅区之间均设有第一外延层及栅介质层；所述第一外延层设置在所述源区与所述栅介质层之间，所述第一外延层与所述源区形成p-n隧穿结；所述栅介质层上远离所述第一外延层的一面与所述栅区连接，所述栅介质层用于将所述第一外延层与所述栅区隔离。
  2. 如权利要求1任一项所述的隧穿场效应晶体管，其特征在于，所述第一方向为相对所述源区的上下方向，所述第二方向为相对所述源区的左右方向；
    两所述漏区包括第一漏区和第二漏区；所述第一漏区位于所述源区的正下方，所述第二漏区位于所述源区的正上方；
    在所述第二方向上，两所述栅区及所述源区的总体尺寸等于或小于所述第一漏区的尺寸，所述源区位于所述第一漏区中间位置的正上方，两所述栅区分别设置于所述第一漏区两端处的正上方。
  3. 如权利要求2所述的隧穿场效应晶体管，其特征在于，所述沟道层包括第一沟道层与第二沟道层，所述第一沟道层设置在所述源区与第一漏区之间，所述第二沟道层设置在所述源区与所述第二漏区之间；所述第一沟道层、所述源区、所述第二沟道层及所述第二漏区在所述第二方向上的尺寸相同，且在所述第一方向上对齐设置。
  4. 如权利要求2所述的隧穿场效应晶体管，其特征在于，所述第一漏区上与所述源区相对应的位置处向上凸起形成凸台。
  5. 如权利要求2所述的隧穿场效应晶体管，其特征在于，两所述栅区的形状结构相同，且相对所述源区对称设置。
  6. 如权利要求5所述的隧穿场效应晶体管，其特征在于，所述栅区为L形，其两支臂分别为第一部分及第二部分，所述第一部分与所述源极相对设置，所 述第二部分自所述第一部分的底端朝远离所述源极的方向延伸。
  7. 如权利要求6所述的隧穿场效应晶体管，其特征在于，两所述栅区与所述第一漏区之间均设有隔离层，所述隔离层将所述栅区与所述第一漏区隔离。
  8. 如权利要求1任一项所述的隧穿场效应晶体管，其特征在于，所述栅区在第三方向上的一端朝另一栅区延伸形成有栅连接部，所述连接部在第三方向上位于所述源区的一侧，所述第三方向同时垂直于所述第一方向及第二方向；两所述栅区通过所述栅连接部相连并形成一第一槽；
    所述栅介质层在第三方向上的一端朝另一栅介质层延伸形成介质连接部，两所述栅介质层通过所述介质连接部相连并形成一第二槽；
    所述第一外延层在第三方向上的一端朝另一第一外延层延伸形成外延连接部，两所述第一外延层通过所述外延连接部相连并形成一第三槽；
    所述介质连接部、所述外延连接部与所述栅连接部在第三方向上位于所述源区的同一侧；所述介质连接部位于所述栅连接部与所述外延连接部之间，所述介质连接部将所述栅连接部与所述外延连接部隔离；所述外延连接部位于所述栅连接部与所述源区之间，所述外延连接部与所述源区之间形成p-n隧穿结；
    两所述栅介质层嵌入在所述第一槽中，两所述第一外延层嵌入在所述第二槽中，所述源区嵌入在所述第三槽中。
  9. 如权利要求8所述的隧穿场效应晶体管，其特征在于，两个所述漏区的形状结构相同；两个所述漏区相对所述源区对称设置。
  10. 如权利要求8所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括衬底，所述衬底与所述栅连接部在所述第三方向上分别设置于所述源区相对的两侧处；
    在第一方向上，两所述漏区、所述沟道层及所述源区的总体尺寸等于或小于所述衬底的尺寸；在第二方向上，两所述栅区、所述栅介质层、所述第一外延层及所述源区的总体尺寸等于或小于所述衬底的尺寸。
  11. 如权利要求1-10任一项所述的隧穿场效应晶体管，其特征在于，所述第一外延层与所述源区之间形成有第二外延层；所述第一外延层与所述第二外延层的掺杂类型相反，所述第二外延层的掺杂类型与所述源区的掺杂类型相同，所述第二外延层的掺杂浓度大于所述源区的掺杂浓度，以在所述第一外延层与 所述源区之间形成陡峭的p-n隧穿结。
  12. 如权利要求1所述的隧穿场效应晶体管，其特征在于，隧穿场效应晶体管还包括电极接触结构，所述栅区、漏区、及源区上均分别对应连接有电极接触结构，以分别形成栅极、漏极及源极。
  13. 一种隧穿场效应晶体管的制备方法，其特征在于，包括以下步骤：
    提供一衬底；
    在所述衬底上形成漏区及源区，所述漏区为两个，两个所述漏区沿第二方向分别设置于所述源区相对的两侧处，所述源区与两所述漏区之间均设有沟道层，所述沟道层形成所述源区与所述漏区之间的沟道；
    制备形成第一外延层、栅介质层及栅区，两个所述栅区沿第二方向分别设置于所述源区相对的两侧处，所述第二方向垂直所述第一方向；所述源区与两所述栅区之间均设有第一外延层及栅介质层；所述第一外延层设置在所述源区与所述栅介质层之间，所述第一外延层与所述源区形成p-n隧穿结；所述栅介质层上远离所述第一外延层的一面与所述栅区连接，所述栅介质层用于将所述第一外延层与所述栅区隔离。
  14. 根据权利要求13所述的隧穿场效应晶体管的制备方法，其特征在于，两所述漏区包括第一漏区和第二漏区；所述沟道层包括第一沟道层与第二沟道层，所述第一沟道层设置在所述源区与第一漏区之间，所述第二沟道层设置在所述源区与所述第二漏区之间；
    在步骤“在所述衬底上形成漏区及源区”中包括以下步骤：
    在衬底上形成第一半导体层，用以制备第一漏区；
    在所述第一半导体层上形成第二半导体层，用以制备所述第一沟道层；
    在所述第二半导体层上形成第三半导体层，用以制备所述源区；
    在所述第三半导体层上形成第四半导体层，用以制备所述第二沟道层；
    在所述第四半导体层上形成第五半导体层，用以制备所述第二漏区；
    在所述第五半导体层上沉积一硬掩膜层，刻蚀硬掩膜层在第二方向上两端的部分，仅保留硬掩膜层在第二方向上中间的部分；
    以所述硬掩膜层为掩膜，刻蚀所述第五半导体层、第四半导体层、第三半导体层、及第二半导体层，使该四层仅保留位于所述硬掩膜层正下方的部分；
    移除所述硬掩膜层。
  15. 根据权利要求14所述的隧穿场效应晶体管的制备方法，其特征在于，在步骤“以所述硬掩膜层为掩膜，刻蚀所述第五半导体层、第四半导体层、第三半导体层、及第二半导体层，使该四层仅保留位于所述第一区上的部分”之后、所述步骤“移除所述硬掩膜层”之前，还包括步骤：以硬掩膜层为掩膜，刻蚀所述第一半导体层，以使得第一半导体层在所述第二方向上的中间部位形成一凸台。
  16. 根据权利要求14所述的隧穿场效应晶体管的制备方法，其特征在于，在所述步骤“制备形成第一外延层、栅介质层及栅区”中包括以下步骤：
    在所述第一漏区上制备两隔离层，两所述隔离层沿第二方向分别设置在所述源区的两侧处；
    在所述源区的两侧均形成第一外延层及栅介质层，所述第一外延层及所述栅介质层位于所述隔离层的上方；以及，
    在各所述栅介质层远离所述源区的一侧形成栅区，所述栅区位于所述隔离层上方。
  17. 根据权利要求13所述的隧穿场效应晶体管的制备方法，其特征在于，在所述步骤“在所述衬底上形成漏区及源区”中包括以下步骤：
    在所述衬底上方形成一半导体条；
    在所述半导体条位于所述第一方向的中部形成源区；以及，
    在所述半导体条位于所述第一方向上相对的两端处形成分别形成一漏区，所述半导体条位于所述漏区与所述源区之间的部分形成所述沟道层。
  18. 根据权利要求17所述的隧穿场效应晶体管的制备方法，其特征在于，所述源区及所述漏区均通过离子注入工艺形成。
  19. 根据权利要求17所述的隧穿场效应晶体管的制备方法，其特征在于，所述步骤“制备形成第一外延层、栅介质层及栅区”中包括以下步骤：
    在所述半导体条上形成半导体层，并使得所述半导体层具有一开口朝向所述源区的第三槽，所述源区位于所述第三槽中；刻蚀所述半导体层在第一方向上的两端，以制备形成两第一外延层及其外延连接部；在第一方向上，所述第一外延层的端部与所述漏区之间存在间距，且所述第一外延层的尺寸大于或等 于所述源区的尺寸；
    在所述第一外延层上形成电介质层，并使得所述电介质层具有一开口朝向所述源区的第二槽，且所述第一外延层位于所述第二槽中；刻蚀所述电介质层在第一方向上的两端，以制备形成两栅介质层及介质连接部；在所述第一方向上，所述栅介质层与所述第一外延层二者的尺寸相同；
    在所述栅介质层上覆盖栅区材料，使得所述栅区材料形成一开口朝向所述源区的第一槽，且所述栅介质层位于该所述第一槽中；刻蚀所述栅区材料在第一方向上的两端，以制备形成两栅区及其栅连接部；在第一方向上，所述栅区与栅介质层、第一外延层三者的尺寸相同。
  20. 根据权利要求13所述的隧穿场效应晶体管的制备方法，其特征在于，所述隧穿场效应晶体管的制备方法还包括步骤：形成电极接触结构，各漏区、源区、及栅区均连接有电极接触结构，以对应形成漏极、源极及栅极。
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