WO2017035780A1 - 隧穿场效应晶体管及其制备方法 - Google Patents

隧穿场效应晶体管及其制备方法 Download PDF

Info

Publication number
WO2017035780A1
WO2017035780A1 PCT/CN2015/088754 CN2015088754W WO2017035780A1 WO 2017035780 A1 WO2017035780 A1 WO 2017035780A1 CN 2015088754 W CN2015088754 W CN 2015088754W WO 2017035780 A1 WO2017035780 A1 WO 2017035780A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
layer
metal
gate
source
Prior art date
Application number
PCT/CN2015/088754
Other languages
English (en)
French (fr)
Inventor
杨喜超
张臣雄
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2015/088754 priority Critical patent/WO2017035780A1/zh
Priority to CN201580082816.6A priority patent/CN107924941B/zh
Publication of WO2017035780A1 publication Critical patent/WO2017035780A1/zh
Priority to US15/908,393 priority patent/US10446672B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a tunneling field effect transistor and a method of fabricating the same.
  • TFET Tanel Field-Effect Transistor
  • FIG. 1 it shows a schematic structural view of a prior art TFET.
  • the prior art TFET includes a heavily doped source region, a drain region, a channel region, a lightly doped pocket layer, a gate oxide layer, and a gate region, wherein the pocket layer is located in the gate oxide layer and the source. Between the districts. Under the action of the gate electric field, carriers in the pocket layer accumulate, eventually forming a tunneling junction with the source region, and carriers in the source region tunnel to the pocket layer to form an electric current.
  • 101 denotes a source region
  • 102 denotes a channel region
  • 103 denotes a drain region
  • 104 denotes a pocket layer
  • 105 denotes a gate oxide layer
  • 106 denotes a gate region.
  • the TFET shown in FIG. 1 forms a tunneling junction by adding a pocket layer.
  • the tunneling current of the structure is proportional to the area of the pocket layer and the carrier tunneling efficiency. If the tunneling current is to be increased, the tunneling current can be passed.
  • the area of the pocket layer is increased or the carrier tunneling efficiency is increased, but the TFET of FIG. 1 is difficult to increase the tunneling efficiency of the carrier due to technical limitations, and thus can only increase the area of the pocket layer.
  • Increasing the tunneling current, and increasing the area of the pocket layer will result in an increase in the TFET layout area, which will reduce the integration density of the TFET on the chip.
  • embodiments of the present invention provide a TFET and a method of fabricating the same.
  • the technical solution is as follows:
  • a TFET including a source region, a drain region, a channel region, a pocket layer, a gate oxide layer, and a gate region, wherein:
  • the channel region connects the source region and the drain region
  • the pocket layer and the gate oxide layer are sequentially prepared between the source region and the gate region, and the pocket layer is located on a side close to the source region;
  • a first region of the source region is prepared with a metal layer, the first region is located on a side of the source region in contact with the pocket layer, and the pocket layer at least partially covers the metal layer;
  • the pocket layer and a second region in the source region constitute a first tunneling junction of the tunneling field effect transistor, and the pocket layer and the metal layer constitute a second tunnel of the tunneling field effect transistor
  • the junction is formed, and the second area is an area of the source area other than the first area.
  • the source region and the drain region are separately prepared inside a semiconductor substrate
  • the pocket layer is prepared in a partial region of an upper surface of the semiconductor substrate
  • the gate oxide layer and the gate region are sequentially prepared on the pocket layer.
  • the pocket layer, the gate oxide layer, and the gate region are respectively provided with a partition wall;
  • a metal source electrode, a metal gate electrode and a metal drain electrode are respectively prepared at the specified positions of the source region, the gate region and the drain region, and the isolation wall is used for isolating the metal source electrode and the metal gate An electrode and the metal drain electrode.
  • the drain region is formed on a semiconductor substrate, and the channel region is prepared in a partial region on the drain region, the source region Prepared on the channel region;
  • the pocket layer completely covers both sides of the source region and the channel region
  • the gate oxide layer and the gate region are sequentially prepared outside the pocket layer.
  • the contact side of the gate region and the drain region is provided with a separation wall
  • a metal source electrode, a metal gate electrode and a metal drain electrode are respectively prepared at the specified positions of the source region, the gate region and the drain region, and the isolation wall is used for isolating the metal source electrode and the metal gate An electrode and the metal drain electrode.
  • the material of the semiconductor substrate is bulk silicon, silicon on insulator, silicon germanium, One of ruthenium and a III-V compound semiconductor;
  • the material of the pocket layer is one of silicon, germanium silicon, germanium, and a group III-V compound semiconductor.
  • the semiconductor substrate and the pocket layer are the same material or different materials.
  • the material of the gate region is one of polysilicon and metal
  • the material of the gate oxide layer is one of silicon dioxide, silicon nitride, and a high dielectric material.
  • a method of preparing a TFET comprising:
  • Preparing a gate region sequentially preparing a pocket layer and a gate oxide layer between the source region and the gate region, the pocket layer being prepared on a side close to the source region;
  • the pocket layer and the second region in the source region constitute a first tunneling junction of a tunneling field effect transistor, and the pocket layer and the metal layer constitute a second tunneling junction of the tunneling field effect transistor,
  • the second area is an area of the source area other than the first area.
  • the separately preparing the source and drain regions comprises:
  • a rapid annealing process is performed on the structure in which ion implantation is completed, and source and drain regions are generated.
  • the separately preparing the source and drain regions comprises:
  • a source region is prepared on the channel region.
  • the photolithographic technique is used to protect a predetermined drain region in the semiconductor substrate to the semiconductor Before the first ion implantation in the predetermined source region in the substrate, the method further includes:
  • a protective layer on the semiconductor substrate Preparing a protective layer on the semiconductor substrate, the protective layer for protecting the semiconductor substrate during ion implantation of the predetermined source region and the predetermined drain region;
  • Preparing a sacrificial layer of a specified shape on the protective layer the sacrificial layer being configured to form a channel region in a self-aligned manner when ion implantation is performed on the predetermined source region and the predetermined drain region, A channel region connects the source region to the drain region.
  • the preparing the metal layer in the first region of the source region comprises:
  • the metal film that has not been processed by the annealing process is removed.
  • the preparing the metal layer in the first region of the source region comprises:
  • the drain region is protected by photolithography to expose the source region, and the material in the first region of the source region is removed by an etching technique. Forming a groove;
  • the trench is filled with a metal or a metal silicide to obtain a metal layer in the first region.
  • the preparing a gate region, sequentially forming a pocket layer between the source region and the gate region includes:
  • a semiconductor film is sequentially grown as a pocket layer, a deposited growth dielectric film as a gate oxide layer, deposited polysilicon or a metal as a gate region in a partial region of the upper surface of the semiconductor substrate.
  • the preparing a gate region, sequentially forming a pocket layer between the source region and the gate region includes:
  • a semiconductor film is sequentially grown as a pocket layer, a deposition growth dielectric film as a gate oxide layer, a deposited polysilicon or a metal as a gate region on both sides of the channel region and the source region.
  • the method further includes:
  • a metal layer is deposited in a portion of the drain region.
  • the preparing a gate region, sequentially forming a pocket layer between the source region and the gate region After the gate oxide layer also includes:
  • the preparing a gate region, sequentially forming a pocket layer between the source region and the gate region After the gate oxide layer also includes:
  • a metal layer is prepared through the first region in the source region such that the second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and the pocket layer and the metal layer constitute a second tunneling junction of the TFET .
  • the TFET when the gate voltage of the TFET is greater than the threshold voltage, the TFET is turned on. At this time, in addition to the tunneling of the first tunneling junction, the tunneling of the second tunneling junction also occurs at the same time.
  • the two tunneling junctions are Schottky tunneling junctions composed of metal and semiconductor. Since the Schottky barrier has large band-control capability and can reduce the tunneling distance, reducing the tunneling distance can improve the tunneling efficiency.
  • the carrier tunneling efficiency of the TFET is relatively high compared to the TFET in which the tunneling layer and the source region only form a tunneling junction, thereby increasing the tunneling current of the TFET, thereby achieving no increase in the pocket layer.
  • the area is increased to increase the tunneling current so as not to make the layout area of the TFET too large, thereby increasing the integration density of the TFET on the chip.
  • FIG. 1 is a schematic structural diagram of a prior art TFET according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • FIG. 5 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a semiconductor substrate according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a protective layer and a sacrificial layer according to another embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a source region and a drain region according to another embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a metal layer according to another embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an initial pocket layer, an initial gate oxide layer, and an initial gate region according to another embodiment of the present invention.
  • FIG. 12 is a schematic structural view of a pocket layer, a gate oxide layer, and a gate region according to another embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a partition wall according to another embodiment of the present invention.
  • FIG. 14 is a schematic diagram of a low dielectric material and a metal source electrode, a metal gate electrode, and a metal drain electrode according to another embodiment of the present invention.
  • FIG. 15 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention.
  • 16 is a schematic diagram of a source region and a drain region according to another embodiment of the present invention.
  • 17 is a schematic diagram of an initial pocket layer, an initial gate oxide layer, and an initial gate region according to another embodiment of the present invention.
  • FIG. 18 is a schematic diagram of a partition wall according to another embodiment of the present invention.
  • FIG. 19 is a schematic view of a trench provided by another embodiment of the present invention.
  • FIG. 20 is a schematic view of a metal layer according to another embodiment of the present invention.
  • 21 is a schematic diagram of a low dielectric material, a metal source electrode, a metal gate electrode, and a metal drain electrode according to another embodiment of the present invention.
  • FIG. 22 is a flowchart of a method for fabricating a TFET according to another embodiment of the present invention.
  • Embodiments of the present invention provide a TFET including a source region, a drain region, a channel region, a pocket layer, a gate oxide layer, and a gate region. among them:
  • the channel region is connected to the source region and the drain region; the pocket layer and the gate oxide layer are sequentially prepared between the source region and the gate region, the pocket layer is located on a side close to the source region; and the first region in the source region is prepared with a metal layer.
  • the first region is located on a side of the source region in contact with the pocket layer, and the pocket layer at least partially covers the metal layer; the second region in the pocket layer and the source region constitutes a first tunneling junction of the TFET, and the pocket layer and the metal layer constitute a TFET a second tunneling junction, wherein the second region is an area of the source region other than the first region.
  • the positional relationship between the pocket layer, the gate oxide layer and the gate region is related to the positional relationship between the source region, the drain region and the channel region, and the subsequent content will combine the positional relationship of the source region, the drain region and the channel region, and the pocket layer and the gate oxide.
  • the locations of the layers and gates are detailed.
  • the tunnel junction of the TFET is composed of two parts: a pocket layer and a second region in the source region constitute a first tunneling junction of the TFET, and the pocket layer and the metal layer constitute a TFET.
  • the second tunneling junction is a Schottky tunneling junction.
  • the doping concentration of the pocket layer is less than the doping concentration of the source region.
  • the gate region is used to determine the turn-on and turn-off of the TFET.
  • the TFET is turned off, and the subthreshold characteristic of the TFET is controlled by the first tunneling junction, ie, the steep subthreshold swing of the conventional line tunneling mechanism is maintained; when the gate voltage of the TFET is greater than At the threshold voltage, the device is in an on state, except that the first tunneling junction continues to be turned on, that is, in addition to the tunneling of the first tunneling junction, the second tunneling junction is simultaneously turned on, that is, the second tunneling junction is simultaneously Tunneling occurred.
  • the Schottky barrier Since the Schottky barrier has a large band-control capability and can reduce the tunneling distance, and reducing the tunneling distance can increase the tunneling efficiency, the carrier tunneling efficiency of the TFET is relatively limited only by the pocket.
  • the TFET which forms a tunnel junction with the source region, has a relatively high tunneling efficiency and thus can improve the tunneling current of the TFET.
  • the metal layer is located near a side where the source region contacts the pocket layer, and the pocket layer constitutes a second tunneling junction, and the pocket layer and the second region of the region where the non-metal layer is located in the source region constitute a first tunneling junction. Therefore, the first tunneling junction is closer to the channel region than the second tunneling junction, which is equivalent to providing a barrier between the metal layer and the channel region, so that the leakage current of the TFET in the off state can be suppressed.
  • the material of the gate region is one of polysilicon and metal;
  • the material of the gate oxide layer is silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and high dielectric material.
  • the material of the pocket layer is one of silicon, germanium silicon, germanium, and a group III-V compound semiconductor.
  • the material of the metal layer is a metal silicide formed by a chemical reaction between the metal and the semiconductor in the source region.
  • the TFET provided by the embodiment of the present invention prepares a metal layer through the first region in the source region, so that the pocket region and the second region where the non-metal layer in the source region are located constitute the first tunneling junction of the TFET, the pocket layer and the metal layer.
  • a second tunneling junction constituting the TFET.
  • the TFET when the gate voltage of the TFET is greater than the threshold voltage, the TFET is turned on. At this time, in addition to the tunneling of the first tunneling junction, the tunneling of the second tunneling junction also occurs at the same time.
  • the two tunneling junctions are Schottky tunneling junctions composed of metal and semiconductor.
  • the Schottky barrier Since the Schottky barrier has large band-control capability and can reduce the tunneling distance, reducing the tunneling distance can improve the tunneling efficiency. Therefore, the carrier tunneling efficiency of the TFET is relatively high compared to the TFET in which the tunneling layer and the source region only form a tunneling junction, thereby increasing the tunneling current of the TFET, thereby achieving no increase in the pocket layer. The area is increased to increase the tunneling current so as not to make the layout area of the TFET too large, thereby increasing the integration density of the TFET on the chip.
  • FIG. 2 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • the corresponding embodiment of FIG. 2 specifically illustrates a positional relationship between a source region, a drain region, and a channel region, and a positional relationship between the pocket layer, the gate oxide layer, and the gate region, and a source region, a drain region, and a channel region. Positional relationship.
  • the source region 201 and the drain region 203 are separately prepared inside the semiconductor substrate 200; and the channel region 202 is prepared between the source region 201 and the drain region 203.
  • the pocket layer 204 is prepared in a partial region of the upper surface of the semiconductor substrate 200; the gate oxide layer 205 and the gate region 206 are sequentially formed on the pocket layer 204. Wherein, in this embodiment, the pocket layer 204 is in contact with a portion of the metal layer 208, that is, the pocket layer 204 partially covers the metal layer 208, and the pocket layer 204 is not in contact with the drain region 203.
  • 208 denotes a metal layer, and the area covered by 208 is the first area in the source area 201. The area other than the first area in the source area 201 is the second area.
  • the material of the semiconductor substrate 200 is one of bulk silicon, silicon-on-insulator (SOI), germanium silicon, germanium, and a group III-V compound semiconductor.
  • the material of the pocket layer 204 is one of silicon, germanium silicon, germanium, and a group III-V compound semiconductor.
  • the semiconductor substrate 200 and the pocket layer 204 are made of the same material or different materials. Since the channel region 202 is a partial region on the semiconductor substrate 200, the material of the channel region 202 is the same as that of the semiconductor substrate 200, and the channel region 202 is a conductive path of carriers from the source region to the drain region.
  • the material of the gate oxide layer 205 is one of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), and a high dielectric material.
  • a barrier wall 207 is formed on both sides of the pocket layer 204, the gate oxide layer 205, and the gate region 206.
  • the material of the partition wall 207 is an insulating material such as silicon nitride.
  • the periphery of the gate region 206 and the periphery of the spacer 207 may be filled with a low dielectric material 209 such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or the like.
  • a metal source electrode 210, a metal gate electrode 212, and a metal drain electrode 211 are respectively prepared at specified positions of the source region 201, the gate region 206, and the drain region 203.
  • the partition wall 207 is an insulating material, and therefore, it can be used to isolate the metal source electrode 210, the metal gate electrode 212, and the metal drain electrode 211, thereby avoiding a short circuit phenomenon.
  • the mechanical properties of the partition wall 207 are relatively good, and the shapes of the gate region 206, the pocket layer 204, and the gate oxide layer 205 can be fixed. Since the pocket layer 204 is disposed directly above the source region 201 and the partition wall 207 is disposed to be blocked, when the tunnel junction is formed by the pocket layer 204 and the source region 201, the tunneling direction of the TFET can be ensured from bottom to top, that is, The tunneling direction is vertical rather than horizontal.
  • the parasitic capacitance of the TFET can be prevented from being excessive.
  • the mechanical support of the metal source electrode 210, the metal gate electrode 212, and the metal drain electrode 211 can be achieved by the low dielectric material.
  • the "designated position" described in this embodiment is a position for preparing the metal source electrode 210, the metal gate electrode 212, and the metal drain electrode 211 which are set in advance.
  • the designated position may be any position where the upper surface of the source region 201 is not covered by the partition wall 207, any position on the upper surface of the gate region 206, and the upper surface of the drain region 203 is not covered by the partition wall 207.
  • the metal layer 208 in a partial region in the source region 201 may be prepared in a partial region in the drain region 203.
  • the TFET shown in FIG. 2 prepares a metal layer in a partial region in the drain region 203 in addition to the metal layer 208 in a partial region in the source region 201.
  • the material of the metal layer prepared in the drain region 203 is the same as that of the metal layer prepared in the source region 201, which can be used to lower the contact resistance.
  • FIG. 3 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • the TFET shown in FIG. 3 is a vertical nanowire device.
  • the corresponding embodiment of FIG. 3 specifically illustrates the positional relationship between the other source region, the drain region and the channel region, and the positional relationship between the pocket layer, the gate oxide layer and the gate region, and the source region, the drain region and the channel region. The positional relationship.
  • the drain region 303 is prepared on a semiconductor substrate (the semiconductor substrate is not shown in FIG. 3), and the channel region 302 is prepared in a partial region on the drain region 303.
  • a region 301 is formed on the channel region 302; the pocket layer 304 completely covers both sides of the source region 301 and the channel region 302; the gate oxide layer 305 and the gate region 306 are sequentially formed outside the pocket layer 304, and the gate oxide layer 305 is " The L" type surrounds the gate region 306.
  • the pocket layer 304 covers the metal layer 308 in the tunneling direction of the tunneling junction formed with the metal layer 308 in this embodiment.
  • the tunneling direction of the TFET is a horizontal direction, that is, a tunneling direction is a direction in which the metal layer 308 extends toward the pocket layer 304.
  • the TFET provided in the embodiment of the present invention is short gate controlled, and the gate control range is limited to the pocket layer 304 on the source region 301 and the partial pocket layer 304 on the channel region 302, so that the gate control does not affect the drain region 303.
  • the pocket layer 304 may not be in contact with the drain region 303 to reduce the possibility of leakage of the TFET, thereby improving the performance of the TFET.
  • the metal layer 308 has a sickle shape.
  • the material of the semiconductor substrate is one of bulk silicon, silicon on insulator, germanium silicon, germanium, and a group III-V compound semiconductor.
  • the material of the pocket layer 204 is one of silicon, germanium silicon, germanium, and a group III-V compound semiconductor.
  • the semiconductor substrate and the pocket layer 304 may be the same material or different materials.
  • a barrier wall 307 is formed on the contact side of the gate region 306 and the drain region 303.
  • a low dielectric material 309 is prepared on the periphery of the gate region 306, the periphery of the gate oxide layer 305, the periphery of the pocket layer 304, the periphery of the metal layer 308, and the periphery of the source region 301.
  • "peripheral" as used herein refers to a region that is not covered by other film layers.
  • a metal source electrode 310, a metal gate electrode 312, and a metal drain electrode 311 are respectively prepared at specified positions of the source region 301, the gate region 306, and the drain region 303.
  • the "designated position" described in this embodiment is a position for preparing the metal source electrode 310, the metal gate electrode 312, and the metal drain electrode 311 which are set in advance.
  • the designated location may be any location on the upper surface of the source region 301, any location on the upper surface of the gate region 306, and any location on the isolation wall 307 covered by the drain region 303.
  • a metal layer may be prepared in a partial region in the drain region 303 (in FIG. 3 The metal layer prepared in the drain region 303 is not shown).
  • the manner of the metal layer prepared in the drain region 303 and the material of the metal layer are the same as those of the metal layer prepared in the source region 301, and will not be described herein. Among them, the metal layer is prepared in the drain region 303, and the contact resistance can be lowered.
  • FIG. 3 has been described by taking the shape of the metal layer 308 as a sickle shape.
  • the shape of the metal layer 308 may be other shapes such as a rectangle or the like.
  • Figure 4 is another embodiment of the present invention A schematic structural diagram of a TFET provided by the embodiment. The difference between the TFET of FIG. 4 and the TFET of FIG. 3 is that the shape of the metal layer 408 in the source region 401 is different. In FIG. 4, the metal layer 408 has a rectangular shape. Specifically, in FIG.
  • 401 denotes a source region
  • 402 denotes a channel region
  • 403 denotes a drain region
  • 404 denotes a pocket layer
  • 405 denotes a gate oxide layer
  • 406 denotes a gate region
  • 408 denotes a metal layer
  • 409 denotes a low dielectric material.
  • 410 denotes a metal source electrode, a metal drain electrode 411, and a metal gate electrode 412. As can be seen from Figure 4, the metal layer in Figure 4 is rectangular.
  • the embodiment of the present invention further provides a method for preparing a TFET, which can be used to prepare the TFET provided by the embodiment corresponding to FIG. 2 to FIG. 4 described above in combination with the content of the embodiment corresponding to FIG. 2 to FIG.
  • FIG. 5 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention. As shown in FIG. 5, a method for fabricating a TFET according to an embodiment of the present invention includes:
  • a metal layer in a first region in the source region wherein the first region is located on a side of the source region that is in contact with the pocket layer, and the pocket layer at least partially covers the metal layer, so that the pocket layer and the second layer in the source region
  • the region constitutes a first tunneling junction of the tunneling field effect transistor, the pocket layer and the metal layer form a second tunneling junction of the tunneling field effect transistor, and the second region is a region of the source region other than the first region.
  • a method for fabricating a TFET is characterized in that a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • the Schottky barrier Since the Schottky barrier has large band-control capability and can reduce the tunneling distance, reducing the tunneling distance can improve the tunneling efficiency. Therefore, the carrier tunneling efficiency of the TFET is relatively high compared to the TFET in which the tunneling layer and the source region only form a tunneling junction, thereby increasing the tunneling current of the TFET, thereby achieving no increase in the pocket layer. The area is increased to increase the tunneling current so as not to make the layout area of the TFET too large, thereby increasing the integration density of the TFET on the chip.
  • the source and drain regions are separately prepared, including:
  • a rapid annealing process is performed on the structure in which ion implantation is completed, and source and drain regions are generated.
  • the source and drain regions are separately prepared, including:
  • a source region is prepared on the channel region.
  • the lithography is used to protect the predetermined drain region in the semiconductor substrate.
  • the method further includes:
  • a protective layer on the semiconductor substrate Preparing a protective layer on the semiconductor substrate, the protective layer for protecting the semiconductor substrate during ion implantation of the predetermined source region and the predetermined drain region;
  • the sacrificial layer is configured to form a channel region in a self-aligned manner when ion implantation is performed on the predetermined source region and the predetermined drain region, and the channel region is connected to the source region and the drain region .
  • the metal layer is prepared in the first region of the source region, including:
  • the metal film that has not been processed by the annealing process is removed.
  • the metal layer is prepared in the first region of the source region, including:
  • the drain region is protected by photolithography to expose the source region, and the material in the first region of the source region is removed by etching to form a trench;
  • the trench is filled with a metal or metal silicide to obtain a metal layer in the first region.
  • a gate region is prepared, and a pocket layer and a gate oxide layer are sequentially formed between the source region and the gate region, including:
  • a semiconductor film is sequentially grown as a pocket layer, a growth dielectric film is deposited as a gate oxide layer, deposited polysilicon or metal as a gate region in a partial region of the upper surface of the semiconductor substrate.
  • a gate region is prepared, and a pocket layer and a gate oxide layer are sequentially formed between the source region and the gate region, including:
  • a semiconductor film is sequentially grown as a pocket layer on both sides of the channel region and the source region, and a thin film of a deposition medium is deposited as a gate oxide layer, deposited polysilicon, or metal as a gate region.
  • the method further includes:
  • a metal layer is deposited in a portion of the drain region.
  • the method further includes:
  • a metal source electrode, a metal gate electrode and a metal drain electrode are respectively prepared at specified positions of the source region, the gate region and the drain region, and the isolation wall is used for isolating the metal source electrode, the metal gate electrode and the metal drain electrode.
  • the method further includes:
  • a metal source electrode, a metal gate electrode and a metal drain electrode are respectively prepared at specified positions of the source region, the gate region and the drain region, and the isolation wall is used for isolating the metal source electrode, the metal gate electrode and the metal drain electrode.
  • FIG. 6 there is shown a flow chart of a method for preparing a TFET, which can be used to prepare the TFET shown in FIG. 2 above, and the preparation method comprises the following steps:
  • a semiconductor substrate is disposed.
  • FIG. 7 a schematic diagram of a semiconductor substrate is shown.
  • the material of the semiconductor substrate has been described in the above embodiments.
  • the protective layer serves to protect the semiconductor substrate when the source and drain regions are formed by ion implantation in the semiconductor substrate.
  • the sacrificial layer is used to form a channel region in a self-aligned manner when the source region and the drain region are formed by ion implantation in a semiconductor substrate.
  • the specified shape may be a rectangle or the like.
  • ions implanted into the source and drain regions diffuse into the channel region, and the length of the sacrificial layer on the protective layer is greater than the length of the predetermined channel region. For example, if the length of the predetermined channel region is 200 nm, the length of the sacrificial layer may be 250 nm or the like.
  • a schematic of a protective layer and a sacrificial layer is shown. Referring to FIG. 8, the corresponding semiconductor region under the sacrificial layer is the region where the predetermined channel region is located.
  • a protective layer can be formed on a semiconductor substrate by deposition growth
  • a sacrificial layer can be formed on the protective layer by photolithography and etching techniques, and the shape of the sacrificial layer can be defined.
  • the material of the protective layer may be silicon dioxide or the like, and the material of the sacrificial layer may be ⁇ silicon or the like.
  • this step is an optional step for protecting the semiconductor substrate during subsequent ion implantation in the semiconductor substrate.
  • the manner of protecting the semiconductor substrate is described by taking only the generation of the protective layer and the sacrificial layer as an example. However, in the specific implementation, other methods may be used.
  • the types of ions respectively implanted are related to the type of the TFET.
  • the ions implanted in the source region are P-type ions
  • the ions implanted in the drain region are N-type ions
  • the ions implanted in the source region are N-type.
  • the ions, ions implanted in the drain region are P-type ions.
  • FIG. 9 a schematic diagram of a source and drain region is shown.
  • the left half doped region in FIG. 9 represents the source region, and the right half doped region represents the drain region.
  • Remove the exposed protective layer deposit a metal film in the first region of the source region, process the metal film by an annealing process, obtain a metal layer in the first region, and remove the metal film not processed by the annealing process.
  • the exposed protective layer refers to a protective layer not covered by the sacrificial layer. If a protective layer is prepared on the semiconductor substrate in step 602, the exposed protective layer needs to be removed prior to depositing the metal layer in the first region of the source region. Specifically, when the exposed protective layer is removed, it can be realized by an etching technique.
  • the metal constituting the metal thin film and the semiconductor in the source region are chemically reacted to form a metal silicide such as silicon nitride or the like when processed by an annealing process, and thus, the metal layer
  • a metal silicide such as silicon nitride or the like
  • a metal layer may be prepared in a partial region in the drain region.
  • a method of preparing a metal layer in a partial region in a drain region and a method in a source region The manner in which the metal layer is prepared in a region is the same. For details, refer to the manner of preparing the metal layer in the first region in the source region, which is not described in detail in the embodiment of the present invention.
  • the materials regarding the initial pocket layer, the initial gate oxide layer, and the initial gate region are the same as those of the pocket layer, the gate oxide layer, and the gate region described in the above respective embodiments, and are not described herein again.
  • FIG. 11 a schematic diagram of an initial pocket layer, an initial gate oxide layer, and an initial gate region is shown.
  • the initial pocket layer, the initial gate oxide layer, and the initial gate region completely cover the upper surface of the semiconductor substrate.
  • the pocket layer at least partially covers the metal layer, and the other end of the pocket layer does not overlap with the drain region to reduce the possibility of TFET leakage, thereby improving the performance of the TFET.
  • the photolithography and anisotropic etching techniques can be combined.
  • step 605 and step 606 are a specific implementation of sequentially growing a semiconductor film as a pocket layer, depositing a growth dielectric film as a gate oxide layer, depositing polysilicon or metal as a gate region in a partial region of the upper surface of the semiconductor substrate.
  • steps 605 and 606 an initial pocket layer, an initial gate oxide layer, and an initial gate region are prepared, and the initial pocket layer, the initial gate oxide layer, and the initial gate region are processed to obtain a pocket layer, a gate oxide layer, and a gate region.
  • An example is given.
  • the semiconductor film may be sequentially grown as a pocket directly on a portion of the upper surface of the semiconductor substrate according to the shape of the pocket layer, the gate oxide layer, and the gate region which are provided in advance.
  • the layer, the deposition growth medium film is used as a gate oxide layer, deposited polysilicon or metal as a gate region, thereby achieving the purpose of saving the process flow.
  • FIG. 12 shows a schematic structural view of a pocket layer, a gate oxide layer, and a gate region.
  • the material of the partition wall is an insulating material such as silicon nitride.
  • the isolation wall can be prepared on both sides of the pocket layer, the gate oxide layer, and the gate region by an anisotropic etching technique.
  • the partition wall is used to isolate the subsequently prepared metal source electrode, metal gate electrode and metal drain electrode to avoid short circuit.
  • the tunneling direction of the TFET is from bottom to top, that is, the tunneling direction is vertical. Non-horizontal direction.
  • FIG. 13 a schematic view of a barrier wall is shown.
  • the low dielectric material may be silicon dioxide or silicon nitride.
  • the metal source electrode, the metal gate electrode and the metal drain electrode are respectively prepared in a certain region where the source region, the gate region and the drain region are in contact with the low dielectric material. By filling the low dielectric material, the parasitic capacitance of the TFET can be prevented from being relatively large. In addition, through the low dielectric material, it can provide good mechanical support for the metal source electrode, the metal gate electrode and the metal drain electrode.
  • FIG. 14 a schematic diagram of a low dielectric material and a metal source electrode, a metal gate electrode, and a metal drain electrode is shown.
  • a method for fabricating a TFET is characterized in that a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • the Schottky barrier Since the Schottky barrier has large band-control capability and can reduce the tunneling distance, reducing the tunneling distance can improve the tunneling efficiency. Therefore, the carrier tunneling efficiency of the TFET is relatively high compared to the TFET in which the tunneling layer and the source region only form a tunneling junction, thereby increasing the tunneling current of the TFET, thereby achieving no increase in the pocket layer. The area is increased to increase the tunneling current so as not to make the layout area of the TFET too large, thereby increasing the integration density of the TFET on the chip.
  • a metal thin film is deposited on the first region in the source region, and the metal thin film is processed by an annealing process to obtain a metal layer in the first region, and the metal layer is removed.
  • the manner of preparing the metal layer in the first region in the source region is exemplified in the manner of the metal film treated by the annealing process.
  • the manner of preparing the metal layer described in step 604 is applicable to the case where the pocket layer and the semiconductor substrate are the same material or different materials. However, in another embodiment, when the pocket layer and the semiconductor substrate are of different materials, the metal layer may also be prepared in a first region of the source region in other manners. In this case, the method of preparing the TFET can be referred to the content of the corresponding embodiment of FIG.
  • FIG. 15 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention. As shown in FIG. 15, the preparation method provided by the embodiment of the present invention includes:
  • a semiconductor substrate is provided.
  • step 601. The principle of the step is the same as the principle in the step 601. For details, refer to the content in step 601, and details are not described herein again.
  • the structure of the semiconductor substrate can still be seen in FIG.
  • the principle of the step is the same as the principle in the step 602. For details, refer to the content in the step 602, and details are not described herein again.
  • the structure of the protective layer and the sacrificial layer can still be seen in FIG.
  • FIG. 16 shows a schematic diagram of a source region and a drain region.
  • all of the protective layer and the sacrificial layer can be removed by an etching technique.
  • a principle of sequentially growing a semiconductor film as an initial pocket layer, depositing a growth dielectric film as an initial gate oxide layer, depositing polysilicon or metal as an initial gate region on the upper surface of the semiconductor substrate is the same as in the above step 605 on the semiconductor substrate.
  • the principle of sequentially growing the semiconductor film as the initial pocket layer, depositing the growth dielectric film as the initial gate oxide layer, depositing polysilicon or metal as the initial gate region is the same. For details, refer to the content in the above step 605, and details are not described herein again.
  • Figure 17 a schematic diagram of an initial pocket layer, an initial gate oxide layer, and an initial gate region is shown.
  • the principle of the step is the same as the principle in the step 606.
  • step 18 The principle of the step is the same as the principle in the step 607. For details, refer to the content in step 607, and details are not described herein again. As shown in Figure 18, a schematic view of a barrier wall is shown.
  • the drain region is protected by photolithography to expose the source region, and the material in the first region of the source region is removed by etching to form a trench.
  • the groove partially overlaps the pocket layer. Specifically, it can be isotropically etched by wet etching or the like The etch technique removes material from the first region of the source region.
  • the metal layer can be prepared by the steps 1507 and 1508. Specifically, when the material of the pocket layer and the semiconductor substrate are different, when the material in the first region of the source region is removed by etching, the pocket layer is not damaged. When the pocket layer is the same material as the semiconductor substrate, when the etching is used to remove the material in the first region of the source region, the pocket layer may be removed at the same time. Therefore, the manners in steps 1507 and 1508 are applicable when the pocket layer and the semiconductor substrate are of different materials.
  • the principle of the step is the same as the principle in the step 608.
  • FIG. 21 a schematic diagram of a low dielectric material, a metal source electrode, a metal gate electrode, and a metal drain electrode is shown.
  • a method for fabricating a TFET is characterized in that a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • the Schottky barrier Since the Schottky barrier has large band-control capability and can reduce the tunneling distance, reducing the tunneling distance can improve the tunneling efficiency. Therefore, the carrier tunneling efficiency of the TFET is relatively high compared to the TFET in which the tunneling layer and the source region only form a tunneling junction, thereby increasing the tunneling current of the TFET, thereby achieving no increase in the pocket layer. The area is increased to increase the tunneling current so as not to make the layout area of the TFET too large, thereby increasing the integration density of the TFET on the chip.
  • FIG. 22 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention.
  • the preparation method provided by the embodiment can be used to prepare the TFEF provided by the embodiment corresponding to FIG. 3 or FIG. 4 above.
  • the preparation method provided by the embodiment of the present invention includes:
  • a semiconductor substrate is disposed.
  • step 601. The principle of the step is the same as the principle in the step 601. For details, refer to the content in step 601, and details are not described herein again.
  • the specific position of the designated area may be determined in combination with the process of actually preparing the TFET, which is not specifically limited in the embodiment of the present invention.
  • the drain region may be formed on the semiconductor substrate by doping a certain concentration of ions in the semiconductor to obtain a drain region or the like.
  • the manner of preparing the channel region can be combined with the existing method for preparing the channel region, which is not specifically limited in the embodiment of the present invention.
  • the source region including but not limited to, by preparing a semiconductor on the channel region and doping ions in the semiconductor layer.
  • the manner of preparing the metal layer may be the same as the principle of preparing the metal layer in the above step 604. For details, refer to the content in the above step 604.
  • a method for fabricating a TFET is characterized in that a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • a metal layer is prepared in a first region in a source region such that a second region in which the pocket layer and the non-metal layer in the source region are located constitutes a first tunneling junction of the TFET, and a pocket layer Forming a second tunneling junction of the TFET with the metal layer.
  • the carrier tunneling efficiency of the TFET is relative to only
  • the TFET which is composed of a pocket layer and a source region, has a high tunneling efficiency, thereby increasing the tunneling current of the TFET, thereby increasing the tunneling current without increasing the area of the pocket layer, thereby preventing the layout area of the TFET. Too large, thus increasing the integration density of the TFET on the chip.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

提供一种隧穿场效应晶体管（TFET）及其制备方法，属于半导体技术领域。TFET中的沟道区（202）连接源区（201）和漏区（203）；口袋层（204）和栅氧层（205）依次制备于源区与栅区（206）之间；源区中的第一区域制备有金属层（208），第一区域位于源区与口袋层相接触侧，口袋层至少部分覆盖金属层；口袋层与源区中的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结。通过源区中的第一区域制备有金属层，使得口袋层与源区中的非金属层所在的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结，相对于仅由口袋层与源区组成隧穿结的TFET，能够通过口袋层与金属层组成的隧穿结增加隧穿电流，从而实现在不增加TFET版图面积的情况下，增加TFET的隧穿电流。

Description

隧穿场效应晶体管及其制备方法 技术领域
本发明涉及半导体技术领域，特别涉及一种隧穿场效应晶体管及其制备方法。
背景技术
随着半导体技术的迅速发展，芯片中晶体管的集成密度越来越高。在此种情况下，功耗成为芯片设计的关键挑战因素。降低功耗的关键在于降低晶体管的供电电压，而降低供电电压的核心制约因素为晶体管的亚阈值摆幅，陡峭的亚阈值转变允许更大幅度供电电压的降低，从而实现晶体管功耗的大幅降低。TFET(Tunnel Field-Effect Transistor,隧穿场效应晶体管)即为一种具有陡峭的亚阈值特性的晶体管，因此，TFET在降低器件功耗方面具有非常大的发展潜力。
如图1所示，其示出了一种现有技术中的TFET的结构示意图。如图1所示，现有技术TFET中包括重掺杂的源区、漏区、沟道区、轻掺杂的口袋层、栅氧层和栅区，其中，口袋层位于栅氧层和源区之间。在栅电场的作用下，口袋层的载流子积累，最终与源区形成隧穿结，源区的载流子隧穿至口袋层，形成电流。图1中，101表示源区，102表示沟道区，103表示漏区，104表示口袋层，105表示栅氧层，106表示栅区。
在实现本发明的过程中，发明人发现现有技术至少存在以下不足：
图1所示的TFET通过增加口袋层来形成隧穿结，该种结构的隧穿电流大小与口袋层的面积和载流子隧穿效率成正比，如果要增大隧穿电流，则可以通过增大口袋层的面积或者增大载流子隧穿效率来实现，但图1中的TFET由于技术限制，载流子的隧穿效率很难提升，因而仅能通过增大口袋层的面积来增加隧穿电流，而增大口袋层的面积将导致TFET版图面积增大，该种情况将会降低芯片上TFET的集成密度。
发明内容
为了解决现有技术存在的问题，本发明实施例提供了一种TFET及其制备方法。所述技术方案如下：
第一方面，提供了一种TFET，所述TFET包括源区、漏区、沟道区、口袋层、栅氧层和栅区，其中：
所述沟道区连接所述源区和所述漏区；
所述口袋层和所述栅氧层依次制备于所述源区与所述栅区之间，所述口袋层位于靠近所述源区的一侧；
所述源区中的第一区域制备有金属层，所述第一区域位于所述源区与所述口袋层相接触的一侧，且所述口袋层至少部分覆盖所述金属层；
所述口袋层与所述源区中的第二区域组成所述隧穿场效应晶体管的第一隧穿结，所述口袋层与所述金属层组成所述隧穿场效应晶体管的第二隧穿结，所述第二区域为所述源区中除所述第一区域外的区域。
结合第一方面，在第一方面的第一种可能的实现方式中，所述源区和所述漏区分离地制备于半导体衬底内部；
所述口袋层制备于所述半导体衬底上表面的部分区域；
所述栅氧层和所述栅区依次制备于所述口袋层上。
结合第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述口袋层、所述栅氧层和所述栅区两侧制备有隔离墙；
所述源区、所述栅区和所述漏区的指定位置处分别制备有金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
结合第一方面，在第一方面的第三种可能的实现方式中，所述漏区制备于半导体衬底上，所述沟道区制备于所述漏区上的部分区域，所述源区制备于所述沟道区上；
所述口袋层完全覆盖所述源区和所述沟道区的两侧区域；
所述栅氧层和所述栅区依次制备于所述口袋层外侧。
结合第一方面的第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述栅区与所述漏区的接触侧制备有隔离墙；
所述源区、所述栅区和所述漏区的指定位置处分别制备有金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
结合第一方面的第一种或第三种可能的实现方式，在第一方面的第五种可能的实现方式中，所述半导体衬底的材料为体硅、绝缘体上的硅、锗硅、锗以及III-V族化合物半导体中的一种；
所述口袋层的材料为硅、锗硅、锗以及III-V族化合物半导体中的一种。
结合第一方面的第一种或第三种可能的实现方式，在第一方面的第六种可能的实现方式中，所述半导体衬底及所述口袋层为相同的材料或不同的材料。
结合第一方面，在第一方面的第七种可能的实现方式中，所述栅区的材料为多晶硅以及金属中的一种；
所述栅氧层的材料为二氧化硅、四氮化三硅以及高介电材料中的一种。
第二方面，还提供了一种TFET的制备方法，所述制备方法包括：
分离地制备源区和漏区，在所述源区和所述漏区之间制备沟道区；
制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层，所述口袋层制备于靠近所述源区的一侧；
在所述源区中的第一区域制备金属层，所述第一区域位于所述源区与所述口袋层相接触的一侧，且所述口袋层至少部分覆盖所述金属层，使所述口袋层与所述源区中的第二区域组成隧穿场效应晶体管的第一隧穿结，所述口袋层与所述金属层组成所述隧穿场效应晶体管的第二隧穿结，所述第二区域为所述源区中除所述第一区域外的区域。
结合第二方面，在第二方面的第一种可能的实现方式中，所述分离地制备源区和漏区，包括：
设置半导体衬底；
利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入；
利用光刻技术保护所述源区，对所述预设漏区进行第二种离子注入；
对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
结合第二方面，在第二方面的第二种可能的实现方式中，所述分离地制备源区和漏区，包括：
设置半导体衬底；
在所述半导体衬底上的指定区域制备漏区；
在所述漏区上制备沟道区；
在所述沟道区上制备源区。
结合第二方面的第一种可能的实现方式，在第二方面的第三种可能的实现方式中，所述利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入之前，还包括：
在所述半导体衬底上制备保护层，所述保护层用于在对所述预设源区和所述预设漏区进行离子注入时，保护所述半导体衬底；
在所述保护层上制备指定形状的牺牲层，所述牺牲层用于在对所述预设源区和所述预设漏区进行离子注入时，自对准地形成沟道区，所述沟道区连接所述源区与所述漏区。
结合第二方面的第一种或第二种可能的实现方式，在第二方面的第四种可能的实现方式中，所述在所述源区中的第一区域制备金属层，包括：
在所述源区中的第一区域沉积金属薄膜；
通过退火工艺对金属薄膜进行处理，得到所述第一区域中的金属层；
移除未被退火工艺处理掉的金属薄膜。
结合第二方面的第一种或第二种可能的实现方式，在第二方面的第五种可能的实现方式中，在所述源区中的第一区域制备金属层，包括：
当所述半导体衬底及所述口袋层的材料不同时，利用光刻蚀技术保护所述漏区而暴露所述源区，采用刻蚀技术移除所述源区第一区域中的材料，形成沟槽；
采用金属或者金属硅化物填充所述沟槽，得到所述第一区域中的金属层。
结合第二方面的第一种可能的实现方式，在第二方面的第六种可能的实现方式中，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层，包括：
在所述半导体衬底的上表面的部分区域依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区。
结合第二方面的第二种可能的实现方式，在第二方面的第七种可能的实现方式中，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层，包括：
在所述沟道区和所述源区两侧依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区。
结合第二方面，在第二方面的第八种可能的实现方式中，所述在所述源区中的第一区域沉积金属层之后，还包括：
在所述漏区中的部分区域沉积金属层。
结合第二方面的第一种可能的实现方式，在第二方面的第九种可能的实现方式中，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层之后，还包括：
在所述口袋层、所述栅氧层和所述栅区两侧制备隔离墙；
在所述源区、所述栅区和所述漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
结合第二方面的第二种可能的实现方式，在第二方面的第十种可能的实现方式中，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层之后，还包括：
在所述栅区与所述漏区相接触的一侧制备隔离墙；
在所述源区、所述栅区和所述漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
本发明实施例提供的技术方案的有益效果是：
通过源区中的第一区域制备有金属层，使得口袋层与源区中非金属层所在的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结。在该种结构下，当TFET的栅控电压大于阈值电压时，TFET处于开启状态，此时，除了第一隧穿结会发生隧穿外，第二隧穿结也同时发生隧穿，而第二隧穿结为金属和半导体组成的肖特基隧穿结，由于肖特基势垒具有较大的能带调控能力以及能够减小隧穿距离，而减小隧穿距离可以提高隧穿效率，因此，该TFET的载流子隧穿效率相对于仅由口袋层与源区组成隧穿结的TFET，隧穿效率比较高，因而能够提高TFET的隧穿电流，从而实现不通过增加口袋层面积来增加隧穿电流，从而不至于使TFET的版图面积过大，因而能够提高芯片上TFET的集成密度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图1是本发明一实施例提供的一种现有技术中的TFET的结构示意图；
图2是本发明另一实施例提供的一种TFET的结构示意图；
图3是本发明另一实施例提供的一种TFET的结构示意图；
图4是本发明另一实施例提供的一种TFET的结构示意图；
图5是本发明另一实施例提供的一种TFET的制备方法流程图；
图6是本发明另一实施例提供的一种TFET的制备方法流程图；
图7是本发明另一实施例提供的一种半导体衬底的示意图；
图8是本发明另一实施例提供的一种保护层和牺牲层的示意图；
图9是本发明另一实施例提供的一种源区和漏区的示意图；
图10是本发明另一实施例提供的一种金属层的示意图；
图11是本发明另一实施例提供的一种初始口袋层、初始栅氧层和初始栅区的示意图；
图12是本发明另一实施例提供的一种口袋层、栅氧层和栅区的结构示意图；
图13是本发明另一实施例提供的一种隔离墙的示意图；
图14是本发明另一实施例提供的一种低介电材料及金属源电极、金属栅电极和金属漏电极的示意图；
图15是本发明另一实施例提供的一种TFET的制备方法流程图；
图16是本发明另一实施例提供的一种源区和漏区的示意图；
图17是本发明另一实施例提供的一种初始口袋层、初始栅氧层和初始栅区的示意图；
图18是本发明另一实施例提供的一种隔离墙的示意图；
图19是本发明另一实施例提供的一种沟槽的示意图；
图20是本发明另一实施例提供的一种金属层的示意图；
图21是本发明另一实施例提供的一种低介电材料、金属源电极、金属栅电极及金属漏电极的示意图；
图22是本发明另一实施例提供的一种TFET的制备方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明 实施方式作进一步地详细描述。
本发明实施例提供了一种TFET，该TFET包括源区、漏区、沟道区、口袋层、栅氧层和栅区。其中：
沟道区连接源区和漏区；口袋层和栅氧层依次制备于源区与栅区之间，口袋层位于靠近源区的一侧；源区中的第一区域制备有金属层，该第一区域位于源区与口袋层相接触的一侧，且口袋层至少部分覆盖金属层；口袋层与源区中的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结，其中，第二区域为源区中除第一区域外的区域。
关于源区、漏区及沟道区之间的位置关系，可以有很多种，本发明实施例将在后续内容中对此进行详细说明。口袋层、栅氧层和栅区的位置关系与源区、漏区及沟道区的位置关系相关，后续内容将结合源区、漏区及沟道区的位置关系，对口袋层、栅氧层和栅区的位置进行详细阐述。
结合上述TFET的结构可得，本发明实施例提供的TFET的隧穿结由两部分组成：口袋层和源区中的第二区域组成TFET的第一隧穿结，口袋层和金属层组成TFET的第二隧穿结。其中，口袋层和金属层组成的第二隧穿结为肖特基隧穿结。口袋层的掺杂浓度小于源区的掺杂浓度。
在该TFET中，栅区用于确定TFET的开启与关闭。当TFET的栅控电压小于阈值电压时，TFET处于关闭状态，TFET的亚阈值特性由第一隧穿结控制，即保持常规线隧穿机制的陡峭亚阈值摆幅；当TFET的栅控电压大于阈值电压时，器件处于开启状态，除了第一隧穿结继续开启之外，即除了第一隧穿结会发生隧穿外，第二隧穿结也同时开启，即第二隧穿结也同时发生隧穿。由于肖特基势垒具有较大的能带调控能力以及能够减小隧穿距离，而减小隧穿距离可以增加隧穿效率，因此，该TFET的载流子隧穿效率相对于仅包括口袋层与源区组成隧穿结的TFET，隧穿效率比较高，因而能够提高TFET的隧穿电流。
另外，由于金属层位于靠近源区与口袋层相接触的一侧而与口袋层组成第二隧穿结，而口袋层与源区中非金属层所在区域的第二区域组成第一隧穿结，因此，第一隧穿结相对于第二隧穿结更靠近沟道区，相当于在金属层与沟道区之间设置了一个势垒，从而能够抑制TFET在关闭状态时的泄漏电流。
在本发明实施例中，栅区的材料为多晶硅和金属中的一种；栅氧层的材料为二氧化硅(SiO2)、氮化硅(Si3N4)以及高介电材料中的一种；口袋层的材 料为硅、锗硅、锗以及III-V族化合物半导体中的一种。金属层的材料为由金属和源区中的半导体发生化学反应而生成的金属硅化物。
本发明实施例提供的TFET，通过源区中的第一区域制备有金属层，使得口袋层与源区中非金属层所在的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结。在该种结构下，当TFET的栅控电压大于阈值电压时，TFET处于开启状态，此时，除了第一隧穿结会发生隧穿外，第二隧穿结也同时发生隧穿，而第二隧穿结为金属和半导体组成的肖特基隧穿结，由于肖特基势垒具有较大的能带调控能力以及能够减小隧穿距离，而减小隧穿距离可以提高隧穿效率，因此，该TFET的载流子隧穿效率相对于仅由口袋层与源区组成隧穿结的TFET，隧穿效率比较高，因而能够提高TFET的隧穿电流，从而实现不通过增加口袋层面积来增加隧穿电流，从而不至于使TFET的版图面积过大，因而能够提高芯片上TFET的集成密度。
结合上述实施例的内容，图2是本发明另一实施例提供的一种TFET的结构示意图。图2所对应实施例具体阐释了一种源区、漏区及沟道区之间的位置关系，以及口袋层、栅氧层和栅区的位置关系与源区、漏区及沟道区的位置关系。
如图2所示，本发明实施例提供的TFET中，源区201和漏区203分离地制备于半导体衬底200内部；源区201和漏区203之间制备有沟道区202。口袋层204制备于半导体衬底200上表面的部分区域；栅氧层205和栅区206依次制备于口袋层204上。其中，该实施例中口袋层204与部分金属层208接触，即口袋层204部分覆盖金属层208，且口袋层204不与漏区203接触。口袋层204不与漏区203接触能减小TFET漏电的可能性，从而能够提高TFET的性能。图2中，208表示金属层，208所覆盖的区域即为源区201中的第一区域。源区201中除第一区域以外的区域即为第二区域。
半导体衬底200的材料为体硅、绝缘体上的硅(SOI,Silicon-on-insulator)、锗硅、锗以及III-V族化合物半导体中的一种。口袋层204的材料为硅、锗硅、锗以及III-V族化合物半导体中的一种。其中，半导体衬底200及口袋层204为相同的材料，也可以为不同的材料。由于沟道区202为半导体衬底200上的部分区域，因此，沟道区202的材料与半导体衬底200的材料一样，沟道区202是载流子从源区到漏区的导电通路。栅氧层205的材料为二氧化硅(SiO2)、 氮化硅(Si3N4)以及高介电材料中的一种。
结合图2，在可选择的实施方案中，口袋层204、栅氧层205和栅区206两侧制备有隔离墙207。隔离墙207的材料为氮化硅等绝缘材料。栅区206外围和隔离墙207外围可以填充有低介电材料209，如二氧化硅(SiO2)、氮化硅(Si3N4)等。另外，源区201、栅区206和漏区203的指定位置处分别制备有金属源电极210、金属栅电极212和金属漏电极211。
其中，隔离墙207为绝缘材料，因此，其可以用于隔离金属源电极210、金属栅电极212及金属漏电极211，从而避免出现短路现象。另外，基于隔离墙207的材料，使得隔离墙207的机械性能比较好，能够固定栅区206、口袋层204和栅氧层205的形状。由于口袋层204设置于源区201正上方，且设置隔离墙207阻断，因此，在由口袋层204与源区201形成隧穿结时，可以确保TFET的隧穿方向为由下至上，即隧穿方向为竖直方向而非水平方向。
通过填充低介电材料209，可以防止TFET的寄生电容过大。另外，通过低介电材料，能起到对金属源电极210、金属栅电极212和金属漏电极211的机械支撑作用。
需要说明的是，该实施例中所述的“指定位置”为预先设置的用于制备金属源电极210、金属栅电极212和金属漏电极211的位置。例如，指定位置可以为源区201上表面未被隔离墙207覆盖的任意位置，栅区206上表面的任意位置，漏区203上表面未被隔离墙207覆盖的任意位置。
另外，上述内容以在源区201中的部分区域制备金属层208为例进行了说明，然而，在具体实施时，还可以在漏区203中的部分区域制备金属层213。图2示出的TFET除了在源区201中的部分区域制备了金属层208以外，在漏区203中的部分区域中也制备了金属层。其中，在漏区203中制备的金属层的材料与在源区201中制备的金属层的材料相同，其可以用于降低接触电阻。
结合上述实施例的内容，图3是本发明另一实施例提供的一种TFET的结构示意图，图3所示的TFET为一种竖直纳米线器件。图3所对应实施例具体阐释了另外一种源区、漏区及沟道区之间的位置关系，以及口袋层、栅氧层和栅区的位置关系与源区、漏区及沟道区的位置关系。
如图3所示，本发明实施例提供的TFET中，漏区303制备于半导体衬底上(图3未示出半导体衬底)，沟道区302制备于漏区303上的部分区域，源 区301制备于沟道区302上；口袋层304完全覆盖源区301和沟道区302的两侧区域；栅氧层305和栅区306依次制备于口袋层304外侧，栅氧层305呈“L”型包围栅区306。其中，该实施例中口袋层304在与金属层308形成的隧穿结的隧穿方向覆盖金属层308。结合图3，该TFET的隧穿方向为水平方向，即隧穿方向为由金属层308向口袋层304延伸的方向。
本发明实施例中提供的TFET为短栅控的，栅控范围仅限于源区301上的口袋层304和沟道区302上的部分口袋层304，从而使得栅控不影响漏区303。具体地，口袋层304可以不与漏区303接触，以减小TFET漏电的可能性，进而能够提高TFET的性能。该实施例中，金属层308的形状为镰刀形。
其中，半导体衬底的材料为体硅、绝缘体上的硅、锗硅、锗以及III-V族化合物半导体中的一种。口袋层204的材料为硅、锗硅、锗以及III-V族化合物半导体中的一种。其中，半导体衬底及口袋层304可以为相同的材料，也可以为不同的材料。
在可选择的实施例中，仍如图3所示，栅区306与漏区303的接触侧制备有隔离墙307。栅区306外围、栅氧层305外围、口袋层304外围、金属层308外围、源区301外围制备有低介电材料309。其中，此处所述的“外围”是指未被其它膜层覆盖的区域。源区301、栅区306和漏区303的指定位置处分别制备有金属源电极310、金属栅电极312和金属漏电极311。需要说明的是，该实施例中所述的“指定位置”为预先设置的用于制备金属源电极310、金属栅电极312和金属漏电极311的位置。例如，指定位置可以为源区301上表面的任意位置，栅区306上表面的任意位置，漏区303上所覆盖的隔离墙307上的任意位置。
关于隔离墙307的材料及作用、低介电材料309的材料及作用等已在图2对应的实施例中进行了描述，具体可参见上述图2中的内容，此处不再赘述。
需要说明的是，上述内容以在源区301中的部分区域制备金属层308为例进行了说明，然而，在具体实施时，还可以在漏区303中的部分区域制备金属层(图3中未示出在漏区303中制备的金属层)。在漏区303中制备的金属层的方式及金属层的材料与在源区301中制备金属层的方式及材料相同，此处将不再赘述。其中，在漏区303中制备金属层，可以降低接触电阻。
另外，图3以金属层308的形状为镰刀形为例进行了说明，然而，在具体实施时，金属层308的形状还可以为其它形状，如矩形等。图4是本发明另一 实施例提供的一种TFET的结构示意图。图4中的TFET与图3中的TFET的差别在于：源区401中金属层408的形状不同。图4中，金属层408的形状为矩形。具体地，图4中，401表示源区，402表示沟道区，403表示漏区，404表示口袋层，405表示栅氧层，406表示栅区，408表示金属层，409表示低介电材料，410表示金属源电极、金属漏电极411和金属栅电极412。由图4可得，图4中的金属层呈矩形。
结合上述图2至图4所对应的实施例的内容，本发明实施例还提供了一种TFET的制备方法，该制备方法可以用于制备上述图2至图4所对应实施例提供的TFET。图5是本发明另一实施例提供的一种TFET的制备方法的流程图。如图5所示，本发明实施例提供的TFET的制备方法包括：
501、分离地制备源区和漏区，在源区和漏区之间制备沟道区。
502、制备栅区，在源区和栅区之间依次制备口袋层和栅氧层，其中，口袋层制备于靠近源区的一侧。
503、在源区中的第一区域制备金属层，其中，第一区域位于源区与口袋层相接触的一侧，且口袋层至少部分覆盖金属层，使口袋层与源区中的第二区域组成隧穿场效应晶体管的第一隧穿结，口袋层与金属层组成隧穿场效应晶体管的第二隧穿结，第二区域为源区中除第一区域外的区域。
本发明实施例提供的TFET的制备方法，通过在源区中的第一区域制备金属层，使得口袋层与源区中非金属层所在的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结。在该种结构下，当TFET的栅控电压大于阈值电压时，TFET处于开启状态，此时，除了第一隧穿结会发生隧穿外，第二隧穿结也同时发生隧穿，而第二隧穿结为金属和半导体组成的肖特基隧穿结，由于肖特基势垒具有较大的能带调控能力以及能够减小隧穿距离，而减小隧穿距离可以提高隧穿效率，因此，该TFET的载流子隧穿效率相对于仅由口袋层与源区组成隧穿结的TFET，隧穿效率比较高，因而能够提高TFET的隧穿电流，从而实现不通过增加口袋层面积来增加隧穿电流，从而不至于使TFET的版图面积过大，因而能够提高芯片上TFET的集成密度。
在另一个实施例中，分离地制备源区和漏区，包括：
设置半导体衬底；
利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区 进行第一种离子注入；
利用光刻技术保护源区，对预设漏区进行第二种离子注入；
对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
在另一个实施例中，分离地制备源区和漏区，包括：
设置半导体衬底；
在半导体衬底上的指定区域制备漏区；
在漏区上制备沟道区；
在沟道区上制备源区。
在另一个实施例中，利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入之前，还包括：
在半导体衬底上制备保护层，该保护层用于在对预设源区和预设漏区进行离子注入时，保护半导体衬底；
在保护层上制备指定形状的牺牲层，该牺牲层用于在对预设源区和预设漏区进行离子注入时，自对准地形成沟道区，沟道区连接源区与漏区。
在另一个实施例中，在源区中的第一区域制备金属层，包括：
在源区中的第一区域沉积金属薄膜；
通过退火工艺对金属薄膜进行处理，得到第一区域中的金属层；
移除未被退火工艺处理掉的金属薄膜。
在另一个实施例中，在源区中的第一区域制备金属层，包括：
当半导体衬底及口袋层的材料不同时，利用光刻蚀技术保护漏区而暴露源区，采用刻蚀技术移除源区第一区域中的材料，形成沟槽；
采用金属或者金属硅化物填充沟槽，得到第一区域中的金属层。
在另一个实施例中，制备栅区，在源区和栅区之间依次制备口袋层和栅氧层，包括：
在半导体衬底上表面的部分区域依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区。
在另一个实施例中，制备栅区，在源区和栅区之间依次制备口袋层和栅氧层，包括：
在沟道区和源区两侧依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区。
在另一个实施例中，在源区中的第一区域沉积金属层之后，还包括：
在漏区中的部分区域沉积金属层。
在另一个实施例中，制备栅区，在源区和栅区之间依次制备口袋层和栅氧层之后，还包括：
在口袋层、栅氧层和栅区两侧制备隔离墙；
在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，该隔离墙用于隔离金属源电极、金属栅电极及金属漏电极。
在另一个实施例中，制备栅区，在源区和栅区之间依次制备口袋层和栅氧层之后，还包括：
在栅区与漏区相接触的一侧制备隔离墙；
在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，该隔离墙用于隔离金属源电极、金属栅电极及金属漏电极。
需要说明的是，上述所有可选技术方案，可以采用任意结合形成本发明的可选实施例，在此不再一一赘述。
结合上述实施例的内容。为了便于理解，本发明实施例以制备图2所示的TFET为例，对本发明实施例提供的TFET的制备方法进行详细说明。如图6所示，其示出了一种TFET的制备方法流程图，该制备方法可以用于制备上述图2所示的TFET，该制备方法包括以下步骤：
601、设置半导体衬底。
如图7所示，其示出了一种半导体衬底的示意图。该半导体衬底的材料已在上述各个实施例中进行了说明，具体可参见上述各个实施例中的内容，此处不再赘述。
602、在半导体衬底上制备保护层，在保护层上制备指定形状的牺牲层。
保护层用于在半导体衬底中通过离子注入的方式形成源区和漏区时，保护半导体衬底。牺牲层用于在半导体衬底中通过离子注入的方式形成源区和漏区时，自对准地形成沟道区。其中，指定形状可以为矩形等。需要说明的是，为了防止后续离子注入时，注入源区和漏区的离子扩散至沟道区中，牺牲层在保护层上的长度大于预设沟道区的长度。例如，预设沟道区的长度为200纳米，则牺牲层的长度可以为250纳米等。如图8所示，其示出了一种保护层和牺牲层的示意图。结合图8，牺牲层下面对应的半导体区域为预设沟道区所在的区域。
具体地，关于制备保护层和牺牲层的方式，可以有很多种。例如，可以通过沉积生长的方式在半导体衬底上制备保护层，可以通过光刻和刻蚀技术在保护层上制备牺牲层，并定义牺牲层的形状。其中，保护层的材料可以为二氧化硅等，牺牲层的材料可以为α硅等。
需要说明的是，该步骤为可选步骤，用于在后续在半导体衬底中进行离子注入时保护半导体衬底。当然，此处仅以生成保护层和牺牲层为例对保护半导体衬底的方式进行了说明，然而，在具体实施时，也可以采用其它方式实现。
603、利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入；利用光刻技术保护源区，对预设漏区进行第二种离子注入；对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
在进行第一种离子注入和第二种离子注入时，分别注入的离子的类型与TFET的类型有关。例如，当TFET是N型时，在源区中注入的离子为P型离子，在漏区中注入的离子为N型离子；当TFET是P型时，在源区中注入的离子为N型离子，在漏区中注入的离子为P型离子。
如图9所示，其示出了一种源区和漏区的示意图。图9中的左半边掺杂区域表示源区，右半边掺杂区域表示漏区。
604、移除暴露的保护层，在源区中的第一区域沉积金属薄膜，通过退火工艺对金属薄膜进行处理，得到第一区域中的金属层，移除未被退火工艺处理掉的金属薄膜。
其中，暴露的保护层是指未被牺牲层覆盖的保护层。如果步骤602中在半导体衬底上制备了保护层，则在源区中的第一区域沉积金属层之前，需要先移除暴露的保护层。具体地，在移除暴露的保护层时，可以通过刻蚀技术实现。
当在源区中的第一区域沉积金属薄膜后，通过退火工艺处理时，组成金属薄膜的金属和源区中的半导体发生化学反应而生成金属硅化物，如氮化硅等，因此，金属层的实际组成材料为金属硅化物。
进一步地，通过退火工艺处理时，并不能正好反应掉金属薄膜中的所有金属，因此，在生成金属层时，需要移除未被退火工艺处理掉的金属薄膜。其中，在移除未被退火工艺处理掉的金属薄膜时，可以通过刻蚀技术实现。如图10所示，其示出了一种金属层的示意图。
可选地，除了可以在源区中的第一区域制备金属层外，还可以在漏区中的部分区域制备金属层。在漏区中的部分区域制备金属层的方式与在源区中的第 一区域制备金属层的方式相同，具体可参见在源区中的第一区域制备金属层的方式，本发明实施例对此不作详细阐述。
605、移除剩余的保护层和牺牲层，在半导体衬底的上表面依次生长半导体薄膜作为初始口袋层、沉积生长介质薄膜作为初始栅氧层、沉积多晶硅或者金属作为初始栅区。
关于初始口袋层、初始栅氧层和初始栅区的材料与上述各个实施例中所述的口袋层、栅氧层和栅区的材料分别相同，此处不再赘述。
如图11所示，其示出了一种初始口袋层、初始栅氧层和初始栅区的示意图。在图11中，初始口袋层、初始栅氧层和初始栅区完全覆盖半导体衬底的上表面。
606、根据预先设置的口袋层、栅氧层和栅区的形状，对初始口袋层、初始栅氧层和初始栅区进行处理，得到口袋层、栅氧层和栅区。
其中，口袋层至少要部分覆盖金属层，且口袋层的另一个端不与漏区重叠，以减小TFET漏电的可能性，从而提高TFET的性能。
具体地，在对初始口袋层、初始栅氧层和初始栅区进行处理，得到口袋层、栅氧层和栅区时，可以结合光刻和各向异性刻蚀技术实现。
需要说明的是，步骤605和步骤606为在半导体衬底的上表面的部分区域依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区的一种具体实现方式，且步骤605和步骤606以先制备初始口袋层、初始栅氧层和初始栅区，并对初始口袋层、初始栅氧层和初始栅区进行处理得到口袋层、栅氧层和栅区为例进行了说明。然而，在生成口袋层、栅氧层和栅区时，也可以根据预先设置的口袋层、栅氧层和栅区的形状，直接在半导体衬底上表面上的部分区域依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区，从而达到节省工艺流程的目的。
如图12所示，其示出了一种口袋层、栅氧层和栅区的结构示意图。
607、在口袋层、栅氧层和栅区两侧制备隔离墙。
其中，隔离墙的材料为绝缘材料，如氮化硅等。具体地，可以通过各向异性刻蚀技术在口袋层、栅氧层和栅区两侧制备隔离墙。该隔离墙用于隔离后续制备的金属源电极、金属栅电极及金属漏电极，从而避免短路。另外，通过设置隔离墙，可以确保TFET的隧穿方向为由下至上，即隧穿方向为竖直方向而 非水平方向。
如图13所示，其示出了一种隔离墙的示意图。
608、在隔离墙及栅区外侧填充低介电材料，并在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极。
其中，低介电材料可以为二氧化硅或氮化硅等。金属源电极、金属栅电极和金属漏电极分别制备于源区、栅区及漏区与低介电材料接触的一定区域。通过填充低介电材料，可以防止TFET的寄生电容比较大。另外，通过低介电材料，能对金属源电极、金属栅电极和金属漏电极起到很好的机械支撑作用。
如图14所示，其示出了一种低介电材料及金属源电极、金属栅电极和金属漏电极的示意图。
本发明实施例提供的TFET的制备方法，通过在源区中的第一区域制备金属层，使得口袋层与源区中非金属层所在的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结。在该种结构下，当TFET的栅控电压大于阈值电压时，TFET处于开启状态，此时，除了第一隧穿结会发生隧穿外，第二隧穿结也同时发生隧穿，而第二隧穿结为金属和半导体组成的肖特基隧穿结，由于肖特基势垒具有较大的能带调控能力以及能够减小隧穿距离，而减小隧穿距离可以提高隧穿效率，因此，该TFET的载流子隧穿效率相对于仅由口袋层与源区组成隧穿结的TFET，隧穿效率比较高，因而能够提高TFET的隧穿电流，从而实现不通过增加口袋层面积来增加隧穿电流，从而不至于使TFET的版图面积过大，因而能够提高芯片上TFET的集成密度。
需要说明的是，上述图6所对应实施例中的步骤604以在源区中的第一区域沉积金属薄膜，通过退火工艺对金属薄膜进行处理，得到第一区域中的金属层，移除未被退火工艺处理掉的金属薄膜的方式，对在源区中的第一区域制备金属层的方式进行了举例说明。步骤604中所述的制备金属层的方式适用于当口袋层和半导体衬底为相同材料或不同材料的情况。然而，在另一个实施例中，当口袋层和半导体衬底为不同材料时，还可以其它方式在源区中的第一区域制备金属层。在此种情况下，制备TFET的方法可参见图15所对应实施例的内容。
图15是本发明另一实施例提供的一种TFET的制备方法流程图。如图15所示，本发明实施例提供的制备方法包括：
1501、设置半导体衬底。
该步骤的原理同步骤601中的原理一致，具体可参见步骤601中的内容，此处不再赘述。半导体衬底的结构仍可参见图7。
1502、在半导体衬底上制备保护层，在保护层上制备指定形状的牺牲层。
该步骤的原理同步骤602中的原理一致，具体可参见步骤602中的内容，此处不再赘述。保护层及牺牲层的结构仍可参见图8。
1503、利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入；利用光刻技术保护源区，对预设漏区进行第二种离子注入；对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
该步骤的原理同步骤603中的原理一致，具体可参见步骤603中的内容，此处不再赘述。如图16所示，其示出了一种源区和漏区的示意图。
1504、移除保护层和牺牲层，在半导体衬底的上表面依次生长半导体薄膜作为初始口袋层、沉积生长介质薄膜作为初始栅氧层、沉积多晶硅或者金属作为初始栅区。
具体地，可以通过刻蚀技术移除全部的保护层和牺牲层。
另外，在半导体衬底的上表面依次生长半导体薄膜作为初始口袋层、沉积生长介质薄膜作为初始栅氧层、沉积多晶硅或者金属作为初始栅区的原理，同上述步骤605中在半导体衬底的上表面依次生长半导体薄膜作为初始口袋层、沉积生长介质薄膜作为初始栅氧层、沉积多晶硅或者金属作为初始栅区的原理一致，具体可参见上述步骤605中的内容，此处不再赘述。如图17所示，其示出了一种初始口袋层、初始栅氧层和初始栅区的示意图。
1505、根据预先设置的口袋层、栅氧层和栅区的形状，对初始口袋层、初始栅氧层和初始栅区进行处理，得到口袋层、栅氧层和栅区。
该步骤的原理同步骤606中的原理一致，具体可参见步骤606中的内容，此处不再赘述。
1506、在口袋层、栅氧层和栅区两侧制备隔离墙。
该步骤的原理同步骤607中的原理一致，具体可参见步骤607中的内容，此处不再赘述。如图18所示，其示出了一种隔离墙的示意图。
1507、当半导体衬底及口袋层的材料不同时，利用光刻蚀技术保护漏区而暴露源区，采用刻蚀技术移除源区中第一区域中的材料，形成沟槽。
其中，沟槽与口袋层部分重叠。具体地，可以通过湿法刻蚀等各向同性刻 蚀技术移除源区第一区域中的材料。
如图19所示，其示出了一种沟槽的示意图。
1508、采用金属或者金属硅化物填充沟槽，得到第一区域中的金属层。
如图20所示，其示出了一种金属层的示意图。
当口袋层和半导体衬底的材料不同时，可以通过步骤1507和1508的方式制备金属层。具体地，当口袋层和半导体衬底的材料不同时，当采用刻蚀技术移除源区第一区域中的材料时，不会损坏口袋层。而当口袋层与半导体衬底为相同材料时，当采用刻蚀技术移除源区第一区域中的材料时，可能同时移除掉口袋层。因此，步骤1507和步骤1508中的方式适用于当口袋层与半导体衬底为不同材料的情况。
1509、在隔离墙及栅区外侧填充低介电材料，并在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极。
该步骤的原理同步骤608中的原理一致，具体可参见步骤608中的内容，此处不再赘述。
如图21所示，其示出了一种低介电材料、金属源电极、金属栅电极及金属漏电极的示意图。
本发明实施例提供的TFET的制备方法，通过在源区中的第一区域制备金属层，使得口袋层与源区中非金属层所在的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结。在该种结构下，当TFET的栅控电压大于阈值电压时，TFET处于开启状态，此时，除了第一隧穿结会发生隧穿外，第二隧穿结也同时发生隧穿，而第二隧穿结为金属和半导体组成的肖特基隧穿结，由于肖特基势垒具有较大的能带调控能力以及能够减小隧穿距离，而减小隧穿距离可以提高隧穿效率，因此，该TFET的载流子隧穿效率相对于仅由口袋层与源区组成隧穿结的TFET，隧穿效率比较高，因而能够提高TFET的隧穿电流，从而实现不通过增加口袋层面积来增加隧穿电流，从而不至于使TFET的版图面积过大，因而能够提高芯片上TFET的集成密度。
图22是本发明另一实施例提供的一种TFET的制备方法的流程图，该实施例所提供的制备方法可以用于制备上述图3或图4所对应实施例提供的TFEF。如图22所示，本发明实施例提供的制备方法包括：
2201、设置半导体衬底。
该步骤的原理同步骤601中的原理一致，具体可参见步骤601中的内容，此处不再赘述。
2202、在半导体衬底上的指定区域制备漏区。
关于指定区域的具体位置，可以结合实际制备TFET的过程而定，本发明实施例对此不作具体限定。
具体地，在半导体衬底上制备漏区的方式可以为：在半导体中掺杂一定浓度的离子而得到漏区等。
2203、在漏区上制备沟道区。
关于制备沟道区的方式，可以结合已有的沟道区制备方式，本发明实施例对此不作具体限定。
2204、在沟道区上制备源区。
具体地，在制备源区时，包括但不限于通过在沟道区上制备半导体，并在半导体层中掺杂离子的方式实现。
2205、在源区中的第一区域制备金属层。
具体地，制备金属层的方式可以同上述步骤604中制备金属层的原理一致，具体可参见上述步骤604中的内容。
2206、在沟道区和源区两侧依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区。
该步骤的原理同上述步骤605和步骤606中的原理相同，具体可参见上述步骤605和步骤606中的内容，此处不再赘述。
2207、在栅区与漏区相接触的一侧制备隔离墙，并在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极。
关于隔离墙的材料、制备方法、功能等内容，可以参见上述607中的内容，此处不再进行赘述。
本发明实施例提供的TFET的制备方法，通过在源区中的第一区域制备金属层，使得口袋层与源区中非金属层所在的第二区域组成TFET的第一隧穿结，口袋层与金属层组成TFET的第二隧穿结。在该种结构下，当TFET的栅控电压大于阈值电压时，TFET处于开启状态，此时，除了第一隧穿结会发生隧穿外，第二隧穿结也同时发生隧穿，而第二隧穿结为金属和半导体组成的肖特基隧穿结，由于肖特基势垒具有较大的能带调控能力以及能够减小隧穿距离，而减小隧穿距离可以提高隧穿效率，因此，该TFET的载流子隧穿效率相对于仅 由口袋层与源区组成隧穿结的TFET，隧穿效率比较高，因而能够提高TFET的隧穿电流，从而实现不通过增加口袋层面积来增加隧穿电流，从而不至于使TFET的版图面积过大，因而能够提高芯片上TFET的集成密度。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

  1. 一种隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管包括源区、漏区、沟道区、口袋层、栅氧层和栅区，其中：
    所述沟道区连接所述源区和所述漏区；
    所述口袋层和所述栅氧层依次制备于所述源区与所述栅区之间，所述口袋层位于靠近所述源区的一侧；
    所述源区中的第一区域制备有金属层，所述第一区域位于所述源区与所述口袋层相接触的一侧，且所述口袋层至少部分覆盖所述金属层；
    所述口袋层与所述源区中的第二区域组成所述隧穿场效应晶体管的第一隧穿结，所述口袋层与所述金属层组成所述隧穿场效应晶体管的第二隧穿结，所述第二区域为所述源区中除所述第一区域外的区域。
  2. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述源区和所述漏区分离地制备于半导体衬底内部；
    所述口袋层制备于所述半导体衬底上表面的部分区域；
    所述栅氧层和所述栅区依次制备于所述口袋层上。
  3. 根据权利要求2所述的隧穿场效应晶体管，其特征在于，所述口袋层、所述栅氧层和所述栅区两侧制备有隔离墙；
    所述源区、所述栅区和所述漏区的指定位置处分别制备有金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
  4. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述漏区制备于半导体衬底上，所述沟道区制备于所述漏区上的部分区域，所述源区制备于所述沟道区上；
    所述口袋层完全覆盖所述源区和所述沟道区的两侧区域；
    所述栅氧层和所述栅区依次制备于所述口袋层外侧。
  5. 根据权利要求4所述的隧穿场效应晶体管，其特征在于，所述栅区与所述漏区的接触侧制备有隔离墙；
    所述源区、所述栅区和所述漏区的指定位置处分别制备有金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
  6. 根据权利要求2或4所述的隧穿场效应晶体管，其特征在于，所述半导体衬底的材料为体硅、绝缘体上的硅、锗硅、锗以及III-V族化合物半导体中的一种；
    所述口袋层的材料为硅、锗硅、锗以及III-V族化合物半导体中的一种。
  7. 根据权利要求2或4所述的隧穿场效应晶体管，其特征在于，所述半导体衬底及所述口袋层为相同的材料或不同的材料。
  8. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述栅区的材料为多晶硅以及金属中的一种；
    所述栅氧层的材料为二氧化硅、四氮化三硅以及高介电材料中的一种。
  9. 一种隧穿场效应晶体管的制备方法，其特征在于，所述制备方法包括：
    分离地制备源区和漏区，在所述源区和所述漏区之间制备沟道区；
    制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层，所述口袋层制备于靠近所述源区的一侧；
    在所述源区中的第一区域制备金属层，所述第一区域位于所述源区与所述口袋层相接触的一侧，且所述口袋层至少部分覆盖所述金属层，使所述口袋层与所述源区中的第二区域组成隧穿场效应晶体管的第一隧穿结，所述口袋层与所述金属层组成所述隧穿场效应晶体管的第二隧穿结，所述第二区域为所述源区中除所述第一区域外的区域。
  10. 根据权利要求9所述的制备方法，其特征在于，所述分离地制备源区和漏区，包括：
    设置半导体衬底；
    利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入；
    利用光刻技术保护所述源区，对所述预设漏区进行第二种离子注入；
    对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
  11. 根据权利要求9所述的制备方法，其特征在于，所述分离地制备源区和漏区，包括：
    设置半导体衬底；
    在所述半导体衬底上的指定区域制备漏区；
    在所述漏区上制备沟道区；
    在所述沟道区上制备源区。
  12. 根据权利要求10所述的制备方法，其特征在于，所述利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入之前，还包括：
    在所述半导体衬底上制备保护层，所述保护层用于在对所述预设源区和所述预设漏区进行离子注入时，保护所述半导体衬底；
    在所述保护层上制备指定形状的牺牲层，所述牺牲层用于在对所述预设源区和所述预设漏区进行离子注入时，自对准地形成沟道区，所述沟道区连接所述源区与所述漏区。
  13. 根据权利要求10或11所述的制备方法，其特征在于，所述在所述源区中的第一区域制备金属层，包括：
    在所述源区中的第一区域沉积金属薄膜；
    通过退火工艺对金属薄膜进行处理，得到所述第一区域中的金属层；
    移除未被退火工艺处理掉的金属薄膜。
  14. 根据权利要求10或11所述的制备方法，其特征在于，在所述源区中的第一区域制备金属层，包括：
    当所述半导体衬底及所述口袋层的材料不同时，利用光刻蚀技术保护所述漏区而暴露所述源区，采用刻蚀技术移除所述源区第一区域中的材料，形成沟槽；
    采用金属或者金属硅化物填充所述沟槽，得到所述第一区域中的金属层。
  15. 根据权利要求10所述的制备方法，其特征在于，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层，包括：
    在所述半导体衬底的上表面的部分区域依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区。
  16. 根据权利要求11所述的制备方法，其特征在于，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层，包括：
    在所述沟道区和所述源区两侧依次生长半导体薄膜作为口袋层、沉积生长介质薄膜作为栅氧层、沉积多晶硅或者金属作为栅区。
  17. 根据权利要求9所述的制备方法，其特征在于，所述在所述源区中的第一区域沉积金属层之后，还包括：
    在所述漏区中的部分区域沉积金属层。
  18. 根据权利要求10所述的制备方法，其特征在于，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层之后，还包括：
    在所述口袋层、所述栅氧层和所述栅区两侧制备隔离墙；
    在所述源区、所述栅区和所述漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
  19. 根据权利要求11所述的制备方法，其特征在于，所述制备栅区，在所述源区和所述栅区之间依次制备口袋层和栅氧层之后，还包括：
    在所述栅区与所述漏区相接触的一侧制备隔离墙；
    在所述源区、所述栅区和所述漏区的指定位置处分别制备金属源电极、金 属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
PCT/CN2015/088754 2015-09-01 2015-09-01 隧穿场效应晶体管及其制备方法 WO2017035780A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2015/088754 WO2017035780A1 (zh) 2015-09-01 2015-09-01 隧穿场效应晶体管及其制备方法
CN201580082816.6A CN107924941B (zh) 2015-09-01 2015-09-01 隧穿场效应晶体管及其制备方法
US15/908,393 US10446672B2 (en) 2015-09-01 2018-02-28 Tunnel field-effect transistor and tunnel field-effect transistor production method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/088754 WO2017035780A1 (zh) 2015-09-01 2015-09-01 隧穿场效应晶体管及其制备方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/908,393 Continuation US10446672B2 (en) 2015-09-01 2018-02-28 Tunnel field-effect transistor and tunnel field-effect transistor production method

Publications (1)

Publication Number Publication Date
WO2017035780A1 true WO2017035780A1 (zh) 2017-03-09

Family

ID=58186602

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/088754 WO2017035780A1 (zh) 2015-09-01 2015-09-01 隧穿场效应晶体管及其制备方法

Country Status (3)

Country Link
US (1) US10446672B2 (zh)
CN (1) CN107924941B (zh)
WO (1) WO2017035780A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019051651A1 (zh) * 2017-09-12 2019-03-21 华为技术有限公司 一种tfet及其制备方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180138307A1 (en) * 2016-11-17 2018-05-17 Globalfoundries Inc. Tunnel finfet with self-aligned gate
CN110416080B (zh) * 2018-04-28 2021-01-29 华为技术有限公司 隧穿场效应管及其制造方法、芯片
US10644150B2 (en) 2018-06-04 2020-05-05 International Business Machines Corporation Tunnel field-effect transistor with reduced subthreshold swing
US11164939B2 (en) * 2018-06-27 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Tunnel field-effect transistor and method for forming the same
US11621340B2 (en) 2019-11-12 2023-04-04 International Business Machines Corporation Field-effect transistor structure and fabrication method
US11201246B2 (en) 2019-11-12 2021-12-14 International Business Machines Corporation Field-effect transistor structure and fabrication method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060118899A1 (en) * 2004-12-03 2006-06-08 Jang Moon G Schottky barrier tunnel single electron transistor and method of manufacturing the same
US7777282B2 (en) * 2008-08-13 2010-08-17 Intel Corporation Self-aligned tunneling pocket in field-effect transistors and processes to form same
CN102751325A (zh) * 2011-04-21 2012-10-24 中国科学院微电子研究所 一种隧穿场效应晶体管及其制造方法
US20140209863A1 (en) * 2013-01-28 2014-07-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
CN104617137A (zh) * 2015-01-19 2015-05-13 华为技术有限公司 一种场效应器件及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384122B1 (en) * 2008-04-17 2013-02-26 The Regents Of The University Of California Tunneling transistor suitable for low voltage operation
US8587075B2 (en) * 2008-11-18 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel field-effect transistor with metal source
US9159565B2 (en) * 2009-08-20 2015-10-13 Globalfoundries Singapore Pte. Ltd. Integrated circuit system with band to band tunneling and method of manufacture thereof
JP5734744B2 (ja) * 2011-05-27 2015-06-17 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5728444B2 (ja) * 2012-08-23 2015-06-03 株式会社東芝 半導体装置およびその製造方法
CN103594519A (zh) * 2013-11-11 2014-02-19 苏州智权电子科技有限公司 一种隧穿场效应浮栅晶体管及其制造方法
JP6175411B2 (ja) * 2014-06-16 2017-08-02 東芝メモリ株式会社 半導体装置
DE102014018382B4 (de) * 2014-12-15 2018-07-26 Forschungszentrum Jülich GmbH Tunnel-Feldeffekttransistor sowie Verfahren zu dessen Herstellung

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060118899A1 (en) * 2004-12-03 2006-06-08 Jang Moon G Schottky barrier tunnel single electron transistor and method of manufacturing the same
US7777282B2 (en) * 2008-08-13 2010-08-17 Intel Corporation Self-aligned tunneling pocket in field-effect transistors and processes to form same
CN102751325A (zh) * 2011-04-21 2012-10-24 中国科学院微电子研究所 一种隧穿场效应晶体管及其制造方法
US20140209863A1 (en) * 2013-01-28 2014-07-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
CN104617137A (zh) * 2015-01-19 2015-05-13 华为技术有限公司 一种场效应器件及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019051651A1 (zh) * 2017-09-12 2019-03-21 华为技术有限公司 一种tfet及其制备方法

Also Published As

Publication number Publication date
US10446672B2 (en) 2019-10-15
CN107924941A (zh) 2018-04-17
US20180190802A1 (en) 2018-07-05
CN107924941B (zh) 2020-09-04

Similar Documents

Publication Publication Date Title
US10910278B2 (en) Semiconductor device, method of manufacturing the same and electronic device including the same
WO2017035780A1 (zh) 隧穿场效应晶体管及其制备方法
KR100748261B1 (ko) 낮은 누설전류를 갖는 ｆｉｎ 전계효과트랜지스터 및 그제조 방법
US12096623B2 (en) Vertical semiconductor device, manufacturing method therefor, integrated circuit and electronic device
US20160365456A1 (en) Semi-floating gate fet
CN104517847B (zh) 无结晶体管及其形成方法
WO2015131527A1 (zh) 一种半浮栅器件及其制备方法
CN103094121B (zh) 一种用于制造半导体器件的方法
US10861962B2 (en) Semiconductor device and method of fabricating the same
CN104517901B (zh) Cmos晶体管的形成方法
US20160133695A1 (en) A method of inhibiting leakage current of tunneling transistor, and the corresponding device and a preparation method thereof
WO2016070592A1 (zh) 一种互补隧穿场效应晶体管及其制作方法
CN103515283B (zh) 半导体器件制造方法
WO2016119682A1 (zh) 隧穿场效应晶体管及其制备方法
KR101682420B1 (ko) 선택적 게르마늄 응축과 측벽공정을 이용한 자기정렬된 이종접합 터널링 전계효과 트랜지스터의 제조방법
US20230343851A1 (en) Semiconductor device and method for manufacturing the same
CN104425606B (zh) 隧穿场效应晶体管及其形成方法
US11201246B2 (en) Field-effect transistor structure and fabrication method
CN113257918B (zh) 半导体器件及其制造方法及包括该器件的电子设备
WO2022041896A1 (zh) 一种半导体结构及其制备方法
WO2017079928A1 (zh) 隧穿场效应晶体管及其制备方法
CN113363321B (zh) 半导体结构及其形成方法
CN113363256B (zh) 半导体结构及其形成方法
KR100823874B1 (ko) 낮은 누설전류를 갖는 고밀도 ｆｉｎ 전계효과트랜지스터및 그 제조 방법
CN104143530B (zh) 晶体管及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15902587

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15902587

Country of ref document: EP

Kind code of ref document: A1