WO2019051651A1 - 一种tfet及其制备方法 - Google Patents

一种tfet及其制备方法 Download PDF

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Publication number
WO2019051651A1
WO2019051651A1 PCT/CN2017/101447 CN2017101447W WO2019051651A1 WO 2019051651 A1 WO2019051651 A1 WO 2019051651A1 CN 2017101447 W CN2017101447 W CN 2017101447W WO 2019051651 A1 WO2019051651 A1 WO 2019051651A1
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Prior art keywords
region
photoresist layer
covered
forming
sidewall
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PCT/CN2017/101447
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English (en)
French (fr)
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蔡皓程
杨喜超
赵静
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华为技术有限公司
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Priority to PCT/CN2017/101447 priority Critical patent/WO2019051651A1/zh
Publication of WO2019051651A1 publication Critical patent/WO2019051651A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a TFET and a method for fabricating the same. .
  • the working principle of Tunneling Field Effect Transistor is fundamentally different from that of traditional MOSFET.
  • the working principle of MOSFET is the diffusion drift mechanism of carriers, and the working principle of TFET device is band tunneling mechanism. .
  • the turn-on current of the TFET has no exponential dependence on the temperature, the sub-negative current is not limited by the carrier heat distribution, and a relatively small SS can be realized, thereby reducing the operating voltage of the device and reducing the device.
  • the shutdown current reduces the static power dissipation of the device.
  • the tunneling is roughly divided into point tunneling and line tunneling. Since the tunneling provides a larger tunneling area, the tunneling probability can be increased, and the turn-on current can be increased without significantly increasing the leakage current. .
  • the present application provides a TFET and a method of fabricating the same, which can further improve leakage current.
  • a preparation method comprising: forming a first protective layer covering at least an active region on a substrate; wherein the substrate defines an active region by an isolation structure; and forming a first protective layer Forming a main shaft on the substrate and a hard mask covering the main shaft, the main shaft covers an area where the drain area of the active area is located; wherein the main shaft has an inclined side surface, and a lower surface area of the main shaft is larger than an upper surface area; a sidewall is formed around the main shaft, And doping the active region not covered by the sidewall and the hard mask to form a source region; filling with a first filler, and performing a planarization process to expose the main axis and the sidewall; removing the upper portion of the isolation structure The sidewall, the main axis, and the oblique ion implantation process to form a drain region such that the orthographic projection of the drain region on the substrate does not overlap with the orthographic projection of the sidewall of the active region on the substrate; using the
  • the formed sidewalls can also be tilted, so that the orthographic projection of the drain region on the substrate can be made active when the drain region is formed by the oblique ion implantation process based on the self-alignment method.
  • the orthographic projection of the sidewalls of the regions on the substrate does not overlap, and the non-overlapping regions can be precisely controlled, so that after the sidewalls are removed to form the gates, the gate and drain regions have no overlapping regions, thereby improving leakage current.
  • a TFET having a high precision can be fabricated.
  • the active region not covered by the sidewall and the hard mask is doped to form a source region, including: removing sidewalls and Hard mask covered
  • the first protective layer etches the exposed substrate to form a source region trench; and epitaxially grows a material containing P-type ions or N-type ions in the source region trench to form a source region.
  • performing a doping process on the active region not covered by the sidewall and the hard mask to form a source region comprising: performing an ion implantation process on the active region not covered by the sidewall and the hard mask to form a source region;
  • the first protective layer above the source region is removed.
  • the first protective layer can protect the substrate during ion implantation to avoid defects on the surface of the substrate, and after the ion implantation, the first protective layer may have defects, thereby removing the first protective layer and avoiding the TFET The impact of performance.
  • the preparation method further includes: removing the upper portion above the drain region A protective layer. To avoid defects in the first protective layer after ion implantation, the performance of the TFET is affected.
  • the first protective layer has a thickness between 2 and 10 nm.
  • the first protective layer having a thickness of 2 to 10 nm can protect the active region, and on the other hand, the first protective layer can be prevented from being too thick to generate a large stress on the substrate.
  • the simultaneous preparation of the N-type and P-type TFETs Forming a sidewall around the spindle and doping the active region not covered by the sidewall and the hard mask to form a source region, including: forming an insulating layer on the substrate on which the spindle and the hard mask are formed a film layer, and a first photoresist layer is formed on the insulating film layer, the first photoresist layer exposing the N-type TFET region; and the insulating film layer not covered by the first photoresist layer is etched by an etching process Forming a sidewall around the major axis of the N-type TFET region, and doping the active region not covered by the sidewall and the hard mask to form a source region of the N-type TFET; removing the first photoresist layer; forming a second photoresist layer, the second photoresist layer
  • the simultaneous preparation of the N-type and P-type TFETs Forming a sidewall around the spindle and doping the active region not covered by the sidewall and the hard mask to form a source region, including: forming an insulating layer on the substrate on which the spindle and the hard mask are formed a film layer, and a first photoresist layer is formed on the insulating film layer, the first photoresist layer exposing the N-type TFET region; and the insulating film layer not covered by the first photoresist layer is etched by an etching process Forming a sidewall around the major axis of the N-type TFET region, and doping the active region not covered by the sidewall and the hard mask to form a source region of the N-type TFET; removing the first photoresist layer; forming Covering a second protective layer of the substrate, and forming
  • the sidewall and the main axis located above the isolation structure are removed, and a tilt ion implantation process is performed to form The drain region includes: forming a third photoresist layer, the third photoresist layer covering the sidewalls of the active region in the P-type TFET region and the N-type TFET region; removing the third photoresist by an etching process Layer covering sidewalls and removing the main axis; forming a fourth photoresist layer, exposing the N-type TFET region to the fourth photoresist layer, performing a tilt ion implantation process to form a drain region of the N-type TFET; forming a fifth photoresist The fifth photoresist layer covers the N-type TFET region and performs a tilt ion implantation process to form a drain region of the P-type TFET.
  • the material of the first protective layer is SiO 2 ; the material of the main axis is polysilicon; the material of the hard mask and the sidewall is Si 3 N 4 ; The materials of the first filler and the second filler are both SiO 2 .
  • the material of the substrate includes one of Si, SOI, SiGe, Ge, GeOI.
  • a TFET is provided which can be prepared by any of the possible implementations of the first aspect.
  • FIG. 1 is a schematic flow chart 1 of a method for preparing a TFET according to the present application
  • FIG. 2 is a schematic cross-sectional view showing the formation of a first protective layer, a main axis, and a hard mask on a substrate;
  • 3a is a schematic cross-sectional view showing the sidewalls being formed and removing the first protective layer not covered by the sidewalls and the hard mask;
  • Figure 3b is a cross-sectional view showing the source region formed on the basis of Figure 3a;
  • FIG. 4 is a schematic cross-sectional view showing a sidewall formed and forming a source region by an ion implantation process
  • Figure 5 is a schematic cross-sectional view showing filling and planarization using a first filler
  • 6a is a cross-sectional view showing the removal of a sidewall, a main axis located above the isolation structure, and forming a drain region by a tilt ion implantation process;
  • Figure 6b is a schematic cross-sectional view showing the exposed first protective layer on the basis of Figure 6a;
  • FIG. 7 is a cross-sectional view showing a first protective layer exposed, planarized, and sidewall-covered and covered with a second filler;
  • Figure 8 is a cross-sectional view showing the formation of a gate dielectric layer and a gate electrode in a region where the substrate is exposed;
  • FIG. 9 is a second schematic diagram of a process for preparing a TFET according to the present application.
  • 10a is a top plan view showing the formation of a first protective layer, a main axis, and a hard mask in a P-type TFET and an N-type TFET region on a substrate;
  • Figure 10b is a cross-sectional view of the A3A4 direction and the A1A2 direction of Figure 10a;
  • 11a is a top plan view showing a first photoresist layer forming an insulating film layer and exposing an N-type TFET region;
  • Figure 11b is a cross-sectional view of the B3B4 direction and the B1B2 direction of Figure 11a;
  • Figure 12a is a top plan view showing the sidewalls formed around the major axis of the N-type TFET
  • Figure 12b is a cross-sectional view of the C3C4 direction and the C1C2 direction of Figure 12a;
  • Figure 13a is a top plan view of a source region forming an N-type TFET
  • Figure 13b is a cross-sectional view of the D3D4 direction and the D1D2 direction of Figure 13a;
  • 14a is a top plan view of forming a second photoresist layer covering an N-type TFET region
  • Figure 14b is a cross-sectional view of the E3E4 direction and the E1E2 direction of Figure 14a;
  • Figure 15a is a top plan view showing the sidewalls formed around the main axis of the P-type TFET
  • Figure 15b is a cross-sectional view of the F3F4 direction and the F1F2 direction of Figure 15a;
  • Figure 16a is a top plan view showing a source region of a P-type TFET
  • Figure 16b is a cross-sectional view of the G3G4 direction and the G1G2 direction of Figure 16a;
  • Figure 17a is a top plan view showing the main axis and the sidewalls exposed through a planarization process
  • Figure 17b is a cross-sectional view of the H3H4 direction and the H1H2 direction of Figure 17a;
  • Figure 18a is a top plan view showing the formation of a third photoresist layer covering the sidewalls in the active region;
  • Figure 18b is a cross-sectional view of the I3I4 direction and the I1I2 direction of Figure 18a;
  • 19a is a top plan view of removing a sidewall not covered by a third photoresist layer and removing the spindle;
  • Figure 19b is a cross-sectional view of the J3J4 direction and the J1J2 direction of Figure 19a;
  • Figure 20a is a top plan view showing a fourth photoresist layer exposing an N-type TFET region
  • Figure 20b is a cross-sectional view of the K3K4 direction and the K1K2 direction of Figure 20a;
  • Figure 21a is a top plan view showing a fifth photoresist layer covering an N-type TFET region
  • Figure 21b is a cross-sectional view of the L3L4 direction and the L1L2 direction of Figure 21a;
  • 22a is a top plan view showing a sidewall exposed by a planarization process, and removing the sidewall and the first protective layer covered by the sidewall;
  • Figure 22b is a cross-sectional view of the M3M4 direction and the M1M2 direction of Figure 22a;
  • Figure 23 is a cross-sectional view showing a gate dielectric layer and a gate
  • 24a is a top plan view showing a second protective layer forming a cover substrate and a second photoresist layer covering the N-type TFET region;
  • Figure 24b is a cross-sectional view of the N3N4 direction and the N1N2 direction of Figure 24a;
  • 25a is a top plan view of removing a second protective layer not covered by a second photoresist layer and removing a second photoresist layer;
  • Figure 25b is a cross-sectional view of the O3O4 direction and the O1O2 direction of Figure 25a;
  • Figure 26a is a top plan view showing a source region of a P-type TFET formed by forming sidewalls around the major axis of the P-type TFET;
  • Figure 26b is a cross-sectional view of the P3P4 direction and the P1P2 direction of Figure 26a;
  • FIG. 27 is a cross-sectional view showing an NTFET and a P-type TFET provided by the present application.
  • the present application provides a method for preparing a TFET, as shown in FIG. 1, comprising the following steps:
  • a first protective layer 30 covering at least the active region is formed on the substrate 10; wherein the substrate 10 defines an active region by the isolation structure 20.
  • the material of the substrate 10 may be bulk silicon (Si), silicon on insulator (SOI), germanium silicon (SiGe), germanium (Ge), germanium on germanium (GeOI), or the like.
  • the isolation structure 20 can be formed by a shallow tunnel isolation (STI) process.
  • the STI process that is, forming a shallow trench by performing photolithography and etching processes on the substrate 10; filling in the shallow trench to form the isolation structure 20.
  • the material of the first protective layer 30 may be, for example, silicon dioxide (SiO 2 ).
  • the thickness of the first protective layer 30 may be in the range of 2 to 10 nm.
  • the first protective layer having a thickness of 2 to 10 nm can protect the active region, and on the other hand, the first protective layer can be prevented from being too thick to generate a large stress on the substrate.
  • FIG. 2 is schematically illustrated by the first protective layer 30 covering only the active region.
  • the active regions may be doped or undoped.
  • the drawings of the present application are illustrated with the active region being doped.
  • a main shaft 40 and a hard mask 50 covering the main shaft 40 are formed on the substrate 10 on which the first protective layer 30 is formed, and the main shaft 40 covers an area where the drain region of the active region is located; 40 has an inclined side surface, and the lower surface area of the main shaft 40 is larger than the upper surface area.
  • the material of the spindle 40 can be, for example, polysilicon.
  • the material of the hard mask 50 may be, for example, silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or the like.
  • the hard mask 50 may be a stacked structure of silicon oxide/silicon nitride/silicon oxide.
  • the lower surface of the main shaft 40 is the surface of the main shaft 40 close to the substrate 10
  • the upper surface of the main shaft 40 is the surface of the main shaft 40 away from the substrate 10.
  • a sidewall 60 is formed around the main axis 40, and an active region not covered by the sidewall 60 and the hard mask 50 is doped to form a doping process.
  • Source area 102 Source area 102.
  • the material of the side wall 60 may be, for example, Si 3 N 4 , SiON or the like.
  • the sidewall 60 corresponds to It is the gate region, and the width of the sidewall 60 determines the width of the gate. For the side wall 60, its width is uniform.
  • the doping process is performed on the active region not covered by the sidewall 60 and the hard mask 50.
  • the formation of the source region 102 can be achieved as follows:
  • Method 1 As shown in FIG. 3a, the first protective layer 30 not covered by the sidewall 60 and the hard mask 50 is removed; then the exposed substrate 10 is etched to form a source trench; as shown in FIG. 3b A material containing P-type ions or N-type ions is epitaxially grown in the trenches of the source region to form source regions 102.
  • the source region 102 is doped with P-type ions, in which case, for example, boron (B)-containing silicon germanium (SiGe) may be epitaxially grown in the source region trench.
  • the source region 102 is doped with N-type ions, in which case, for example, phosphorus (P)-containing silicon may be epitaxially grown in the source region trenches.
  • a better doping profile can be obtained, which is beneficial to improve device characteristics.
  • the epitaxial growth material is different from the substrate 10, a hetero-junction can be formed, which brings about an energy band modulation effect to further improve device characteristics.
  • Method 2 As shown in FIG. 4, an ion implantation process is performed on the active region not covered by the sidewall 60 and the hard mask 50 to form the source region 102; and the first protective layer 30 above the source region 102 is removed.
  • the first protective layer 30 can protect the substrate 10 during the ion implantation process, avoiding defects on the surface of the substrate 10, and after the ion implantation, the first protective layer 30 may have defects, thereby removing the first protective layer 30. To avoid the impact on the performance of the TFET.
  • the source region 102 is implanted with a P-type ion such as B, boron difluoride (BF 2 ) or the like.
  • a P-type ion such as B, boron difluoride (BF 2 ) or the like.
  • the source region 102 is implanted with an N-type ion such as P, arsenic (AS), or the like.
  • the first filler is used for filling, and a planarization process is performed to expose the spindle 40 and the sidewall 60.
  • the sidewall 60 and the spindle 40 located above the isolation structure 20 are removed, and a tilt ion implantation process is performed to form a drain region 103, so that the orthographic projection of the drain region 103 on the substrate 10 is active.
  • the orthographic projection of the sidewalls 60 of the regions on the substrate 10 does not overlap.
  • the inclination angle ⁇ can be set in the range of 0° to 30°.
  • the drain region 103 is implanted with N-type ions, such as P, AS, and the like.
  • N-type ions such as P, AS, and the like.
  • the drain region 103 is implanted with a P-type ion such as B, BF 2 or the like.
  • the first protective layer 30 above the drain region 103 can be removed. To avoid defects in the first protective layer 30 after ion implantation.
  • an annealing process can be performed, and ions in the source region 102 and the drain region 103 are activated. Among them, the annealing process may occur before the gate 80 is formed.
  • the first filler and the second filler may be the same material, such as SiO 2 .
  • the above filling process can be performed using tetraethyl orthosilicate (TEOS) or silazane (TOSZ); Flowable Chemical Vapor Deposition (FCVD), high density plasma chemical vapor deposition (High Density) can also be utilized. Plasma Chemical Vapor Deposition (HDP-CVD), High Aspect Ratio Process (HARP) process is used for the above filling process.
  • TEOS tetraethyl orthosilicate
  • TOSZ silazane
  • FCVD Flowable Chemical Vapor Deposition
  • HDP-CVD High Aspect Ratio Process
  • HTP High Aspect Ratio Process
  • a gate dielectric layer 70 and a gate electrode 80 are formed in a region where the substrate 10 is exposed.
  • the present application provides a method for fabricating a TFET.
  • the formed sidewall 60 can also be tilted, so that the drain region 103 can be formed by a tilt ion implantation process based on a self-aligned manner.
  • the orthographic projection of the drain region 103 on the substrate 10 does not overlap with the orthographic projection of the sidewall 60 on the substrate 10 on the active region, and the non-overlapping region can be precisely controlled to form a gate on the sidewall 60.
  • the gate 80 and the drain region 103 are left unoverlapping regions, thereby improving leakage current.
  • a TFET having a high precision can be fabricated.
  • Embodiment 1 provides a method for preparing a TFET, which can simultaneously prepare an N-type TFET and a P-type TFET, as shown in FIG. 9, and includes the following steps:
  • a first protective layer 30 covering the active region is formed on the substrate 10, wherein the substrate 10 defines an active region by the isolation structure 20.
  • the material of the first protective layer 30 may be SiO 2 and may have a thickness in the range of 2 to 10 nm.
  • a main shaft 40 and a hard mask 50 covering the main shaft 40 are formed on the substrate 10 on which the first protective layer 30 is formed, and the main shaft 40 covers an area where the drain region of the active region is located;
  • the main shaft 40 has an inclined side surface, and the lower surface area of the main shaft 40 is larger than the upper surface area.
  • the shape of the main shaft 40 may be a ridge.
  • the material of the main shaft 40 may be polysilicon, and the material of the hard mask may be Si 3 N 4 .
  • the forming of the main shaft 40 and the hard mask 50 may be: firstly depositing a polysilicon film and a Si 3 N 4 film on the substrate 10 on which the first protective layer 30 is formed, and forming a photoresist by photolithography, and photolithography
  • the glue is located in the region where the drain region is located and extends above the isolation structure 20; the polysilicon film and the Si 3 N 4 film are etched by an etching process to form a spindle 40 having inclined sides and a hard mask 50 on the spindle 40; Engraved.
  • an insulating film layer 601 is formed on the substrate 10 on which the spindle 40 and the hard mask 50 are formed, and a first photoresist layer 91 is formed on the insulating film layer 601, first The photoresist layer 601 exposes an N-type TFET region.
  • the material of the insulating film layer 601 may be Si 3 N 4 .
  • the Si 3 N 4 may be deposited first, the insulating film layer 601 is formed, and then the first photoresist layer 91 is formed by a photolithography process, and the first photoresist layer 91 covers the P-type TFET region to expose the N-type TFET region. .
  • the insulating film layer 601 not covered by the first photoresist layer 91 is etched by an etching process, and formed around the main axis 40 of the N-type TFET.
  • the sidewall 60 is doped to the active region not covered by the sidewall 60 and the hard mask 50 to form the source region 102 of the N-type TFET; the first photoresist layer 91 is removed.
  • the insulating film layer 601 not covered by the first photoresist layer 91 may be etched by an isotropic etching process to form sidewalls 60 around the main axis 40 of the N-type TFET.
  • the source region 102 of the N-type TFET can then be formed in the following two ways.
  • the first protective layer 30 not covered by the sidewall 60 and the hard mask 50 is removed, and the exposed substrate 10 is etched to form a source region trench; and B is epitaxially grown in the source region trench.
  • the SiGe material forms the source region 102 of the N-type TFET.
  • the active region not covered by the sidewall 60 and the hard mask 50 is subjected to an ion implantation process, and the implanted ions may be B, BF 2 , etc., forming a source region 102 of the N-type TFET; and removing the source of the N-type TFET The first protective layer 30 above the region 102.
  • a second photoresist layer 92 is formed, and the second photoresist layer 92 covers the N-type TFET region.
  • the insulating film layer 601 not covered by the second photoresist layer 92 is etched by an etching process, and formed around the main axis 40 of the P-type TFET.
  • the sidewall 60 is doped to the active region not covered by the sidewall 60 and the hard mask 50 to form the source region 102 of the P-type TFET; the second photoresist layer 92 is removed.
  • the insulating film layer 601 not covered by the second photoresist layer 92 may be etched by an isotropic etching process to form sidewalls 60 around the main axis 40 of the P-type TFET.
  • the source region 102 of the P-type TFET can then be formed in the following two ways.
  • the first protective layer 30 not covered by the sidewall 60 and the hard mask 50 is removed, and the exposed substrate 10 is etched to form a source region trench; and P is epitaxially grown in the source region trench.
  • a silicon material forms a source region 102 of a P-type TFET.
  • the active region not covered by the sidewall 60 and the hard mask 50 is subjected to an ion implantation process, and the implanted ions may be P, AS, etc., forming a source region 102 of the P-type TFET; and removing the source region of the P-type TFET.
  • SiO 2 may be deposited first to cover the device; then the hard mask 50 is removed by a planarization process (which may be etched and chemically mechanically polished) to expose the spindle 40 and sidewalls 60.
  • a third photoresist layer 93 is formed, and the third photoresist layer 93 covers the sidewalls of the active region in the P-type TFET and N-type TFET regions. 60.
  • the sidewall 60 not covered by the third photoresist layer 93 is removed by an etching process, and the spindle 40 is removed.
  • the side wall 60 not covered by the third photoresist layer 93 may be removed using phosphoric acid (H 3 PO 4 ); the spindle 40 is removed using a solution of tetramethylammonium hydroxide (TMAH) or ammonia (NH 4 OH).
  • TMAH tetramethylammonium hydroxide
  • NH 4 OH ammonia
  • a fourth photoresist layer 94 is formed, and the fourth photoresist layer 94 exposes the N-type TFET region, and a tilt ion implantation process is performed to form a drain region 103 of the N-type TFET.
  • the inclination angle ⁇ can be set within a range of 0° to 30°.
  • the ions to be implanted may be P, AS, or the like.
  • the first protective layer 30 over the drain region 103 of the N-type TFET can be removed.
  • a fifth photoresist layer 95 is formed, and the fifth photoresist layer 95 covers the N-type TFET region, and a tilt ion implantation process is performed to form a drain region 103 of the P-type TFET.
  • the inclination angle ⁇ can be set to 0° to 30°.
  • the implanted ions can be B, BF 2, etc.
  • the first protective layer 30 over the drain region 103 of the P-type TFET can be removed.
  • an annealing process may be performed to activate ions in the source region 102 and the drain region 103.
  • SiO 2 may be deposited first to cover the device; then the sidewall 60 and the first protective layer 30 covered by the sidewall 60 are removed by a planarization process to expose the substrate 10.
  • a gate dielectric layer 70 and a gate electrode 80 are formed in a region where the substrate 10 is exposed.
  • the gate dielectric layer 70 and the gate 80 can be formed using a high-k metal gate (HKMG).
  • HKMG high-k metal gate
  • the source region 102 of the N-type TFET is formed first, and the source region 102 of the P-type TFET is formed.
  • the drain region 103 of the N-type TFET is formed first, and the drain region 103 of the P-type TFET is formed.
  • the present application is not limited thereto.
  • the source region 102 is formed, the source region 102 of the N-type TFET may be formed first, and then the source region 102 of the P-type TFET may be formed. Alternatively, the source region 102 of the P-type TFET may be formed first, and then formed. Source region 102 of the N-type TFET.
  • the drain region 103 of the N-type TFET may be formed first, and then the drain region 103 of the P-type TFET may be formed.
  • the drain region 103 of the P-type TFET may be formed first, and then the drain of the N-type TFET may be formed. Area 103.
  • the difference from the first embodiment is that the steps S24 to S25 in the first embodiment can be replaced by the following steps S40 to S42.
  • the material of the second protective layer 110 may be SiO 2 .
  • the second protective layer 110 can be formed by a deposition process.
  • the second protective layer 110 not covered by the second photoresist layer 92 is removed by an etching process, and the second photoresist layer 92 is removed.
  • the second protective layer 110 not covered by the second photoresist layer 92 may be removed by, for example, an isotropic etching process, such as a soaking hydrofluoric acid method.
  • the insulating film layer 601 not covered by the second protective layer 110 is etched by an etching process, and sidewalls are formed around the main axis 40 of the P-type TFET, and are not side.
  • the active region covered by wall 60 and hard mask 50 is doped to form source region 102 of the P-type TFET; second protective layer 110 is removed (see Figures 16a and 16b).
  • the insulating film layer 601 not covered by the second protective layer 110 may be etched by an isotropic etching process, and sidewalls 60 are formed around the main axis 40 of the P-type TFET.
  • the source region 102 of the P-type TFET can then be formed in the following two ways.
  • the first protective layer 30 not covered by the sidewall 60 and the hard mask 50 is removed, and the exposed substrate 10 is etched to form a source region trench; and P is epitaxially grown in the source region trench.
  • a silicon material forms a source region 102 of a P-type TFET.
  • the active region not covered by the sidewall 60 and the hard mask 50 is subjected to an ion implantation process, and the implanted ions may be P, AS, etc., forming a source region 102 of the P-type TFET; and removing the source region of the P-type TFET.
  • a metal wiring can also be formed.
  • TFET preparation method of the present application is also applicable to the preparation of a TFET of a fin structure, and the drawings of the present application are only illustrated by a planar structure TFET.
  • the present application also provides a TFET which can be prepared by the above preparation method.

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Abstract

一种TFET及其制备方法，涉及半导体技术领域，可进一步改善漏电流。所述TFET的制备方法，包括：在衬底（10）上形成至少覆盖有源区的第一保护层（30）；形成主轴（40）以及硬掩膜（50），主轴（40）覆盖有源区的漏区所在的区域；其中，主轴（40）具有倾斜侧面；在主轴（40）四周形成侧壁（60），并对未被侧壁（60）和硬掩膜（50）覆盖的有源区进行掺杂工艺形成源区（102）；进行平坦化的工艺，露出主轴（40）以及侧壁（60）；去除位于隔离结构（20）上方的侧壁（60）、主轴（40），并进行倾斜离子注入工艺，形成漏区（103），使漏区（103）在衬底（10）上的正投影与位于有源区的侧壁（60）在衬底（10）上的正投影无交叠；进行平坦化的工艺，露出位于有源区的侧壁（60），并去除侧壁（60）以及被侧壁（60）覆盖的第一保护层（30），暴露出衬底（10）；在暴露出衬底（10）的区域，形成栅介质层（70）和栅极（80）。

Description

一种TFET及其制备方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种TFET及其制备方法。.
背景技术
随着金属-氧化物-半导体场效应晶体管(Metal-Oxide-Semiconductor Field Effect Transistor，简称MOSFET)栅长缩小到45nm以下，受载流子波尔兹曼热分布限制的亚阈值摆幅(Subthreshold Swing，简称SS)严重影响了MOSFET器件在相应的栅电压下的开关速率，导致MOSFET的漏电流随着电源电压的降低呈指数增长，从而导致静态功耗呈指数增长。
隧穿场效应晶体管(Tunneling Field Effect Transistor，简称TFET)的工作原理与传统MOSFET有着根本的不同，MOSFET的工作原理是载流子的扩散漂移机制，而TFET器件的工作原理是带带隧穿机制。从工作原理上来看，由于TFET的开启电流与温度没有指数依赖关系，因此亚阂值电流不受载流子热分布的限制，可以实现比较小的SS，从而降低器件的工作电压，减小器件的关断电流，降低器件的静态功耗。其中，依照隧穿的方式大致又分为点隧穿和线隧穿，由于线隧穿提供较大的隧穿面积，因而可提高隧穿机率，增加开启电流的同时又不会大幅增加漏电流。
发明内容
本申请提供一种TFET及其制备方法，可进一步改善漏电流。
第一方面，提供一种的制备方法，包括：在衬底上形成至少覆盖有源区的第一保护层；其中，衬底由隔离结构定义出有源区；在形成有第一保护层的衬底上形成主轴以及覆盖主轴的硬掩膜，主轴覆盖有源区的漏区所在的区域；其中，主轴具有倾斜侧面，且主轴的下表面面积大于上表面面积；在主轴四周形成侧壁，并对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成源区；使用第一填充物进行填充，并进行平坦化的工艺，露出主轴以及侧壁；去除位于隔离结构上方的侧壁、主轴，并进行倾斜离子注入工艺，形成漏区，使漏区在衬底上的正投影与位于有源区的侧壁在衬底上的正投影无交叠；使用第二填充物进行填充，并进行平坦化的工艺，露出位于有源区的侧壁，并去除侧壁以及被侧壁覆盖的第一保护层，暴露出衬底；在暴露出衬底的区域，形成栅介质层和栅极。通过形成具有倾斜侧面的主轴，可使形成的侧壁也倾斜，这样可基于自对准方式，通过倾斜离子注入工艺形成漏区时，可使漏区在衬底上的正投影与位于有源区的侧壁在衬底上的正投影无交叠，且可以精确控制无交叠区域，从而在去除侧壁形成栅极后，使得栅极和漏区无重叠区域，进而改善漏电流。其中，在形成漏区过程中，由于不受光刻工艺限制，因而，可制作精度要求较高的TFET。
结合第一方面，在第一方面的第一种可能的实现方式中，对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成源区，包括：去除未被侧壁和硬掩膜覆盖的 第一保护层，并对露出的衬底进行刻蚀，形成源区沟槽；在源区沟槽内外延生长含P型离子或含N型离子的材料，形成源区。
或者，对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成源区，包括：对未被侧壁和硬掩膜覆盖的有源区进行离子注入工艺，形成源区；去除源区上方的第一保护层。第一保护层可在离子注入过程中保护衬底，避免衬底的表面出现缺陷，而在经过离子注入后，第一保护层会存在缺陷，因而，将第一保护层去除，可避免对TFET性能的影响。
结合第一方面，在第一方面的第二种可能的实现方式中，进行倾斜离子注入工艺形成漏区之后，使用第二填充物进行填充之前，该制备方法还包括：去除漏区上方的第一保护层。以避免经过离子注入后第一保护层存在缺陷，对TFET的性能造成影响。
结合第一方面，在第一方面的第三种可能的实现方式中，第一保护层的厚度在2～10nm之间。一方面，2～10nm厚度的第一保护层可对有源区进行保护，另一方面，可避免第一保护层太厚对衬底产生较大的应力。
结合第一方面或第一方面的第一种到第三种中任一种可能的实现方式，在第一方面的第四种可能的实现方式中，在N型和P型TFET同时制备的情况下，在主轴四周形成侧壁，并对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成源区，包括：在形成有主轴和硬掩膜的衬底上，形成绝缘膜层，并在绝缘膜层上形成第一光刻胶层，第一光刻胶层露出N型TFET区域；利用刻蚀工艺对未被第一光刻胶层覆盖的绝缘膜层进行刻蚀，在N型TFET区域的主轴四周形成侧壁，并对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成N型TFET的源区；去除第一光刻胶层；形成第二光刻胶层，第二光刻胶层覆盖N型TFET区域；利用刻蚀工艺对未被第二光刻胶层覆盖的绝缘膜层进行刻蚀，在P型TFET区域的主轴四周形成侧壁，并对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成P型TFET的源区；去除第二光刻胶层。采用较简单的工艺便可形成N型TFET的源区和P型TFET的源区。
结合第一方面或第一方面的第一种到第三种中任一种可能的实现方式，在第一方面的第五种可能的实现方式中，在N型和P型TFET同时制备的情况下，在主轴四周形成侧壁，并对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成源区，包括：在形成有主轴和硬掩膜的衬底上，形成绝缘膜层，并在绝缘膜层上形成第一光刻胶层，第一光刻胶层露出N型TFET区域；利用刻蚀工艺对未被第一光刻胶层覆盖的绝缘膜层进行刻蚀，在N型TFET区域的主轴四周形成侧壁，并对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成N型TFET的源区；去除第一光刻胶层；形成覆盖衬底的第二保护层，并在第二保护层上形成第二光刻胶层，第二光刻胶层覆盖N型TFET区域；通过刻蚀工艺去除未被第二光刻胶层覆盖的第二保护层，并去除第二光刻胶层；利用刻蚀工艺对未被第二保护层覆盖的绝缘膜层进行刻蚀，在P型TFET区域的主轴四周形成侧壁，并对未被侧壁和硬掩膜覆盖的有源区进行掺杂工艺，形成P型TFET的源区；去除第二保护层。采用较简单的工艺便可形成N型TFET的源区和P型TFET的源区。
结合第一方面的第四种或第五种可能的实现方式，在第一方面的第六种可能的实现方式中，去除位于隔离结构上方的侧壁、主轴，并进行倾斜离子注入工艺，形成漏区，包括：形成第三光刻胶层，第三光刻胶层覆盖P型TFET区域和N型TFET区域中位于有源区的侧壁；通过刻蚀工艺去除未被第三光刻胶层覆盖的侧壁，并去除主轴；形成第四光刻胶层，第四光刻胶层露出N型TFET区域，进行倾斜离子注入工艺，形成N型TFET的漏区；形成第五光刻胶层，第五光刻胶层覆盖N型TFET区域，进行倾斜离子注入工艺，形成P型TFET的漏区。用较简单的工艺便可形成N型TFET的漏区和P型TFET的漏区。
结合第一方面，在第一方面的第七种可能的实现方式中，第一保护层的材料为SiO2；主轴的材料为多晶硅；硬掩膜和侧壁的材料均为Si3N4；第一填充物和第二填充物的材料均为SiO2。
结合第一方面，在第一方面的第八种可能的实现方式中，衬底的材料包括Si、SOI、SiGe、Ge、GeOI中的一种。
第二方面，提供一种TFET，可通过第一方面任一种可能的实现方式制备得到。
附图说明
图1为本申请提供的一种制备TFET的流程示意图一；
图2为在衬底上形成第一保护层、主轴和硬掩膜的剖视示意图；
图3a为形成侧壁并去除未被侧壁和硬掩膜覆盖的第一保护层的剖视示意图；
图3b为在图3a基础上形成源区的剖视示意图；
图4为形成侧壁并通过离子注入工艺形成源区的剖视示意图；
图5为使用第一填充物进行填充并进行平坦化的剖视示意图；
图6a为去除位于隔离结构上方的侧壁、主轴，并通过倾斜离子注入工艺形成漏区的剖视示意图；
图6b为在图6a基础上去除露出的第一保护层的剖视示意图；
图7为使用第二填充物进行填充、平坦化并去除侧壁以及侧壁覆盖的第一保护层暴露出衬底的剖视示意图；
图8为在暴露出衬底的区域形成栅介质层和栅极的剖视示意图；
图9为本申请提供的一种制备TFET的流程示意图二；
图10a为在衬底上的P型TFET和N型TFET区域形成第一保护层、主轴和硬掩膜的俯视示意图；
图10b为图10a中A3A4向以及A1A2向的剖视示意图；
图11a为形成绝缘膜层以及露出N型TFET区域的第一光刻胶层的俯视示意图；
图11b为图11a中B3B4向以及B1B2向的剖视示意图；
图12a为在N型TFET的主轴四周形成侧壁的俯视示意图；
图12b为图12a中C3C4向以及C1C2向的剖视示意图；
图13a为形成N型TFET的源区的俯视示意图；
图13b为图13a中D3D4向以及D1D2向的剖视示意图；
图14a为形成覆盖N型TFET区域的第二光刻胶层的俯视示意图；
图14b为图14a中E3E4向以及E1E2向的剖视示意图；
图15a为在P型TFET的主轴四周形成侧壁的俯视示意图；
图15b为图15a中F3F4向以及F1F2向的剖视示意图；
图16a为形成P型TFET的源区的俯视示意图；
图16b为图16a中G3G4向以及G1G2向的剖视示意图；
图17a为经过平坦化工艺露出主轴以及侧壁的俯视示意图；
图17b为图17a中H3H4向以及H1H2向的剖视示意图；
图18a为形成覆盖位于有源区中侧壁的第三光刻胶层的俯视示意图；
图18b为图18a中I3I4向以及I1I2向的剖视示意图；
图19a为去除未被第三光刻胶层覆盖的侧壁并去除主轴的俯视示意图；
图19b为图19a中J3J4向以及J1J2向的剖视示意图；
图20a形成露出N型TFET区域的第四光刻胶层的俯视示意图；
图20b为图20a中K3K4向以及K1K2向的剖视示意图；
图21a形成覆盖N型TFET区域的第五光刻胶层的俯视示意图；
图21b为图21a中L3L4向以及L1L2向的剖视示意图；
图22a为经过平坦化工艺露出侧壁，并去除侧壁以及被侧壁覆盖的第一保护层的俯视示意图；
图22b为图22a中M3M4向以及M1M2向的剖视示意图；
图23形成栅介质层和栅极的剖视示意图；
图24a为形成覆盖衬底的第二保护层以及覆盖N型TFET区域的第二光刻胶层的俯视示意图；
图24b为图24a中N3N4向以及N1N2向的剖视示意图；
图25a为去除未被第二光刻胶层覆盖的第二保护层并去除第二光刻胶层的俯视示意图；
图25b为图25a中O3O4向以及O1O2向的剖视示意图；
图26a为在P型TFET的主轴四周形成侧壁并形成P型TFET的源区的俯视示意图；
图26b为图26a中P3P4向以及P1P2向的剖视示意图；
图27为本申请提供的一种NTFET和P型TFET的的剖视示意图。
附图标记：
10-衬底；20-隔离结构；30-第一保护层；40-主轴；50-硬掩膜；60-侧壁；70-栅介质层；80-栅极；91-第一光刻胶层；92-第二光刻胶层；93-第三光刻胶层；94-第四光刻胶层；95-第五光刻胶层；102-源区；103-漏区；110-第二保护层；601-绝缘膜层。
具体实施方式
本申请提供一种TFET的制备方法，如图1所示，包括如下步骤：
S10、如图2所示，在衬底10上形成至少覆盖有源区的第一保护层30；其中，衬底10由隔离结构20定义出有源区。
衬底10的材料可以为体硅(Si)、绝缘体上的硅(SOI)、锗硅(SiGe)、锗(Ge)、绝缘体上的锗(GeOI)等。
隔离结构20可通过浅槽隔离(shallow tunnel isolation,简称STI)工艺形成。STI工艺，即：通过对衬底10进行光刻、刻蚀工艺，形成浅沟槽；在浅沟槽中进行填充，形成隔离结构20。
第一保护层30的材料例如可以为二氧化硅(SiO2)。
第一保护层30的厚度可以在2～10nm范围内。一方面，2～10nm厚度的第一保护层可对有源区进行保护，另一方面，可避免第一保护层太厚对衬底产生较大的应力。
需要说明的是，图2以第一保护层30仅覆盖有源区进行示意。
此外，有源区可以是掺杂的，也可以是不掺杂的。本申请附图以有源区是掺杂的进行示意。
S11、如图2所示，在形成有第一保护层30的衬底10上形成主轴40以及覆盖主轴40的硬掩膜50，主轴40覆盖有源区的漏区所在的区域；其中，主轴40具有倾斜侧面，且主轴40的下表面面积大于上表面面积。
主轴40的材料例如可以为多晶硅。
硬掩膜50的材料例如可以为氮化硅(Si3N4)、氮氧化硅(SiON)等。或者，硬掩膜50也可以为氧化硅/氮化硅/氧化硅的层叠结构。
需要说明的是，主轴40的下表面为主轴40靠近衬底10的表面，主轴40的上表面为主轴40远离衬底10的表面。
S12、如图3a-图3b所示，或者如图4所示，在主轴40四周形成侧壁60，并对未被侧壁60和硬掩膜50覆盖的有源区进行掺杂工艺，形成源区102。
侧壁60的材料例如可以为Si3N4、SiON等。
由于对未被侧壁60和硬掩膜50覆盖的有源区进行掺杂工艺后形成源区102，而硬掩膜50下方的主轴40对应的是漏区，因而，侧壁60对应的则是栅区，侧壁60的宽度决定栅极的宽度。对于侧壁60而言，其宽度均匀一致。
对未被侧壁60和硬掩膜50覆盖的有源区进行掺杂工艺，形成源区102可以通过如下方式实现：
方式一：如图3a所示，去除未被侧壁60和硬掩膜50覆盖的第一保护层30；之后对露出的衬底10进行刻蚀，形成源区沟槽；如图3b所示，在源区沟槽内外延生长含P型离子或含N型离子的材料，形成源区102。
其中，当TFET为N型TFET时，源区102掺杂P型离子，在此情况下，可在源区沟槽内外延生长例如含硼(B)的锗硅(SiGe)。当TFET为P型TFET时，源区102掺杂N型离子，在此情况下，可在源区沟槽内外延生长例如含磷(P)的硅。
采用方式一可以获得更好的掺杂分布(doping profile)，利于提升器件特性。此外，外延生长材料如果跟衬底10不同，则可以形成异质结(hetero-juction)，其带来的能带调制效果可以进一步提升器件特性。
方式二：如图4所示，对未被侧壁60和硬掩膜50覆盖的有源区进行离子注入工艺，形成源区102；去除源区102上方的第一保护层30。第一保护层30可在离子注入过程中保护衬底10，避免衬底10的表面出现缺陷，而在经过离子注入后，第一保护层30会存在缺陷，因而，将第一保护层30去除，可避免对TFET性能的影响。
其中，当TFET为N型TFET时，源区102注入P型离子，例如B、二氟化硼(BF2) 等。当TFET为P型TFET时，源区102注入N型离子，例如P、砷(AS)等。
S13、如图5所示，使用第一填充物进行填充，并进行平坦化的工艺，露出主轴40以及侧壁60。
S14、如图6a所示，去除位于隔离结构20上方的侧壁60、主轴40，并进行倾斜离子注入工艺，形成漏区103，使漏区103在衬底10上的正投影与位于有源区的侧壁60在衬底10上的正投影无交叠。
其中，倾斜角度θ可设置为0°～30°范围内。
当TFET为N型TFET时，漏区103注入N型离子，例如P、AS等。当TFET为P型TFET时，漏区103注入P型离子，例如B、BF2等。
如图6b所示，在形成漏区103之后，可去除漏区103上方的第一保护层30。以避免经过离子注入后第一保护层30存在缺陷。
当然，在形成漏区103后，可进行退火工艺，及激活源区102、漏区103中的离子。其中，退火工艺可发生在形成栅极80之前。
S15、如图7所示，使用第二填充物进行填充，并进行平坦化的工艺，露出位于有源区的侧壁60，并去除侧壁60以及被侧壁60覆盖的第一保护层30，暴露出衬底10。
第一填充物和第二填充物可以为同一种材料，例如SiO2。可利用正硅酸乙酯(TEOS)、硅氮烷(TOSZ)进行如上填充工艺；也可利用可流动化学气相沉积(Flowable Chemical Vapor Deposition，简称FCVD)、高密度等离子体化学气相沉积(High Density Plasma Chemical Vapor Deposition，简称HDP-CVD)、高深宽比化学气相沉积(High Aspect Ratio Process，简称HARP)工艺进行如上的填充工艺。
S16、如图8所示，在暴露出衬底10的区域，形成栅介质层70和栅极80。
本申请提供一种TFET的制备方法，通过形成具有倾斜侧面的主轴40，可使形成的侧壁60也倾斜，这样可基于自对准方式，通过倾斜离子注入工艺形成漏区103时，可使漏区103在衬底10上的正投影与位于有源区的侧壁60在衬底10上的正投影无交叠，且可以精确控制无交叠区域，从而在去除侧壁60形成栅极80后，使得栅极80和漏区103无重叠区域，进而改善漏电流。其中，在形成漏区103过程中，由于不受光刻工艺限制，因而，可制作精度要求较高的TFET。
实施例一，提供一种TFET的制备方法，可同时制备N型TFET和P型TFET，如图9所示，包括如下步骤：
S20、如图10a和图10b所示，在衬底10上形成覆盖有源区的第一保护层30，其中，衬底10由隔离结构20定义出有源区。
第一保护层30的材料可以为SiO2，厚度可以在2～10nm范围内。
S21、如图10a和图10b所示，在形成有第一保护层30的衬底10上形成主轴40以及覆盖主轴40的硬掩膜50，主轴40覆盖有源区的漏区所在的区域；其中，主轴40具有倾斜侧面，且主轴40的下表面面积大于上表面面积。
即，主轴40的形状可以为棱台。
主轴40的材料可以为多晶硅，硬掩膜的材料可以为Si3N4。
具体的，形成主轴40和硬掩膜50可以是：先在形成有第一保护层30的衬底10依次沉积多晶硅薄膜和Si3N4薄膜，并通过光刻工艺形成光刻胶，光刻胶位于漏区所 在的区域且延伸至隔离结构20上方；采用刻蚀工艺刻蚀多晶硅薄膜和Si3N4薄膜，形成具有倾斜侧面的主轴40和位于主轴40上的硬掩膜50；去除光刻胶。
S22、如图11a和图11b所示，在形成有主轴40和硬掩膜50的衬底10上形成绝缘膜层601，并在绝缘膜层601上形成第一光刻胶层91，第一光刻胶层601露出N型TFET区域。
绝缘膜层601的材料可以为Si3N4。
具体的，可先沉积Si3N4，形成绝缘膜层601，然后通过光刻工艺形成第一光刻胶层91，第一光刻胶层91覆盖P型TFET区域，而露出N型TFET区域。
S23、如图12a和图12b以及图13a和图13b所示，利用刻蚀工艺对未被第一光刻胶层91覆盖的绝缘膜层601进行刻蚀，在N型TFET的主轴40四周形成侧壁60，并对未被侧壁60和硬掩膜50覆盖的有源区进行掺杂工艺，形成N型TFET的源区102；去除第一光刻胶层91。
具体的，可利用各向同性刻蚀工艺对未被第一光刻胶层91覆盖的绝缘膜层601进行刻蚀，在N型TFET的主轴40四周形成侧壁60。
之后可采用如下两种方式形成N型TFET的源区102。
方式一，去除未被侧壁60和硬掩膜50覆盖的第一保护层30，并对露出的衬底10进行刻蚀，形成源区沟槽；在源区沟槽内外延生长含B的SiGe材料，形成N型TFET的源区102。
方式二，对未被侧壁60和硬掩膜50覆盖的有源区进行离子注入工艺，注入的离子可以为B、BF2等，形成N型TFET的源区102；去除N型TFET的源区102上方的第一保护层30。
S24、如图14a和图14b所示，形成第二光刻胶层92，第二光刻胶层92覆盖N型TFET区域。
S25、如图15a和图15b以及图16a和图16b所示，利用刻蚀工艺对未被第二光刻胶层92覆盖的绝缘膜层601进行刻蚀，在P型TFET的主轴40四周形成侧壁60，并对未被侧壁60和硬掩膜50覆盖的有源区进行掺杂工艺，形成P型TFET的源区102；去除第二光刻胶层92。
具体的，可利用各向同性刻蚀工艺对未被第二光刻胶层92覆盖的绝缘膜层601进行刻蚀，在P型TFET的主轴40四周形成侧壁60。
之后可采用如下两种方式形成P型TFET的源区102。
方式一，去除未被侧壁60和硬掩膜50覆盖的第一保护层30，并对露出的衬底10进行刻蚀，形成源区沟槽；在源区沟槽内外延生长含P的硅材料，形成P型TFET的源区102。
方式二，对未被侧壁60和硬掩膜50覆盖的有源区进行离子注入工艺，注入的离子可以为P、AS等，形成P型TFET的源区102；去除P型TFET的源区102上方的第一保护层30。
S26、如图17a和图17b所示，使用SiO2进行填充，并进行平坦化的工艺，露出主轴40以及侧壁60。
具体的，可先沉积SiO2，将器件覆盖；之后利用平坦化工艺(可以通过刻蚀和化 学机械研磨并用的方式)去除硬掩膜50，而露出主轴40以及侧壁60。
S27、如图18a和图18b以及图19a和图19b所示，形成第三光刻胶层93，第三光刻胶层93覆盖P型TFET和N型TFET区域中位于有源区的侧壁60,通过刻蚀工艺去除未被第三光刻胶层93覆盖的侧壁60，并去除主轴40。
具体的，可采用磷酸(H3PO4)去除未被第三光刻胶层93覆盖的侧壁60；采用四甲基氢氧化铵(TMAH)或者氨水(NH4OH)溶液去除主轴40。
S28、如图20a和图20b所示，形成第四光刻胶层94，第四光刻胶层94露出N型TFET区域，进行倾斜离子注入工艺，形成N型TFET的漏区103。
其中，倾斜角度θ可设置为0°～30°的范围内。注入的离子可以为P、AS等。
在形成N型TFET的漏区103之后，可去除N型TFET的漏区103上方的第一保护层30。
S29、如图21a和图21b所示，形成第五光刻胶层95，第五光刻胶层95覆盖N型TFET区域，进行倾斜离子注入工艺，形成P型TFET的漏区103。
其中，倾斜角度θ可设置为0°～30°。注入的离子可以为B、BF2等
在形成P型TFET的漏区103之后，可去除P型TFET的漏区103上方的第一保护层30。
当然，在形成N型TFET和P型TFET的漏区103后，可进行退火工艺，以激活源区102、漏区103中的离子。
S30、如图22a和图22b所示，使用SiO2进行填充，并进行平坦化的工艺，露出位于有源区的侧壁60，并去除侧壁60以及被侧壁60覆盖的第一保护层30，暴露出衬底10。
具体的，可先沉积SiO2，将器件覆盖；之后利用平坦化工艺去除侧壁60以及被侧壁60覆盖的第一保护层30，而暴露出衬底10。
S31、如图23所示，在暴露出衬底10的区域，形成栅介质层70和栅极80。
具体的，可利用高k介电层+金属栅(High-k metal gate，HKMG)制作栅介质层70和栅极80。
需要说明的是，上述以先形成N型TFET的源区102，再形成P型TFET的源区102，先形成N型TFET的漏区103，再形成P型TFET的漏区103进行说明。但本申请并不限于此，在形成源区102时，可以先形成N型TFET的源区102，再形成P型TFET的源区102，也可以先形成P型TFET的源区102，再形成N型TFET的源区102。同理，在形成漏区103时，可以先形成N型TFET的漏区103，再形成P型TFET的漏区103，也可以先形成P型TFET的漏区103，再形成N型TFET的漏区103。
实施例二，与实施例一的不同在于，可通过如下步骤S40～S42替换实施例一中的步骤S24～S25。
S40、如图24a和图24b所示，形成覆盖衬底10的第二保护层110，在第二保护层110上形成第二光刻胶层92，第二光刻胶层92覆盖N型TFET区域。
第二保护层110的材料可以为SiO2。具体可通过沉积工艺形成第二保护层110。
S41、如图25a和图25b所示，通过刻蚀工艺去除未被第二光刻胶层92覆盖的第二保护层110，并去除第二光刻胶层92。
具体的，可例如各向同性刻蚀工艺，例如浸泡氢氟酸方法，去除未被第二光刻胶层92覆盖的第二保护层110。
S42、如图26a和图26b所示，利用刻蚀工艺对未被第二保护层110覆盖的绝缘膜层601进行刻蚀，在P型TFET的主轴40四周形成侧壁，并对未被侧壁60和硬掩膜50覆盖的有源区进行掺杂工艺，形成P型TFET的源区102；去除第二保护层110(参见图16a和图16b所示)。
具体的，可利用各向同性刻蚀工艺对未被第二保护层110覆盖的绝缘膜层601进行刻蚀，在P型TFET的主轴40四周形成侧壁60。
之后可采用如下两种方式形成P型TFET的源区102。
方式一，去除未被侧壁60和硬掩膜50覆盖的第一保护层30，并对露出的衬底10进行刻蚀，形成源区沟槽；在源区沟槽内外延生长含P的硅材料，形成P型TFET的源区102。
方式二，对未被侧壁60和硬掩膜50覆盖的有源区进行离子注入工艺，注入的离子可以为P、AS等，形成P型TFET的源区102；去除P型TFET的源区102上方的第一保护层30。
基于实施例一和实施例二，如图27所示，还可形成金属连线。
需要说明的是，本申请的TFET制备方法，也适用于制备鳍形结构的TFET，本申请附图仅以平面结构的TFET进行示意。
本申请还提供一种TFET，可通过上述的制备方法制备得到。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种TFET的制备方法，其特征在于，包括：
    在衬底上形成至少覆盖有源区的第一保护层；其中，所述衬底由隔离结构定义出所述有源区；
    在形成有所述第一保护层的衬底上形成主轴以及覆盖所述主轴的硬掩膜，所述主轴覆盖所述有源区的漏区所在的区域；其中，所述主轴具有倾斜侧面，且所述主轴的下表面面积大于上表面面积；
    在所述主轴四周形成侧壁，并对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成源区；
    使用第一填充物进行填充，并进行平坦化的工艺，露出所述主轴以及所述侧壁；
    去除位于所述隔离结构上方的所述侧壁、所述主轴，并进行倾斜离子注入工艺，形成漏区，使所述漏区在所述衬底上的正投影与位于所述有源区的所述侧壁在所述衬底上的正投影无交叠；
    使用第二填充物进行填充，并进行平坦化的工艺，露出位于所述有源区的所述侧壁，并去除所述侧壁以及被所述侧壁覆盖的所述第一保护层，暴露出所述衬底；
    在暴露出所述衬底的区域，形成栅介质层和栅极。
  2. 根据权利要求1所述的制备方法，其特征在于，对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成源区，包括：
    去除未被所述侧壁和所述硬掩膜覆盖的所述第一保护层，并对露出的所述衬底进行刻蚀，形成源区沟槽；
    在所述源区沟槽内外延生长含P型离子或含N型离子的材料，形成所述源区；或者，
    对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行离子注入工艺，形成所述源区；
    去除所述源区上方的所述第一保护层。
  3. 根据权利要求1所述的制备方法，其特征在于，进行倾斜离子注入工艺形成漏区之后，使用所述第二填充物进行填充之前，所述制备方法还包括：去除所述漏区上方的所述第一保护层。
  4. 根据权利要求1所述的制备方法，其特征在于，所述第一保护层的厚度在2～10nm之间。
  5. 根据权利要求1-4任一项所述的制备方法，其特征在于，在N型和P型TFET同时制备的情况下，在所述主轴四周形成侧壁，并对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成源区，包括：
    在形成有所述主轴和所述硬掩膜的衬底上，形成绝缘膜层，并在所述绝缘膜层上形成第一光刻胶层，所述第一光刻胶层露出N型TFET区域；
    利用刻蚀工艺对未被所述第一光刻胶层覆盖的所述绝缘膜层进行刻蚀，在所述N型TFET区域的所述主轴四周形成侧壁，并对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成所述N型TFET的所述源区；去除所述第一光刻胶层；
    形成第二光刻胶层，所述第二光刻胶层覆盖N型TFET区域；
    利用刻蚀工艺对未被所述第二光刻胶层覆盖的所述绝缘膜层进行刻蚀，在所述P型TFET区域的所述主轴四周形成侧壁，并对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成所述P型TFET的所述源区；去除所述第二光刻胶层。
  6. 根据权利要求1-4任一项所述的制备方法，其特征在于，在N型和P型TFET同时制备的情况下，在所述主轴四周形成侧壁，并对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成源区，包括：
    在形成有所述主轴和所述硬掩膜的衬底上，形成绝缘膜层，并在所述绝缘膜层上形成第一光刻胶层，所述第一光刻胶层露出N型TFET区域；
    利用刻蚀工艺对未被所述第一光刻胶层覆盖的所述绝缘膜层进行刻蚀，在所述N型TFET区域的所述主轴四周形成侧壁，并对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成所述N型TFET的所述源区；去除所述第一光刻胶层；
    形成覆盖所述衬底的第二保护层，并在所述第二保护层上形成第二光刻胶层，所述第二光刻胶层覆盖N型TFET区域；
    通过刻蚀工艺去除未被所述第二光刻胶层覆盖的所述第二保护层，并去除所述第二光刻胶层；
    利用刻蚀工艺对未被所述第二保护层覆盖的所述绝缘膜层进行刻蚀，在所述P型TFET区域的所述主轴四周形成侧壁，并对未被所述侧壁和所述硬掩膜覆盖的所述有源区进行掺杂工艺，形成所述P型TFET的所述源区；去除所述第二保护层。
  7. 根据权利要求5或6所述的制备方法，其特征在于，去除位于所述隔离结构上方的所述侧壁、所述主轴，并进行倾斜离子注入工艺，形成漏区，包括：
    形成第三光刻胶层，所述第三光刻胶层覆盖所述P型TFET区域和所述N型TFET区域中位于所述有源区的所述侧壁；
    通过刻蚀工艺去除未被所述第三光刻胶层覆盖的所述侧壁，并去除所述主轴；
    形成第四光刻胶层，所述第四光刻胶层露出所述N型TFET区域，进行倾斜离子注入工艺，形成所述N型TFET的所述漏区；
    形成第五光刻胶层，所述第五光刻胶层覆盖所述N型TFET区域，进行倾斜离子注入工艺，形成所述P型TFET的所述漏区。
  8. 根据权利要求1所述的制备方法，其特征在于，所述第一保护层的材料为SiO2；所述主轴的材料为多晶硅；所述硬掩膜和所述侧壁的材料均为Si3N4；所述第一填充物和所述第二填充物的材料均为SiO2。
  9. 根据权利要求1所述的制备方法，其特征在于，所述衬底的材料包括Si、SOI、SiGe、Ge、GeOI中的一种。
  10. 一种TFET，其特征在于，包括：通过权利要求1-9任一项所述的制备方法制备得到。
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