WO2022041896A1 - 一种半导体结构及其制备方法 - Google Patents

一种半导体结构及其制备方法 Download PDF

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Publication number
WO2022041896A1
WO2022041896A1 PCT/CN2021/096917 CN2021096917W WO2022041896A1 WO 2022041896 A1 WO2022041896 A1 WO 2022041896A1 CN 2021096917 W CN2021096917 W CN 2021096917W WO 2022041896 A1 WO2022041896 A1 WO 2022041896A1
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WIPO (PCT)
Prior art keywords
layer
insulating layer
semiconductor
semiconductor substrate
trench
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PCT/CN2021/096917
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English (en)
French (fr)
Inventor
吴公一
陆勇
陈龙阳
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长鑫存储技术有限公司
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Priority to EP21859740.9A priority Critical patent/EP4195273A4/en
Priority to US17/444,085 priority patent/US20220059539A1/en
Publication of WO2022041896A1 publication Critical patent/WO2022041896A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • Each memory cell typically includes a transistor and a capacitor.
  • the word line voltage on the transistor can control the turning on and off of the transistor, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor.
  • the size of the transistor is getting smaller, and the channel electric field strength of the transistor is continuously increasing. can lead to device reliability issues. For example, the device Snapback breakdown, the latch-up effect of CMOS circuits and the reduction of device life, etc.
  • the technical problem to be solved by the present application is to provide a semiconductor structure and a preparation method thereof, which can avoid substrate leakage current and improve the reliability of the semiconductor structure.
  • the present application provides a method for preparing a semiconductor structure, which includes the following steps: providing a semiconductor substrate; forming a trench on the semiconductor substrate; forming a first insulating layer, the first insulating layer at least covering the inner wall of the trench; forming a channel layer, the channel layer covering at least the inner wall of the first insulating layer; forming a second insulating layer, the second insulating layer covering at least the inner wall of the channel layer;
  • the trench is filled with a word line structure; part of the semiconductor substrate, part of the first insulating layer and part of the channel layer is removed, and a recessed area is formed on the outer sidewall of the second insulating layer; source and drain are formed in the recessed area , the source and drain are electrically connected to the channel layer.
  • the semiconductor substrate has a plurality of independent active regions, the active regions are isolated by a shallow trench isolation structure, and the trenches are formed in the active regions Inside.
  • the word line structure includes a conductive structure and a third insulating layer on the conductive structure, and the conductive structure includes a barrier layer and a first conductive layer.
  • the step of forming the channel layer further includes: forming a semiconductor layer at least on the inner wall of the first insulating layer; doping the semiconductor layer to form the channel layer .
  • the method for doping the semiconductor layer is to use an ion implantation process to dope the semiconductor layer.
  • the first insulating layer further covers a region above the semiconductor substrate, and the channel layer further covers a surface of the first insulating layer located above the semiconductor substrate, so The second insulating layer also covers the surface of the channel layer above the semiconductor substrate, and the step of filling the word line structure in the trench further includes the step of: forming the barrier layer on the surface of the second insulating layer , the barrier layer also covers the surface of the second insulating layer above the semiconductor substrate; a first conductive layer is formed on the surface of the barrier layer, and the first conductive layer fills the trench; the first conductive layer is etched back layer and the barrier layer, the top surfaces of the first conductive layer and the barrier layer are lower than the top surface of the semiconductor substrate, and the film layer above the semiconductor substrate is removed to form the first conductive layer and the barrier layer.
  • an insulating layer is used as an etch stop layer; the third insulating layer is formed, the third insulating layer fills the trench and covers the area above the semiconductor substrate; removes the
  • the materials of the first insulating layer and the third insulating layer are different.
  • the step of forming the source and drain in the recessed region further includes: depositing a second conductive layer, the second conductive layer filling the recessed region and covering the semiconductor the surface of the substrate; the second conductive layer is etched until the third insulating layer stops, so as to form the source and drain.
  • the step of depositing the second conductive layer further includes the following steps: depositing a semiconductor layer, the semiconductor layer filling the recessed area and covering the surface of the semiconductor substrate; The semiconductor layer is subjected to plasma implantation or ion doping to enhance the conductivity of the semiconductor layer.
  • the present application further provides a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate has a trench; a first insulating layer covering the inner wall of the trench; a channel layer covering the inner wall of the first insulating layer; The second insulating layer covers the inner wall of the channel layer; the word line structure is filled in the trench; the source and drain are arranged on the outer sidewall of the second insulating layer and are electrically connected to the channel layer .
  • the semiconductor substrate has a plurality of independent active regions, the active regions are isolated by a shallow trench isolation structure, and the trenches are formed in the active regions .
  • the depth of the trench is 50-300 nm, and the width of the trench is 20-100 nm.
  • the thickness of the first insulating layer is 1-30 nm.
  • the thickness of the channel layer is 3-30 nm.
  • the top surface of the first insulating layer is lower than the top surface of the channel layer, and the top surface of the channel layer is lower than the top surface of the second insulating layer noodle.
  • the upper surface of the source and drain is flush with the upper surface of the word line structure.
  • the upper surface of the source and drain is flush with the upper surface of the shallow trench isolation structure.
  • the advantage of the present application is that the first insulating layer is used to isolate the channel layer from the semiconductor substrate, thereby avoiding the generation of substrate leakage current and improving the reliability of the semiconductor structure.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for preparing a semiconductor structure of the present application
  • 2 to 14 are process flow diagrams of an embodiment of a method for fabricating a semiconductor structure of the present application.
  • 200-semiconductor substrate 201-active region; 202-shallow trench isolation structure; 210-trench; 220-first insulating layer; 230-channel layer; 240-second insulating layer; 250-word line structure 251-conductive structure; 251A-blocking layer; 251B-first conductive layer; 252-third insulating layer; 260-recessed region; 270-source and drain;
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for fabricating a semiconductor structure of the present application.
  • the method for fabricating the semiconductor structure includes the following steps: providing a semiconductor substrate; forming a trench in the semiconductor substrate; forming a first insulating layer, the first insulating layer covering at least the trench inner wall; forming a channel layer, the channel layer covering at least the inner wall of the first insulating layer; forming a second insulating layer, the second insulating layer covering at least the inner wall of the channel layer; filling the trench word line structure; removing part of the semiconductor substrate, part of the first insulating layer and part of the channel layer, forming a recessed area on the outer sidewall of the second insulating layer; forming a source and drain in the recessed area, the source and drain electrically connected to the channel layer.
  • 2 to 14 are process flow diagrams of an embodiment of a method for fabricating a semiconductor structure of the present application.
  • the semiconductor substrate 200 may be at least one of the following mentioned materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes many of these semiconductors.
  • the layer structure or the like may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like.
  • the constituent material of the semiconductor substrate 200 is single crystal silicon.
  • the semiconductor substrate 200 has a plurality of independent active regions 201 , and the active regions 201 are isolated by shallow trench isolation structures 202 .
  • the material of the shallow trench isolation structure may be an insulating material such as oxide.
  • trenches 210 are formed in the semiconductor substrate 200 .
  • the trench 210 is formed in the active region 201 . As shown in FIG. 3 , two trenches 210 are formed in one of the active regions 201 .
  • the method of forming the trench may be: forming a patterned hard mask layer 300 on the semiconductor substrate 200; using photolithography and etching processes to transfer the pattern of the hard mask layer 300 to the semiconductor On the substrate 200, the trench 210 is formed.
  • the depth of the trench 210 may be 50-300 nm, and the width may be 20-100 nm, so as to provide enough space for the structure formed in the subsequent process.
  • the hard mask layer is not removed to protect the semiconductor substrate 200 in subsequent processes.
  • a first insulating layer 220 is formed, and the first insulating layer 220 at least covers the inner wall of the trench 210 .
  • the first insulating layer 220 can be formed by an atomic layer deposition (ALD) process.
  • the first insulating layer 220 formed by this process has a dense structure and strong blocking effect.
  • the first insulating layer 220 is a nitride, such as silicon nitride.
  • the first insulating layer 220 can also be other insulating materials, such as oxide.
  • the thickness of the first insulating layer 220 is in the range of 1-30 nm, so that it can effectively block leakage current and avoid occupying too much space of the active region 201, thereby affecting the performance of the semiconductor device.
  • the first insulating layer 220 not only covers the inner wall of the trench 210 but also covers the surface of the semiconductor substrate 200 . Specifically, in this embodiment, since the surface of the semiconductor substrate 200 has the hard mask layer 300, the first insulating layer 220 not only covers the inner wall of the trench 210, but also covers the semiconductor substrate The hard mask layer 300 on the surface of the bottom 200 .
  • a channel layer 230 is formed, and the channel layer 230 at least covers the inner wall of the first insulating layer 220 . Further, the channel layer 230 not only covers the inner wall of the first insulating layer 220 , but also covers the upper surface of the first insulating layer 220 above the semiconductor substrate 200 .
  • the method for forming the channel layer 230 is:
  • a semiconductor layer is formed at least on the inner wall of the first insulating layer 220 .
  • the semiconductor layer not only covers the inner wall of the first insulating layer 220 , but also covers the first insulating layer above the semiconductor substrate 200 .
  • the semiconductor layer may be formed by a low pressure chemical vapor deposition method (LPCVD), or may be formed by a low pressure chemical vapor deposition method and an epitaxial process.
  • the semiconductor layers include but are not limited to structural layers such as silicon and germanium.
  • the semiconductor layer is doped to form the channel layer 230 .
  • the method for doping the semiconductor layer is to use an ion implantation process to dope the semiconductor layer.
  • the semiconductor layer is doped with boron (B) by an ion implantation process to form the channel layer 230 .
  • a rapid thermal process is performed on the channel layer 230 to repair the lattice damage of the channel layer 230 and increase the carriers of the channel layer 230 mobility, ensuring semiconductor device performance.
  • the thickness of the channel layer 230 is 3-30 nm, so that the channel layer 230 can not only meet the requirements of the semiconductor device, but also avoid occupying the space of the active region and affecting the formation of the subsequent word line structure.
  • a second insulating layer 240 is formed, and the second insulating layer 240 at least covers the inner wall of the channel layer 230 .
  • the second insulating layer 240 serves as an insulating layer between the subsequent word line structure and the channel layer.
  • the thickness of the second insulating layer 240 may be 15-40 angstroms. If it is too thin, it will not function as insulation between the word line structure and the channel layer. If it is too thick, the threshold voltage of the semiconductor device will be increased. , which affects the performance of semiconductor devices.
  • the material of the second insulating layer 240 may be oxide or high-K dielectric material.
  • the oxide can be silicon oxide
  • the high-K dielectric material can be HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO or Ta 2 O 5 .
  • the material of the second insulating layer 240 is different from the material of the first insulating layer 220, so that in the subsequent process, under the same etching condition, the second insulating layer 240 and the first insulating layer 220 has different etch rates, thereby enabling selective etching.
  • the second insulating layer 240 not only covers the inner wall of the channel layer 230 , but also covers the upper surface of the channel layer 230 above the semiconductor substrate 200 .
  • the trench 210 is filled with a word line structure 250
  • the word line structure 250 includes a conductive structure 251 and a third insulating layer 252 on the conductive structure 251 .
  • the conductive structure 251 includes a barrier layer 251A and a first conductive layer 251B.
  • the material of the third insulating layer 252 is different from the material of the first insulating layer 220, so that in the subsequent etching process, under the same etching condition, the third insulating layer 252 and the first insulating layer 220 has different etch rates, thereby enabling selective etching.
  • the method for filling the word line structure 250 in the trench 210 includes the following steps:
  • a barrier layer 251A is formed on the surface of the second insulating layer 240 , and the barrier layer 251A also covers the upper surface of the second insulating layer 240 above the semiconductor substrate 200 .
  • the barrier layer 251A may be a TiN layer or a composite layer of Ti and TiN.
  • the thickness of the barrier layer 251A may be 2 ⁇ 7 nm.
  • a first conductive layer 251B is formed on the barrier layer 251A, the first conductive layer 251B fills the trench 210 and covers the upper surface of the barrier layer 251A above the semiconductor substrate 200 .
  • the first conductive layer 251B may be a metal tungsten layer.
  • the chemical vapor deposition (CVD) method is used to form the first conductive layer 251B, and chemical mechanical polishing is performed to make the surface of the first conductive layer 251B flat.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • dry etching is used to etch back the first conductive layer 251B and the barrier layer 251A so that the top surfaces of the first conductive layer 251B and the barrier layer 251A are lower than the semiconductor substrate 200's top.
  • a part of the trench 210 is filled with the conductive structure 251, and part of the sidewall of the second insulating layer 240 is exposed.
  • the distance from the upper surface of the first conductive layer 251B to the top surface of the semiconductor substrate 200 may be 20-150 nm.
  • the film layer above the semiconductor substrate 200 is removed, and the first insulating layer 220 is used as an etch stop layer. Specifically, the first conductive layer 251B, the barrier layer 251A, the second insulating layer 240 and the channel layer 230 above the semiconductor substrate 200 are removed, and the first insulating layer 220 remains.
  • a wet etching process is used to remove the remaining barrier layer 251A on the sidewall of the second insulating layer 240 .
  • a third insulating layer 252 is formed, the third insulating layer 252 fills the trench 210 and covers the area above the semiconductor substrate 200 . Specifically, in this embodiment, the third insulating layer 252 fills the trench 210 and covers the surface of the first insulating layer 220 located above the semiconductor substrate 200 .
  • the material of the third insulating layer 252 may be SiON.
  • the film layer above the semiconductor substrate 200 is removed, and the semiconductor substrate 200 is used as an etch stop layer.
  • dry etching is used to remove the third insulating layer 252 , the first insulating layer 220 and the hard mask layer 300 above the semiconductor substrate 200 to expose the semiconductor substrate 200 .
  • the top surfaces of the first insulating layer 220 , the channel layer 230 , the second insulating layer 240 and the third insulating layer 252 are flush with the top surface of the semiconductor substrate 200 .
  • part of the semiconductor substrate 200 , part of the first insulating layer 220 and part of the channel layer 230 are removed, and a recessed region 260 is formed on the outer sidewall of the second insulating layer 240 .
  • a dry etching process is used for etching.
  • the third insulating layer 252 and the second insulating layer 240 may be selected to be etched with an etchant having a low etching rate, so as to prevent the third insulating layer 252 and the second insulating layer 240 from being removed.
  • the etching rate of the etching substance to the first insulating layer 220 is greater than the etching rate of the semiconductor substrate 200 and the channel layer 230 , and the etching rate of the semiconductor substrate 200 and the channel layer 230 The rate is higher than the etching rate of the second insulating layer 240 and the third insulating layer 252 , so that a recessed region 260 can be formed on the outer sidewall of the second insulating layer 240 .
  • the etching depth of the first insulating layer 220 is 10-80 nm, and the etching depth of the semiconductor substrate 200 and the channel layer 230 is 5-60 nm.
  • the remaining thickness of the third insulating layer 252 is 50-80 nm.
  • source and drain electrodes 270 are formed in the recessed regions 260 , and the source and drain electrodes 270 are electrically connected to the channel layer 230 .
  • the source and drain electrodes 270 are made of a conductive material, which fills the recessed region 260 .
  • the material of the source and drain electrodes 270 includes, but is not limited to, polysilicon.
  • the method for forming the source and drain 270 in the recessed region 260 includes the following steps:
  • a semiconductor layer 400 is deposited, the semiconductor layer 400 fills the recessed region 260 and covers the surface of the semiconductor substrate 200 .
  • the semiconductor layer 400 may be deposited by a chemical vapor deposition (CVD) process, and the material of the semiconductor layer 400 includes, but is not limited to, polysilicon, germanium, and the like. In this embodiment, the material of the semiconductor layer 400 is polysilicon.
  • plasma implantation or ion doping is performed on the semiconductor layer 400 to enhance the conductivity of the semiconductor layer 400 to form a second conductive layer.
  • one or more of P ions and As ions can be selected for the plasma implantation.
  • the second conductive layer can be annealed to repair lattice damage and improve device performance.
  • planarization process is performed on the second conductive layer to make its surface flat.
  • the planarization process may be chemical mechanical polishing (CMP).
  • the second conductive layer is etched until the third insulating layer 252 stops to form the source and drain electrodes 270 . In this step, only the second conductive layer located in the recessed region 260 remains as the source and drain electrodes 270 .
  • the remaining second conductive layer is used as the source and drain electrodes 270 of the transistor, the word line structure 250 is used as the gate of the transistor, and the second insulating layer 240 is used as the gate insulating layer.
  • the first insulating layer 220 isolates the channel layer 230 from the semiconductor substrate 200, thereby avoiding the generation of substrate leakage current and improving the reliability of the semiconductor structure.
  • the present application also provides a semiconductor structure prepared by the above method.
  • the semiconductor structure includes a semiconductor substrate 200 , a first insulating layer 220 , a channel layer 230 , a second insulating layer 240 , a word line structure 250 , and a source/drain Pole 270.
  • the semiconductor substrate 200 has trenches 210 .
  • the semiconductor substrate 200 has a plurality of independent active regions 201 , the active regions 201 are isolated by shallow trench isolation structures 202 , and the trenches 210 are formed in the active regions 201 Inside.
  • the depth of the trench 210 is 50-300 nm, and the width is 20-100 nm, so as to provide enough space for the semiconductor structure formed in the trench 210 .
  • the semiconductor substrate 200 includes a plurality of the trenches 210 . For example, as shown in FIG. 14 , two trenches 210 are formed in one of the active regions 201 .
  • the first insulating layer 220 covers the inner wall of the trench 210 .
  • the first insulating layer 220 is a nitride, such as silicon nitride.
  • the first insulating layer 220 can also be other insulating materials, such as oxide.
  • the thickness of the first insulating layer 220 is 1-30 nm, so that it can not only effectively block leakage current, but also avoid occupying too much space of the active region 201, thereby affecting the performance of the semiconductor device.
  • the channel layer 230 covers the inner wall of the first insulating layer 220 .
  • the channel layer 230 may be formed of boron-doped silicon material.
  • the thickness of the channel layer 230 is 3-30 nm, so that the channel layer 230 can not only meet the requirements of the semiconductor device, but also avoid occupying the space of the active region and affecting the formation of the subsequent word line structure.
  • the second insulating layer 240 covers the inner wall of the channel layer 230 .
  • the second insulating layer 240 serves as an insulating layer between the word line structure 250 and the channel layer 230 .
  • the thickness of the second insulating layer 240 may be 15-40 angstroms. If it is too thin, it will not function as insulation between the word line structure and the channel layer. If it is too thick, the threshold voltage of the semiconductor device will be increased. , which affects the performance of semiconductor devices.
  • the material of the second insulating layer 240 may be oxide or high-K dielectric material.
  • the oxide can be silicon oxide
  • the high-K dielectric material can be HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , La 2 O 3 , ZrO 2 , LaAlO or Ta 2 O 5 .
  • the material of the second insulating layer 240 is different from the material of the first insulating layer 220, so that in the subsequent process, under the same etching condition, the second insulating layer 240 and the first insulating layer 220 has different etch rates, thereby enabling selective etching.
  • the word line structures 250 are filled in the trenches 210 .
  • the word line structure 250 includes a conductive structure 251 and a third insulating layer 252 on the conductive structure 251 .
  • the conductive structure 251 includes a barrier layer 251A and a first conductive layer 251B.
  • the barrier layer 251A may be a TiN layer or a composite layer of Ti and TiN.
  • the thickness of the barrier layer 251A may be 2 ⁇ 7 nm.
  • the first conductive layer 251B may be a metal tungsten layer.
  • the top surfaces of the first conductive layer 251B and the barrier layer 251A are lower than the top surface of the semiconductor substrate 200 .
  • the distance from the first conductive layer 251B to the top surface of the semiconductor substrate 200 may be 20-150 nm.
  • the material of the third insulating layer 252 may be SiON.
  • the material of the third insulating layer 252 is different from the material of the first insulating layer 220, so that in the etching process, under the same etching condition, the third insulating layer 252 and the first insulating layer 220 With different etching rates, selective etching can be performed.
  • the source and drain electrodes 270 are disposed on the outer sidewalls of the second insulating layer 240 and are electrically connected to the channel layer 230 .
  • the source and drain electrodes 270 are made of conductive materials, including but not limited to polysilicon.
  • the top surface of the first insulating layer 220 is lower than the top surface of the channel layer 230 to increase the contact area between the source and drain electrodes 270 and the channel layer 230 .
  • the top surface of the channel layer 230 is lower than the top surface of the second insulating layer 240 to prevent the word line structure 250 from contacting the channel layer 230 .
  • the word line structure 250 , the source and drain electrodes 270 and the channel layer 230 constitute a transistor, wherein the word line structure 250 serves as a gate of the transistor, and the second insulating layer 240 serves as a gate insulating layer.
  • the first insulating layer 220 isolates the channel layer 230 from the semiconductor substrate 200, thereby avoiding the generation of substrate leakage current and improving the reliability of the semiconductor structure.

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Abstract

本申请提供一种半导体结构及其制备方法，所述制备方法包括如下步骤：提供半导体衬底；于所述半导体衬底内形成沟槽；形成第一绝缘层，所述第一绝缘层至少覆盖所述沟槽内壁；形成沟道层，所述沟道层至少覆盖所述第一绝缘层内壁；形成第二绝缘层，所述第二绝缘层至少覆盖所述沟道层内壁；于所述沟槽内填充字线结构；去除部分半导体衬底、部分第一绝缘层及部分沟道层，于所述第二绝缘层外侧壁形成凹陷区域；于所述凹陷区域内形成源漏极，所述源漏极与所述沟道层电连接。

Description

一种半导体结构及其制备方法
相关申请的交叉引用
本申请基于申请号为202010855256.6、申请日为2020年08月24日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体制造领域，尤其涉及一种半导体结构及其制备方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由用于存储数据的存储单元阵列以及位于所述存储单元阵列外围的外围电路组成。每个存储单元通常包括晶体管和电容器。所述晶体管上的字线电压能够控制晶体管的开启和关闭，从而通过位线读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着制程工艺的不断发展，晶体管的尺寸也越小，而晶体管的沟道电场强度不断增强，随着DRAM的工艺节点来到20nm及以下，晶体管的衬底漏电流问题也越来越严重，会导致器件的可靠性问题。例如，器件Snapback击穿，CMOS电路的拴锁效应(Latch up effect)和器件寿命的降低等。
因此，如何避免衬底漏电流，成为目前亟需解决的问题。
发明内容
本申请所要解决的技术问题是，提供一种半导体结构及其制备方法，其能够避免衬底漏电流，提高半导体结构的可靠性。
为了解决上述问题，本申请提供了一种半导体结构的制备方法，其包括如下步骤：提供半导体衬底；于所述半导体衬底上形成沟槽；形成第一绝缘层，所述第一绝缘层至少覆盖所述沟槽内壁；形成沟道层，所述沟道层至少覆盖所述第一绝缘层内壁；形成第二绝缘层，所述第二绝缘层至少覆盖所述沟道层内壁；于所述沟槽内填充字线结构；去除部分半导体衬底、部分第一绝缘层及部分沟道层，于所述第二绝缘层外侧壁形成凹陷区域；于所述凹陷区域内形成源漏极，所述源漏极与所述沟道层电连接。
在本申请的一种可选实施例中，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离结构隔离，所述沟槽形成在所述有源区内。
在本申请的一种可选实施例中，所述字线结构包括导电结构及位于所述导电结构上的第三绝缘层，所述导电结构包括阻挡层及第一导电层。
在本申请的一种可选实施例中，形成沟道层的步骤进一步包括：至少于所述第一绝缘层内壁形成一半导体层；对所述半导体层进行掺杂，形成所述沟道层。
在本申请的一种可选实施例中，对所述半导体层进行掺杂的方法是，采用离子注入工艺对所述半导体层进行掺杂。
在本申请的一种可选实施例中，所述第一绝缘层还覆盖所述半导体衬底上方区域，所述沟道层还覆盖位于所述半导体衬底上方的第一绝缘层表面，所述第二绝缘层还覆盖位于所述半导体衬底上方的沟道层表面，于所述沟槽内填充字线结构的步骤进一步包括如下步骤：于所述第二绝缘层表面形成所述阻挡层，所述阻挡层还覆盖半导体衬底上方的第二绝缘层表面；于所述阻挡层表面形成第一导电层，且所述第一导电层填充所述沟槽；回 刻所述第一导电层及所述阻挡层，使所述第一导电层及所述阻挡层的顶面低于所述半导体衬底的顶面，并去除所述半导体衬底上方的膜层，以所述第一绝缘层作为刻蚀停止层；形成所述第三绝缘层，所述第三绝缘层填充所述沟槽，并且覆盖所述半导体衬底上方区域；去除所述半导体衬底上方的膜层，以所述半导体衬底为刻蚀停止层。
在本申请的一种可选实施例中，所述第一绝缘层与所述第三绝缘层的材料不同。
在本申请的一种可选实施例中，于所述凹陷区域内形成源漏极的步骤进一步包括：沉积第二导电层，所述第二导电层填充所述凹陷区域，并覆盖所述半导体衬底的表面；对所述第二导电层进行刻蚀，至所述第三绝缘层停止，以形成所述源漏极。
在本申请的一种可选实施例中，沉积第二导电层的步骤，进一步包括如下步骤：沉积半导体层，所述半导体层填充所述凹陷区域，并覆盖所述半导体衬底的表面；对所述半导体层进行等离子体注入或离子掺杂，以增强所述半导体层的导电性。
本申请还提供一种半导体结构，其包括：半导体衬底，所述半导体衬底具有沟槽；第一绝缘层，覆盖所述沟槽内壁；沟道层，覆盖所述第一绝缘层内壁；第二绝缘层，覆盖所述沟道层内壁；字线结构，填充在所述沟槽内；源漏极，设置在所述第二绝缘层的外侧壁，并与所述沟道层电连接。
在本申请的一种可选实施例中，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离结构隔离，所述沟槽形成在所述有源区。
在本申请的一种可选实施例中，所述沟槽的深度为50～300nm，所述沟槽的宽度为20～100nm。
在本申请的一种可选实施例中，所述第一绝缘层的厚度为1～30nm。
在本申请的一种可选实施例中，所述沟道层的厚度为3～30nm。
在本申请的一种可选实施例中，所述第一绝缘层的顶面低于所述沟道层的顶面，所述沟道层的顶面低于所述第二绝缘层的顶面。
在本申请的一种可选实施例中，所述源漏极的上表面与所述字线结构的上表面齐平。
在本申请的一种可选实施例中，所述源漏极的上表面与所述浅沟槽隔离结构的上表面齐平。
本申请的优点在于，利用第一绝缘层将沟道层与半导体衬底隔离，从而避免衬底漏电流的产生，提高了半导体结构的可靠性。
附图说明
图1是本申请半导体结构的制备方法的一实施例的步骤示意图；
图2～图14是本申请半导体结构的制备方法的一实施例的工艺流程图。
附图标记：
200-半导体衬底；201-有源区；202-浅沟槽隔离结构；210-沟槽；220-第一绝缘层；230-沟道层；240-第二绝缘层；250-字线结构；251-导电结构；251A-阻挡层；251B-第一导电层；252-第三绝缘层；260-凹陷区域；270-源漏极；
300-硬掩膜层；
400-半导体层。
具体实施方式
下面结合附图对本申请提供的半导体结构及其制备方法的具体实施方式做详细说明。
图1是本申请半导体结构的制备方法的一实施例的步骤示意图。请参阅图1，所述半导体结构的制备方法包括如下步骤：提供半导体衬底；于所述半导体衬底内形成沟槽；形成第一绝缘层，所述第一绝缘层至少覆盖所 述沟槽内壁；形成沟道层，所述沟道层至少覆盖所述第一绝缘层内壁；形成第二绝缘层，所述第二绝缘层至少覆盖所述沟道层内壁；于所述沟槽内填充字线结构；去除部分半导体衬底、部分第一绝缘层及部分沟道层，于所述第二绝缘层外侧壁形成凹陷区域；于所述凹陷区域内形成源漏极，所述源漏极与所述沟道层电连接。
图2～图14是本申请半导体结构的制备方法的一实施例的工艺流程图。
请参阅图2，提供半导体衬底200。所述半导体衬底200可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底200的构成材料选用单晶硅。
进一步，在该实施例中，所述半导体衬底200具有多个独立的有源区201，所述有源区201通过浅沟槽隔离结构202隔离。所述浅沟槽隔离结构的材料可为氧化物等绝缘材料。
请参阅图3，于所述半导体衬底200内形成沟槽210。
在该实施例中，在所述有源区201形成所述沟槽210。如图3所示，在一个所述有源区201形成两个沟槽210。
形成所述沟槽的方法可以为，在所述半导体衬底200上形成图形化的硬掩膜层300；采用光刻及刻蚀工艺将所述硬掩膜层300的图案转移到所述半导体衬底200上，形成所述沟槽210。其中，所述沟槽210的深度可为50～300nm，宽度可为20～100nm，以为后续工艺形成的结构提供足够的空间。在该步骤之后，所述硬掩膜层并未被去除，以在后续工艺中对所述半导体衬底200起到保护作用。
请参阅图4，形成第一绝缘层220，所述第一绝缘层220至少覆盖所述 沟槽210内壁。其中，可采用原子层沉积(ALD)工艺形成所述第一绝缘层220，该种工艺形成的第一绝缘层220结构致密，阻挡作用强。在本实施例中，所述第一绝缘层220为氮化物，例如氮化硅，在本申请其他实施例中，所述第一绝缘层220也可为其他绝缘材料，例如氧化物等。所述第一绝缘层220的厚度范围为1～30nm，使其既能够起到有效阻挡漏电流的作用，又能够避免占用过多的有源区201的空间，进而影响半导体器件性能。
进一步，所述第一绝缘层220不仅覆盖所述沟槽210的内壁，还覆盖所述半导体衬底200的表面。具体地说，在本实施例中，由于所述半导体衬底200表面具有硬掩膜层300，因此，所述第一绝缘层220不仅覆盖所述沟槽210的内壁，还覆盖所述半导体衬底200表面的硬掩膜层300。
请参阅图5，形成沟道层230，所述沟道层230至少覆盖所述第一绝缘层220内壁。进一步，所述沟道层230不仅覆盖所述第一绝缘层220的内壁，还覆盖所述半导体衬底200上方的第一绝缘层220上表面。
其中，形成所述沟道层230的方法是：
至少于所述第一绝缘层220内壁形成一半导体层，在一实施例中，所述半导体层不仅覆盖所述第一绝缘层220的内壁，还覆盖所述半导体衬底200上方的第一绝缘层220上表面。所述半导体层可采用低压力化学气相沉积法(LPCVD)形成，也可采用低压力化学气相沉积法与外延工艺共同形成。所述半导体层包括但不限于硅、锗等结构层。
对所述半导体层进行掺杂，形成所述沟道层230。其中，对所述半导体层进行掺杂的方法是，采用离子注入工艺对所述半导体层进行掺杂。具体地说，在本实施例中，采用离子注入工艺对半导体层进行硼(B)掺杂，以形成沟道层230。
进一步，在形成所述沟道层230后，对所述沟道层230进行快速热处理(rapid thermal process，RTP)，以修复沟道层230的晶格损伤，增加沟道 层230的载流子迁移率，保证半导体器件性能。
进一步，所述沟道层230的厚度为3～30nm，使得所述沟道层230既能够满足半导体器件的需求，又避免占用有源区空间，影响后续字线结构的形成。
请参阅图6，形成第二绝缘层240，所述第二绝缘层240至少覆盖所述沟道层230内壁。所述第二绝缘层240作为后续字线结构与沟道层之间的绝缘层。所述第二绝缘层240的厚度可为15～40埃，若其太薄，起不到字线结构与沟道层之间绝缘的作用，若太厚，则会增大半导体器件的阈值电压，影响半导体器件的性能。
所述第二绝缘层240的材料可为氧化物或者高K介质材料。例如，所述氧化物可为氧化硅、所述高K介质材料可为HfO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2O 3、La 2O 3、ZrO 2、LaAlO或Ta 2O 5。进一步，所述第二绝缘层240的材料与所述第一绝缘层220的材料不同，使得在后续工艺中，在同一刻蚀条件下，所述第二绝缘层240与所述第一绝缘层220具有不同的刻蚀速率，进而可进行选择性刻蚀。
进一步，在该实施例中，所述第二绝缘层240不仅覆盖所述沟道层230内壁，还覆盖所述半导体衬底200上方的沟道层230的上表面。
请参阅图7～图11，于所述沟槽210内填充字线结构250，所述字线结构250包括导电结构251及位于所述导电结构251上的第三绝缘层252。所述导电结构251包括阻挡层251A及第一导电层251B。所述第三绝缘层252的材料与所述第一绝缘层220的材料不同，以在后续刻蚀工艺中，在同一刻蚀条件下，所述第三绝缘层252与所述第一绝缘层220具有不同的刻蚀速率，进而可进行选择性刻蚀。
具体地说，在本实施例中，于所述沟槽210内填充字线结构250的方法包括如下步骤：
请参阅图7，于所述第二绝缘层240表面形成阻挡层251A，所述阻挡层251A还覆盖半导体衬底200上方的第二绝缘层240上表面。所述阻挡层251A可为TiN层或者Ti与TiN的复合层。所述阻挡层251A的厚度可为2～7nm。
请参阅图8，于所述阻挡层251A上形成第一导电层251B，所述第一导电层251B填充所述沟槽210并且覆盖所述半导体衬底200上方的阻挡层251A的上表面。所述第一导电层251B可为金属钨层。在本实施例中，采用化学气相沉积(CVD)的方法形成所述第一导电层251B，并进行化学机械研磨，以使所述第一导电层251B表面平整。在本申请其他实施例中，可采用其他沉积方法形成所述第一导电层251B，例如，物理气相沉积(PVD)。
请参阅图9，采用干法刻蚀回刻所述第一导电层251B及所述阻挡层251A，使所述第一导电层251B及所述阻挡层251A的顶面低于所述半导体衬底200的顶面。在该步骤结束后，所述沟槽210的部分区域填充有所述导电结构251，所述第二绝缘层240的部分侧壁被暴露。其中，所述第一导电层251B的上表面至所述半导体衬底200的顶面的距离可为20～150nm。
进一步，去除所述半导体衬底200上方的膜层，以所述第一绝缘层220作为刻蚀停止层。具体地说，位于所述半导体衬底200上方的第一导电层251B、阻挡层251A、第二绝缘层240及沟道层230被去除，所述第一绝缘层220被保留。
进一步，在采用干法刻蚀后，再采用湿法刻蚀工艺，去除所述第二绝缘层240侧壁残留的阻挡层251A。
请参阅图10，形成第三绝缘层252，所述第三绝缘层252填充所述沟槽210，并且覆盖所述半导体衬底200上方区域。具体地说，在本实施例中，所述第三绝缘层252填充所述沟槽210，并覆盖位于所述半导体衬底200上方的第一绝缘层220的表面。所述第三绝缘层252的材料可为SiON。
请参阅图11，去除所述半导体衬底200上方的膜层，以所述半导体衬底200为刻蚀停止层。在本实施例中，采用干法刻蚀去除所述半导体衬底200上方的第三绝缘层252、第一绝缘层220及硬掩膜层300，暴露出所述半导体衬底200。在该步骤结束后，所述第一绝缘层220、沟道层230、第二绝缘层240及第三绝缘层252的顶面与所述半导体衬底200的顶面平齐。
请参阅图12，去除部分半导体衬底200、部分第一绝缘层220及部分沟道层230，于所述第二绝缘层240外侧壁形成凹陷区域260。在该步骤中，采用干法刻蚀工艺进行刻蚀。其中，可选择对所述第三绝缘层252及第二绝缘层240刻蚀速率小的刻蚀物质进行刻蚀，以避免所述第三绝缘层252及第二绝缘层240被去除。在本实施例中，刻蚀物质对所述第一绝缘层220的刻蚀速率大于对半导体衬底200及沟道层230的刻蚀速率，对半导体衬底200及沟道层230的刻蚀速率大于对第二绝缘层240及第三绝缘层252的刻蚀速率，进而能够在所述第二绝缘层240的外侧壁形成凹陷区域260。
例如，在一实施例中，形成凹陷区域后，所述第一绝缘层220的刻蚀深度为10～80nm，所述半导体衬底200及沟道层230的刻蚀深度为5～60nm，所述第三绝缘层252的剩余厚度为50～80nm。
请参阅图13及图14，于所述凹陷区域260内形成源漏极270，所述源漏极270与所述沟道层230电连接。所述源漏极270由导电材料构成，其填充所述凹陷区域260。所述源漏极270的材料包括但不限于多晶硅。
进一步，于所述凹陷区域260内形成源漏极270的方法包括如下步骤：
请参阅图13，沉积半导体层400，所述半导体层400填充所述凹陷区域260，并覆盖所述半导体衬底200的表面。其中，可采用化学气相沉积(CVD)工艺沉积所述半导体层400，所述半导体层400的材料包括但不限于多晶硅、锗等。在本实施例中，所述半导体层400的材料为多晶硅。
进一步，在沉积半导体层400的步骤之后，对所述半导体层400进行 等离子体注入或者离子掺杂，以增强所述半导体层400的导电性，形成第二导电层。其中，等离子体注入可选用P离子、As离子中的一种或多种。
进一步，可对所述第二导电层进行退火处理，以修复晶格损伤，提高器件性能。
进一步，在掺杂后，对所述第二导电层进行平坦化处理，以使其表面平整。所述平坦化处理可为化学机械研磨(CMP)。
请参阅图14，对所述第二导电层进行刻蚀，至所述第三绝缘层252停止，以形成所述源漏极270。在该步骤中，仅保留位于所述凹陷区域260内的第二导电层，作为所述源漏极270。
采用本申请制备方法形成的半导体结构将保留的第二导电层作为晶体管的源漏极270，字线结构250作为晶体管的栅极，第二绝缘层240作为栅极绝缘层。所述第一绝缘层220将所述沟道层230与半导体衬底200隔离，从而避免衬底漏电流的产生，提高了半导体结构的可靠性。
本申请还提供一种采用上述方法制备的半导体结构。请参阅图14，在本申请半导体结构的一实施例中，所述半导体结构包括半导体衬底200、第一绝缘层220、沟道层230、第二绝缘层240、字线结构250及源漏极270。
所述半导体衬底200具有沟槽210。在该实施例中，所述半导体衬底200具有多个独立的有源区201，所述有源区201通过浅沟槽隔离结构202隔离，所述沟槽210形成在所述有源区201内。所述沟槽210的深度为50～300nm，宽度为20～100nm，以为在所述沟槽210内形成的半导体结构提供足够的空间。其中，所述半导体衬底200包括多个所述沟槽210。例如，如图14所示，在一个所述有源区201形成两个沟槽210。
所述第一绝缘层220覆盖所述沟槽210内壁。在本实施例中，所述第一绝缘层220为氮化物，例如氮化硅，在本申请其他实施例中，所述第一绝缘层220也可为其他绝缘材料，例如氧化物等。所述第一绝缘层220的 厚度为1～30nm，使得其既能够起到有效阻挡漏电流的作用，又能够避免占用过多的有源区201的空间，进而影响半导体器件性能。
所述沟道层230覆盖所述第一绝缘层220内壁。所述沟道层230可由掺杂硼的硅材料构成。所述沟道层230的厚度为3～30nm，使得所述沟道层230既能够满足半导体器件的需求，又避免占用有源区空间，影响后续字线结构的形成。
所述第二绝缘层240覆盖所述沟道层230内壁。所述第二绝缘层240作为字线结构250与沟道层230之间的绝缘层。所述第二绝缘层240的厚度可为15～40埃，若其太薄，起不到字线结构与沟道层之间绝缘的作用，若太厚，则会增大半导体器件的阈值电压，影响半导体器件的性能。
所述第二绝缘层240的材料可为氧化物或者高K介质材料。例如，所述氧化物可为氧化硅、所述高K介质材料可为HfO 2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2O 3、La 2O 3、ZrO 2、LaAlO或Ta 2O 5。进一步，所述第二绝缘层240的材料与所述第一绝缘层220的材料不同，使得在后续工艺中，在同一刻蚀条件下，所述第二绝缘层240与所述第一绝缘层220具有不同的刻蚀速率，进而可进行选择性刻蚀。
所述字线结构250填充在所述沟槽210内。所述字线结构250包括导电结构251及位于所述导电结构251上的第三绝缘层252。所述导电结构251包括阻挡层251A及第一导电层251B。所述阻挡层251A可为TiN层或者Ti与TiN的复合层。所述阻挡层251A的厚度可为2～7nm。所述第一导电层251B可为金属钨层。所述第一导电层251B及所述阻挡层251A的顶面低于所述半导体衬底200的顶面。其中，所述第一导电层251B至所述半导体衬底200的顶面的距离可为20～150nm。
所述第三绝缘层252的材料可为SiON。所述第三绝缘层252的材料与所述第一绝缘层220的材料不同，以在刻蚀工艺中，在同一刻蚀条件下， 所述第三绝缘层252与所述第一绝缘层220具有不同的刻蚀速率，进而可进行选择性刻蚀。
源漏极270设置在所述第二绝缘层240的外侧壁，并与所述沟道层230电连接。所述源漏极270由导电材料构成，包括但不限于多晶硅。
进一步，所述第一绝缘层220的顶面低于所述沟道层230的顶面，以增大所述源漏极270与沟道层230的接触面积。所述沟道层230的顶面低于所述第二绝缘层240的顶面，以避免所述字线结构250与所述沟道层230接触。
所述字线结构250、所述源漏极270及所述沟道层230构成晶体管，其中，所述字线结构250作为晶体管的栅极，所述第二绝缘层240作为栅极绝缘层。所述第一绝缘层220将所述沟道层230与半导体衬底200隔离，从而避免衬底漏电流的产生，提高了半导体结构的可靠性。
以上所述仅是本申请的可选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (17)

  1. 一种半导体结构的制备方法，包括如下步骤：
    提供半导体衬底；
    于所述半导体衬底内形成沟槽；
    形成第一绝缘层，所述第一绝缘层至少覆盖所述沟槽内壁；
    形成沟道层，所述沟道层至少覆盖所述第一绝缘层内壁；
    形成第二绝缘层，所述第二绝缘层至少覆盖所述沟道层内壁；
    于所述沟槽内填充字线结构；
    去除部分半导体衬底、部分第一绝缘层及部分沟道层，于所述第二绝缘层外侧壁形成凹陷区域；
    于所述凹陷区域内形成源漏极，所述源漏极与所述沟道层电连接。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离结构隔离，所述沟槽形成在所述有源区内。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，所述字线结构包括导电结构及位于所述导电结构上的第三绝缘层，所述导电结构包括阻挡层及第一导电层。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，形成沟道层的步骤进一步包括：
    至少于所述第一绝缘层内壁形成一半导体层；
    对所述半导体层进行掺杂，形成所述沟道层。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，对所述半导体层进行掺杂的方法是，采用离子注入工艺对所述半导体层进行掺杂。
  6. 根据权利要求3所述的半导体结构的制备方法，其中，所述第一 绝缘层还覆盖所述半导体衬底上方区域，所述沟道层还覆盖位于半导体衬底上方的第一绝缘层表面，所述第二绝缘层还覆盖位于所述半导体衬底上方的沟道层表面；
    于所述沟槽内填充字线结构的步骤进一步包括如下步骤：
    于所述第二绝缘层表面形成所述阻挡层，所述阻挡层还覆盖半导体衬底上方的第二绝缘层表面；
    于所述阻挡层表面形成所述第一导电层，且所述第一导电层填充所述沟槽；
    回刻所述第一导电层及所述阻挡层，使所述第一导电层及所述阻挡层的顶面低于所述半导体衬底的顶面，去除所述半导体衬底上方的膜层，以所述第一绝缘层作为刻蚀停止层；
    形成所述第三绝缘层，所述第三绝缘层填充所述沟槽，并且覆盖所述半导体衬底上方区域；
    去除所述半导体衬底上方的膜层，以所述半导体衬底为刻蚀停止层。
  7. 根据权利要求3所述的半导体结构的制备方法，其中，所述第一绝缘层与所述第三绝缘层的材料不同。
  8. 根据权利要求3所述的半导体结构的制备方法，其中，于所述凹陷区域内形成源漏极的步骤进一步包括：
    沉积第二导电层，所述第二导电层填充所述凹陷区域，并覆盖所述半导体衬底的表面；
    对所述第二导电层进行刻蚀，至所述第三绝缘层停止，以形成所述源漏极。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，沉积第二导电层的步骤，进一步包括如下步骤：
    沉积半导体层，所述半导体层填充所述凹陷区域，并覆盖所述半导 体衬底的表面；
    对所述半导体层进行等离子体注入或离子掺杂，以增强所述半导体层的导电性。
  10. 一种半导体结构，包括：
    半导体衬底，所述半导体衬底具有沟槽；
    第一绝缘层，覆盖所述沟槽内壁；
    沟道层，覆盖所述第一绝缘层内壁；
    第二绝缘层，覆盖所述沟道层内壁；
    字线结构，填充在所述沟槽内；
    源漏极，设置在所述第二绝缘层的外侧壁，并与所述沟道层电连接。
  11. 根据权利要求10所述的半导体结构，其中，所述半导体衬底具有多个独立的有源区，所述有源区通过浅沟槽隔离结构隔离，所述沟槽形成在所述有源区。
  12. 根据权利要求10所述的半导体结构，其中，所述沟槽的深度为50～300nm，所述沟槽的宽度为20～100nm。
  13. 根据权利要求10所述的半导体结构，其中，所述第一绝缘层的厚度为1～30nm。
  14. 根据权利要求10所述的半导体结构，其中，所述沟道层的厚度为3～30nm。
  15. 根据权利要求10所述的半导体结构，其中，所述第一绝缘层的顶面低于所述沟道层的顶面，所述沟道层的顶面低于所述第二绝缘层的顶面。
  16. 根据权利要求10所述的半导体结构，其中，所述源漏极的上表面与所述字线结构的上表面齐平。
  17. 根据权利要求11所述的半导体结构，其中，所述源漏极的上表 面与所述浅沟槽隔离结构的上表面齐平。
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