TWI464885B - 在金氧半場效電晶體元件中整合肖特基之結構及其方法 - Google Patents

在金氧半場效電晶體元件中整合肖特基之結構及其方法 Download PDF

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TWI464885B
TWI464885B TW101108798A TW101108798A TWI464885B TW I464885 B TWI464885 B TW I464885B TW 101108798 A TW101108798 A TW 101108798A TW 101108798 A TW101108798 A TW 101108798A TW I464885 B TWI464885 B TW I464885B
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doped
region
substrate
schottky
contact trench
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TW201242034A (en
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Sik Lui
Yi Su
Daniel Ng
Anup Bhalla
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Alpha & Omega Semiconductor
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Description

在金氧半場效電晶體元件中整合肖特基之結構及其方法
本發明是有關於一種金氧半場效電晶體元件，特別是有關於一種將肖特基二極體整合於金氧半場效電晶體元件中的新方法和整合結構。
肖特基二極體在很多應用領域已經取代了PN結二極體。尤其是肖特基二極體已經用於取代功率金氧半場效電晶體(MOSFET)元件中的PN結(也就是，MOSFET中的體二極體同源極(source)和汲極(drain)並聯)。功率MOSFET中配置PN結二極體會表現出幾個不可取的特性，其中包括：過大的正向傳導損耗，在正向偏壓下工作時，本體區與外延層之間的電荷存儲，過量的儲存少子電荷會導致當功率MOSFET從正向偏壓切換到反向偏壓時，造成過大的恢復電流和尖峰電壓，在快速切換時產生射頻干擾。所有這些特性，造成對元件不必要的壓力，導致元件的性能欠佳。
肖特基二極體具有許多優於PN結二極體的特點，特別是配置在功率MOSFET中時。肖特基二極體在正嚮導通時的正向電壓降很低，降低了元件的功耗，從而減少了傳導損耗。肖特基的傳導是藉由多數載流子進行的，在元件正反向切換時，少數載流子的電荷存儲效應不會發生。因此，肖特基二極體是功率MOSFET的首選組態 。
由於功率MOSFET採用肖特基二極體越來越廣泛，所以改進元件組態以降低生產成本變得越來越重要。特別重要是，考慮如何減小整合了肖特基二極體在半導體基板上所占的表面積。減少肖特基二極體所占的表面積，是降低製造成本和進一步使電子設備的尺寸和形狀小型化的關鍵，從而實現便攜性和其他功能。
將肖特基二極體整合於MOSFET，製造功率MOSFET元件，習知多種供選組態。然而，所有這些組態，都有一些不良特性，使它們性能比最佳功率MOSFET元件差。第1圖至第3圖表示了三種這樣的習知技術型態。
第1圖表示了習知技術整合的多層MOSFET元件，以及與這些MOSFET元件並聯的結勢壘控制肖特基(JBS)的整合結構。整合結構100包括了一個n+型基板101和一個n型外延層103，複數個MOSFET內建於整合結構100中。溝槽105加工成外延層103並填充導電材料，由絕緣層108環繞，形成整合結構100中每個MOSFET的各個閘極區107。用p-型材料摻雜外延層103環繞著每個溝槽的區域，以形成每個MOSFET的本體區109。每個MOSFET本體區109在鄰近溝槽105側壁的那部分，摻雜n+型導電摻雜劑，以形成每個MOSFET元件的源極區111。n+型基板101提供了每個MOSFET的汲極區。
結勢壘控制肖特基二極體(JBS)119也內建於整合結構100。肖特基二極體119包括肖特基勢壘金屬115直接形成於n-摻雜區113頂部。n摻雜區113是在外延層103中兩個MOSFET本體區109之間形 成的，肖特基結是在肖特基勢壘金屬115和n摻雜區113之間的介面處形成的。因此，勢壘金屬115形成了肖特基二極體的陽極，基板101形成了肖特基二極體的陰極。此外，在n-型摻雜區113中可能形成一個或多個p+摻雜遮罩區117，構成P-N結，這些P-N結夾斷了肖特基接頭下面的溝道區，以抑制從正向偏壓切換到反向偏壓時，造成過大的反向漏電電流。
雖然這個特定的組態確實製成了帶肖特基二極體的功率MOSFET元件，但它的缺點在於p+遮罩減少了肖特基的表面面積。為了使肖特基二極體具有更高的擊穿電壓，通常需要更深的p+結。因此，具有高擊穿電壓JBS的肖特基表面利用率可能相當低。在MOSFET中需要一個專用的區域，製備肖特基二極體，因此制得的晶片較大。
第2圖表示了一個供選用的習知技術的整合結構，包括一個單片整合肖特基二極體和一個高性能的溝槽閘極MOSFET。整合結構201包括複數個溝槽200-1、200-2、200-3、200-4，布圖蝕刻成一個n型基板202。然後，沿著溝槽200壁形成一薄層介質層204，之後，沉積導電材料206直到基本填滿每個溝槽200，形成整合結構201中的每一個MOSFET閘極區，在除了要形成肖特基二極體的溝槽(如溝槽200-3、200-4)之外的溝槽200間形成p-型阱區208。p-型阱區208構成了整合結構201中每個MOSFET的本體區。然後，在p-型阱區208裏形成n+型源極區212。基板202形成了整合結構201中每個MOSFET的汲極區。
藉由在基板202頂部沒有p-型阱的區域沉積肖特基勢壘金屬218，肖特基二極體210也可以內建於整合結構201之內。肖特基勢壘金 屬218形成肖特基二極體210的陽極，基板形成肖特基二極體210的陰極引出線，肖特基二極體210的周圍環繞著MOSFET溝槽200。
這種型態解決了肖特基表面利用的問題，因為不再需要在肖特基勢壘金屬218和基板202之間形成p-型摻雜區，以抑制在反向偏壓時過大的反向漏出電流。相反，當肖特基二極體的負極有電壓時，環繞著二極體的MOSFET溝槽200-3、200-4形成了耗盡區，該耗盡區有助於減小反向偏壓造成的二極體漏出電流。此外，可以調整溝槽200-3、200-4之間的距離W，這樣每個溝槽附近耗盡區都能在中部相互重疊，夾斷了肖特基勢壘金屬218和基板202之間的漂移區。
雖然第2圖所示整合結構型態更好地利用了肖特基表面，但這樣做必須為肖特基二極體的製備專門在MOSFET內分配特定的無摻雜區，這涉及到在製程中設計額外的程序。此外，這種整合結構仍然需要較大的晶片，這實質上是同JBS二極體一樣的缺點。
第3圖表示了另一整合結構，由一個MOSFET和在每一個MOSFET原胞中的肖特基二極體組成。整合結構300包括一個n+型基板301和一個n型外延層303，複數個MOSFET整合於整合結構300中。溝槽305連接到外延層303，並填充導電材料，周圍由絕緣層308環繞，形成整合結構300中每個MOSFET閘極區307。環繞溝槽的區域摻雜p型材料形成了每個MOSFET本體區309。每個本體區309藉由在溝槽305的鄰壁上摻雜n+型導電材料311，形成MOSFET元件的源極區311。最後，n+基板101為每個MOSFET提供了汲極區。
整合結構300的每個原胞內都內建了一個肖特基二極體319。每個 MOSFET本體區309中已初步形成了一個接觸溝槽316，這樣，接觸溝槽316的末端從了本體區309上方，延伸到外延層303中。用肖特基勢壘金屬315填充每個接觸溝槽316，這樣，在接觸溝槽316末端和外延層303之間的介面處就形成了肖特基結。接觸溝槽316的襯裏肖特基勢壘金屬315作為肖特基二極體319的陽極，基板301作為肖特基二極體319的陰極。此外，沿接觸溝槽316側壁的本體區309內，可能形成一個或多個p+摻雜區317，以改善了同本體區的接觸。
這種型態藉由在MOSFET主動元件中整合肖特基二極體(即在MOSFET元件的本體區內)，消除了在MOSFET之間分配專用區域形成一個肖特基二極體的必要性，似乎糾正了表面的利用率問題。
儘管第3圖表示的整合結構組態有效地利用了肖特基表面，並消除了為構建肖特基二極體預留額外元件面積的需要，但它仍然有不良特性。由於肖特基勢壘金屬必須與n-型材料直接接觸，以適當地形成肖特基二極體，p型本體區內創建的接觸溝槽必須比本體區更深。為了每個阱獲得所需的深度，製程中必須額外設計程序(例如，對本體區的反向摻雜)。這個特定組態的複雜的設計手段，導致了更加複雜和昂貴的製造製程。不幸的是，對本體區的補償摻雜在生產中不好控制，接觸溝槽深度的變化也會影響肖特基特性。
正是在這一背景下，提出了本發明的技術手段。
因此，本發明的目的是提供一種在金氧半場效電晶體元件中整合 肖特基的方法和結構，具有比原有結構簡單、低製造成本和避免形成大的逆洩露電流的明顯優勢。
本發明的一個方面在於，提出了一種結合至少一場效應電晶體和肖特基二極體在輕摻雜半導體基板組合上的整合結構，其包括：a)複數個形成在基板組合中的溝槽，沿基板組合的整體縱方向延伸，在複數個溝槽之間構成複數個臺面結構，各溝槽都用導電材料填充，並且藉由一薄層的電介質材料與溝槽壁分開，形成至少一場效應電晶體的閘極區；b)二導電類型與基板組合相反的具有第一導電類型的摻雜本體區形成在各臺面結構中，二摻雜本體區之間被基板組合的一裸露部分分開，在各摻雜本體區構成一接觸溝槽，沿基板組合的縱深方向部分延伸；c)一對具有第二導電類型的摻雜源極區形成在各摻雜本體區內，這對摻雜源極區位於各接觸溝槽附近的對邊上；以及d)一含有肖特基勢壘金屬的肖特基二極體，肖特基勢壘金屬形成在各摻雜本體區的各接觸溝槽中，在肖特基勢壘金屬和將二摻雜本體區分開的基板組合裸露部分的裸露在接觸溝槽中的垂直側壁之間的交界處形成一肖特基結。
本發明的另一個方面在於，提出了一種用於製備結合至少一場效應電晶體和肖特基二極體在輕摻雜半導體基板組合上的整合結構的方法，其包括：a)在基板組合中製備複數個溝槽，並且沿基板組合的整體縱深方向延伸，在複數個溝槽之間構成複數個臺面結構；b)用導電材料填充各溝槽，與溝槽壁藉由一薄層電介質材料分開，構成至少一場效應電晶體的閘極區；c)在各臺面結構中製備二導電類型與各臺面結構內的基板相反的具有第一導電 類型的摻雜本體區，基板組合的裸露部分將二摻雜本體區分開，在各摻雜本體區形成一接觸溝槽，沿基板組合的一部分縱深方向延伸；d)在各摻雜本體區內，製備一對具有第二導電類型的摻雜源極區，這對摻雜源極區位於各接觸溝槽附近的對邊上；並且e)在二摻雜本體區的各接觸溝槽內，製備含有肖特基勢壘金屬的肖特基二極體，在肖特基勢壘金屬和將二摻雜本體區分開的基板組合的裸露部分的裸露在接觸溝槽中的垂直側壁之間的交界處，肖特基勢壘金屬形成一肖特基結。
閱讀以下詳細說明並參照圖式之後，本發明的這些和其他的特點和優勢，對於本領域的技術人員而言，無疑將顯而易見。
100、201、300、400、500、600、700‧‧‧整合結構
101、202、301、401、701‧‧‧基板
103、303、403、703‧‧‧外延層
105、200-1、200-2、200-3、200-4、200-5、305、407‧‧‧溝槽
107、307、411‧‧‧閘極區
108、308‧‧‧絕緣層
109、309、405、405’、705‧‧‧本體區
111、212、413、713‧‧‧源極區
113、317‧‧‧摻雜區
115、417、717‧‧‧勢壘金屬
117、419、521、619、719、719’‧‧‧遮罩區
119、210、319‧‧‧肖特基二極體
204‧‧‧介質層
206‧‧‧導電材料
208‧‧‧p-型阱區
218、315‧‧‧肖特基勢壘金屬
316、415‧‧‧接觸溝槽
408‧‧‧臺面結構
409‧‧‧電介質材料
418‧‧‧肖特基結
420、720‧‧‧絕緣物
422、722‧‧‧源極金屬
711‧‧‧閘極
718‧‧‧肖特基二極體區
721‧‧‧本體接觸區
W‧‧‧溝槽200-3、200-4之間的距離
第1圖 係為習知技術之整合結構之剖面示意圖。
第2圖 係為供選用之習知技術之整合結構之剖面示意圖。
第3圖 係為供選用之習知技術之整合結構之剖面示意圖。
第4A圖 係為本發明之實施例之整合結構之立體示意圖。
第4B圖 係為本發明之整合結構之沿第4A圖之線B-B’之剖面示意圖。
第4C圖 係為本發明之整合結構之沿第4A圖之線C-C’之剖面示意圖。
第5A圖 係為本發明之實施例之供選用之整合結構之立體示意圖。
第5B圖 係為本發明之整合結構之沿第5A圖之線B-B’之剖面示意圖。
第5C圖 係為本發明之整合結構之沿第5A圖之線C-C’之剖面示意 圖。
第6A圖 係為本發明之實施例之供選用之整合結構之立體示意圖。
第6B圖 係為本發明之整合結構之沿第6A圖之線B-B’之剖面示意圖。
第6C圖 係為本發明之整合結構之沿第6A圖之線C-C’之剖面示意圖。
第7圖 係為本發明之另一實施例之供選用之整合結構之剖面示意圖。
第8A至8C圖 係為本發明之實施例之按第4A圖至第4C圖所示類型之整合結構之製造過程示意圖。
以下結合圖式，藉由詳細說明較佳的具體實施例，對本發明做進一步闡述。
依據本發明的實施例，該整合結構可以利用習知技術中第3圖所示整合結構的多項優勢，同時也避免了該特殊結構繁瑣的製備技術。第4A圖至第4C圖表示依據本發明的一個實施例，含有金氧半場效電晶體(MOSFET)元件和肖特基二極體的整合結構400的不同視圖。第4A圖表示整合結構400前部的立體視圖。第4B圖表示整合結構400沿線B-B’的剖面圖。第4C圖表示整合結構400沿線C-C’的剖面圖。
整合結構400含有至少一MOSFET元件，以及至少一肖特基二極體，它們可以並聯起來，構成功率MOSFET。整合結構400內建於基板401上。作為示例，但不作為侷限，基板可以由以下材料製成 ：矽、二氧化矽、氧化鋁、藍寶石、鍺、砷化鎵(GaAs)、矽或鍺的合金、磷化銦(InP)或可以沉積在電子元件(例如電晶體、二極體等)上的任何其他材料。作為示例，但不作為侷限，可以重摻雜基板401，構成n+型基板。可選外延層403生長在基板上，以便於在整合結構400上製備電子元件。作為示例，但不作為侷限，外延層403可以是n型外延層。外延層403可以輕摻雜以便承載較高的元件擊穿電壓，但這樣做會增大元件的內部阻抗。各種基板401和外延層403的組合在下文中將統稱為組合基板。
然後，在外延層403以及基板401中形成複數個溝槽407。如第4B圖所示，每個溝槽407都沿基板401和外延層403的整個縱深方向延伸。用導電材料填充溝槽407，溝槽407藉由一個薄層的電介質材料409，與溝槽壁分離。填充每個溝槽的導電材料，作為每個MOSFET元件的閘極區411。作為示例，但不作為侷限，導電材料可以是多晶矽，電介質材料可以是二氧化矽。
每對溝槽407定義它們之間的一個臺面結構408。在每個臺面結構408中，製備兩個摻雜的本體區405、405’，它們的導電類型與基板401或外延層403不同。作為示例，但不作為侷限，摻雜的本體區405、405’可以為p-型本體區。如第4A圖所示，外延層403的未摻雜p-型部分將兩個摻雜的本體區405、405’分開。儘管圖中沒有表示出，但仍要注意的是，外延層403是任選的，因此在本發明的其他實施例中，基板401的未摻雜p-型部分可以取代外延層，將兩個摻雜的本體區405、405’分開。
在每個摻雜的本體區405、405’中，製備一對摻雜的源極區413，其導電類型與摻雜的本體區不同。作為示例，但不作為侷限， 如果本體區405、405’為摻雜的p型，那麼摻雜的源極區413可以為n+型源極區。基板401構成每個MOSFET元件的汲極區。因此，每個MOSFET元件都含有一個帶溝槽的閘極區411、一個本體區405位於帶溝槽的閘極區411的兩側，兩個源極區413嵌於本體區405中鄰近帶溝槽的閘極區411的對邊，基板401作為汲極。
接觸溝槽415形成在本體區405中。接觸溝槽415沿基板401和外延層403的縱深方向部分延伸，在本體區405、405’和將兩個本體區405、405’分開的外延層403之間的介面處截止。每個接觸溝槽415都使將兩個摻雜的本體區405、405’分開的外延層403的垂直側壁裸露出來。肖特基二極體沿該垂直側壁形成。儘管沒有表示出來，但仍要注意的是，在沒有外延層的整合結構中，裸露的垂直側壁是指基板的側壁。
肖特基二極體包括肖特基勢壘金屬417，肖特基勢壘金屬417在每個接觸溝槽內，沿接觸溝槽415末端的每個裸露的垂直側壁形成。為了解釋說明，在第4A圖中的接觸溝槽415中並沒有表示出肖特基勢壘金屬，而第4B圖和第4C圖表示的肖特基勢壘金屬417與MOSFET元件整合，填滿了側壁。肖特基勢壘金屬417構成肖特基二極體的陽極，外延層403裸露的垂直側壁構成肖特基二極體的陰極。肖特基結418位於肖特基勢壘金屬417和外延層403裸露的垂直側壁之間的交界處。絕緣物420(例如含有硼酸的矽玻璃(BPSG))可以覆蓋閘極區411和外延層403的上表面，同時使源極區413的上表面部分裸露出來(未示出)。源極金屬422可以連接到源極區413以及勢壘金屬417上。
另一種導電類型的垂直遮罩區419可以形成在每個摻雜的本體區 405中。作為示例，但不作為侷限，摻雜的遮罩區419可以為p+型摻雜區。摻雜的遮罩區419可以沿壁的底面，在基板401和外延層403的縱深方向延伸至少超過肖特基結418，同時包圍著接觸溝槽415的底部拐角。摻雜的遮罩區419也可以延伸到將兩個摻雜的本體區405分開的外延層403裸露的垂直側壁的底部，如第4C圖所示。這個摻雜的遮罩區419在肖特基結418處，構成P-N結，用於夾斷肖特基接頭下方的通道區，防止從正向偏壓向反向偏壓切換時產生的巨大的反向漏電流。
第4A圖至第4C圖所示的結構具有許多優於習知技術的優勢。雖然肖特基二極體獨立於溝槽MOSFET，但是並不需要為製備肖特基二極體專門在MOSFET之間分配專用區域。而是肖特基二極體內建於為MOSFET元件指定的區域中。此外，沿外延層403的裸露部分裸露的垂直側壁，形成肖特基結418，從而使肖特基有效地利用了表面區域。而且，由於所形成的肖特基結沿著外延層403裸露部分的垂直側壁，因此填裝有肖特基勢壘金屬的接觸溝槽415無需延伸超過本體區405、405’的深度。從而降低了整合結構400的複雜性，以及製備整合結構400所需的總的製程步驟。最後，肖特基二極體受到了來自於摻雜的遮罩區419以及帶溝槽的閘極區411的雙重保護，不會在開關時產生大的漏電流。
整合結構400的多種可選結構變化都在本發明的實施例範圍內。
第5A圖至第5C圖表示依據本發明的實施例，整合結構500的多個示意圖，整合結構500含有MOSFET元件和肖特基二極體。第5A圖表示整合結構500的正面立體視圖。第5B圖表示整合結構500的一部分沿線B-B’的剖面圖。第5C圖表示整合結構500的一部分沿線 C-C’的剖面圖。為了解釋說明，接觸溝槽415在第5A圖中表示為空的，而第5B圖和第5C圖表示肖特基勢壘金屬417與MOSFET元件整合，並且填滿了接觸溝槽415。
第5A圖至第5C圖中的整合結構500的結構除了稍有修正之外，其他都與第4A圖至第4C圖所示的整合結構400類似。在第5A圖第5C圖所示的整合結構500中，一個額外的摻雜遮罩區521形成在外延層403的裸露部分的頂面上，以便為肖特基二極體提供額外的反向漏電流遮罩。作為示例，但不作為侷限，額外的摻雜遮罩區521可以是一個p-型額外的摻雜遮罩區521。
第5A圖至第5C圖所示的整合結構500與第4A圖至第4C圖相比，同樣保持了優於習知技術的優勢。雖然肖特基二極體獨立於溝槽MOSFET，但是並不需要為製備肖特基二極體專門在MOSFET之間分配專用區域。而是肖特基二極體內建於為MOSFET元件指定的區域中。此外，沿外延層403的裸露部分裸露的垂直側壁，形成肖特基結418，從而使肖特基有效地利用了表面區域。而且，由於所形成的肖特基結沿著外延層403裸露部分的垂直側壁，因此填裝有肖特基勢壘金屬的接觸溝槽415無需延伸超過本體區405、405’的深度。從而降低了整合結構500的複雜性，以及製備整合結構500所需的總的製程步驟。最後，肖特基二極體受到了來自於摻雜的遮罩區419、額外的摻雜遮罩區521以及帶溝槽的閘極區411的三重保護，而非雙重保護，在開關時不會產生大的漏電流。
第6A圖至第6C圖表示依據本發明的實例，含有MOSFET元件和肖特基二極體整合結構600的示意圖。第6A圖表示整合結構600的正面 立體視圖。第6B圖表示整合結構600的一部分沿線B-B’的剖面圖。第6C圖表示整合結構600的一部分沿線C-C’的剖面圖。為了方便解釋說明，接觸溝槽415在第6A圖中表示為空的，而第6B圖和第6C圖表示肖特基勢壘金屬417與MOSFET元件整合，並且填滿了接觸溝槽415。
第6A圖至第6C圖中的整合結構600的結構除了稍有修正之外，其他都與第4A圖至第4C圖所示的整合結構400類似。在第6A圖至第6C圖所示的整合結構600中，摻雜遮罩區619沿接觸溝槽415的側壁形成，沿摻雜本體區405的縱深方向延伸。摻雜遮罩區619延伸到外延層403的一部分垂直側壁中，沿外延層403的垂直側壁的長度延伸，如第6B圖和第6C圖所示。作為示例，但不作為侷限，摻雜遮罩區619可以是一個p+型摻雜遮罩區。
第6A圖至第6C圖所示的整合結構600與第4A圖至第4C圖相比，同樣保持了優於習知技術的優勢。雖然肖特基二極體獨立於溝槽MOSFET，但是並不需要為製備肖特基二極體專門在MOSFET之間分配專用區域。而是肖特基二極體內建於為MOSFET元件指定的區域中。此外，沿外延層403的裸露部分裸露的垂直側壁，形成肖特基結418，從而使肖特基有效地利用了表面區域。而且，由於所形成的肖特基結沿著外延層403裸露部分的垂直側壁，因此填裝有肖特基勢壘金屬的接觸溝槽415無需延伸超過本體區405、405’的深度上方。從而降低了整合結構600的複雜性，以及製備整合結構600所需的總的製程步驟。最後，肖特基二極體受到了來自於摻雜的遮罩區619以及帶溝槽的閘極區411的雙重保護，在開關時不會產生大的漏電流。
依據另一個可選實例，結型勢壘肖特基和MOSFET元件可以整合在不同的相鄰臺面結構中。第7圖表示一種具有該結構的元件700的示例。元件700在下方的基板701上含有一個外延層703。用相同導電類型的摻雜物摻雜基板和外延層。本體區705形成在外延層703的上部，用導電類型與外延層相反的摻雜物摻雜本體區705。形成在臺面結構中的深溝槽容納了閘極711和閘極絕緣物。閘極711可以藉由絕緣物720實現電絕緣。用導電類型與本體區705相反的摻雜物摻雜源極區713，源極區713可以形成在閘極溝槽一側附近的外延層最上面的部分。接觸溝槽可以形成在每個閘極711的任意一側。接觸溝槽形成在源極區713附近的閘極711的一邊上，從而使源極區位於接觸溝槽和閘極之間。本體接觸區721可以形成在接觸溝槽底部附近的外延層703中。位於鄰近的閘極溝槽之間的臺面結構上的接觸溝槽，容納了肖特基二極體的勢壘金屬717。可以用覆蓋著源極區713和絕緣物720的源極金屬722填充接觸溝槽。
摻雜遮罩區719可以形成在肖特基溝槽底部附近的外延層中。摻雜遮罩區719可以用導電類型與外延層703相反的摻雜物摻雜。與之類似，二極體溝槽頂部附近的摻雜遮罩區719’在溝槽的任一側，可以選擇用導電類型與外延層703相反的摻雜物摻雜。沿淺溝槽的側壁形成肖特基二極體區718。
儘管MOSFET和肖特基二極體並不沿同一個臺面結構，但是元件700的結構仍然具有許多優勢。例如，肖特基二極體溝槽獨立於用於製備MOSFET和二極體接觸區719的溝槽，不需要比本體結更深。此外，根據接觸溝槽的頻率，可以調節肖特基區域。而且， 元件700中的肖特基二極體具有雙重遮罩的優勢一一鑒於接觸溝槽和遮罩區719和719’。元件700的結構可能有很高的串聯肖特基電阻，但是如果肖特基區域中的臺面結構寬度較寬的話，就會克服該缺點。然而，溝槽較寬會限制按比例縮小元件尺寸的能力，並且降低溝槽遮罩。當所有的因素都在考慮範圍之內時，肖特基區域較大的可調性，獨立於肖特基溝槽，以及雙重遮罩的重要性可以超越其他的考慮因素。
利用標準處理技術，將用於限定所需結構的至少一遮罩，根據需要稍作變化，就可以製備上述整合結構。作為示例，但不作為侷限，製備該結構可以從重摻雜基板401開始，輕摻雜的外延層403形成在重摻雜基板401上，如第8A圖所示。可以用相反的導電類型摻雜外延層403(例如穿過正確配置的遮罩利用離子植入)，形成本體區405、405’，並且限定含有外延層403裸露部分的臺面結構408，如第8B圖所示。溝槽407的製備可以在這種摻雜之前或之後進行，並且佈滿了絕緣的電介質材料409。溝槽407中未被電介質材料409佔據的部分，可以用導電材料(例如多晶矽)填充，以限定閘極區411，如第8C圖所示。藉由合適的遮罩，本體區405、405’所選部分的額外摻雜，可以構成源極區413。
接觸溝槽415的製備可以在製備源極區413之前或之後進行，例如藉由適當配置的接觸遮罩的刻蝕。藉由適當配置的遮罩進一步刻蝕，可以在接觸溝槽415的底部或邊緣處的每個摻雜本體區405、405’內，形成肖特基二極體的摻雜遮罩區419。勢壘金屬可以佈滿接觸溝槽415。閘極區411以及外延層403的裸露部分可以用絕緣物(例如氧化物)覆蓋，保留開口處，藉由開口，源極金屬可 以接觸源極區413，並且填充接觸溝槽415的剩餘部分。
本發明示例提供的整合結構具有比原有結構簡單、低製造成本和避免形成大的逆洩露電流的明顯優勢。
儘管已經參照具體的較佳示例，對本發明做了詳細介紹，但是仍然可能存在其他示例。因此，所附的申請專利範圍的意圖及範圍，不應侷限於文中的較佳示例。相反地，本發明的範圍應由所附的申請專利範圍及其全部等效內容決定。
除非特別聲明，否則本說明書中的所有可選件(包括任意附加的申請專利範圍、摘要以及圖式)都可以用目的相同、等價或類似的可選件代替。因此，除非特別聲明，所述的每個可選件僅僅是一系列等價或類似可選件的其中之一。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。
400‧‧‧整合結構
401‧‧‧基板
403‧‧‧外延層
405、405’‧‧‧本體區
407‧‧‧溝槽
408‧‧‧臺面結構
409‧‧‧電介質材料
411‧‧‧閘極區
413‧‧‧源極區
415‧‧‧接觸溝槽
419‧‧‧遮罩區

Claims (24)

  1. 一種在金氧半場效電晶體元件中整合肖特基之結構，其包括：a)複數個形成在一基板組合中的溝槽，沿該基板組合的整體縱方向延伸，在該複數個溝槽之間構成複數個臺面結構，該溝槽都用導電材料填充，並且藉由薄層的電介質材料與溝槽壁分開，形成至少一金氧半場效電晶體元件的閘極區；b)導電類型與該基板組合相反的具有一第一導電類型的二摻雜本體區形成在各該臺面結構中，該二摻雜本體區之間被該基板組合的一裸露部分分開，在各該摻雜本體區構成一接觸溝槽，沿該基板組合的縱深方向部分延伸，其中，接觸溝槽的一個末端使將該二摻雜本體區分開的該基板組合的垂直側壁裸露出來；c)具有一第二導電類型的二摻雜源極區形成在各該摻雜本體區內，該二摻雜源極區位於該接觸溝槽的相對兩側，且與該接觸溝槽的各側邊邊緣相鄰；以及d)含有一肖特基勢壘金屬的一肖特基二極體，該肖特基勢壘金屬形成在該二摻雜本體區的各該接觸溝槽中，在該肖特基勢壘金屬和將該二摻雜本體區分開的該基板組合之該裸露部分的裸露在該接觸溝槽中的垂直側壁之間的交界處形成一肖特基結。
  2. 如申請專利範圍第1項所述之結構，其中更包括具有該第一導電類型的一摻雜遮罩區，形成在各該摻雜本體區中，該摻雜遮罩區沿該摻雜本體區的整體縱深方向延伸到將該二摻雜本體區分開的該基板組合的該裸露部分的一部分裸露在該接觸溝槽中的垂直側 壁中。
  3. 如申請專利範圍第2項所述之結構，其中該摻雜遮罩區為重摻雜。
  4. 如申請專利範圍第1項所述之結構，其中該基板組合是一基板。
  5. 如申請專利範圍第1項所述之結構，其中該基板組合是具有一外延層形成在上面的一基板。
  6. 如申請專利範圍第5項所述之結構，其中將該二摻雜本體區分開的該基板組合之該裸露部分是該外延層。
  7. 如申請專利範圍第2項所述之結構，其中該摻雜遮罩區包圍著該摻雜本體區內形成的該接觸溝槽的所有的底部拐角，並且延伸到該基板組合之該裸露部分裸露在該接觸溝槽中的垂直側壁的底部中。
  8. 如申請專利範圍第6項所述之結構，其中更包括具有該第一導電類型的額外的一摻雜遮罩區，形成在將該二摻雜本體區分開的該基板組合的該裸露部分的頂面中。
  9. 如申請專利範圍第2項所述之結構，其中該摻雜遮罩區沿該摻雜本體區形成的該接觸溝槽的整體寬度或長度延伸，該摻雜遮罩區也形成在該基板組合之該裸露部分的一部分裸露在該接觸溝槽中的垂直側壁中，該摻雜遮罩區沿裸露的垂直側壁的整體長度延伸。
  10. 如申請專利範圍第1項所述之結構，其中該第一導電類型為p型。
  11. 如申請專利範圍第1項所述之結構，其中該第二導電類型為n型。
  12. 如申請專利範圍第1項所述之結構，其中該肖特基二極體和該至少一金氧半場效電晶體元件整合在不同的鄰近該臺面結構中。
  13. 一種在金氧半場效電晶體元件中整合肖特基之方法，其包括： a)在一基板組合中製備複數個溝槽，並且沿該基板組合的整體縱深方向延伸，在該複數個溝槽之間構成複數個臺面結構；b)用導電材料填充各該溝槽，與溝槽壁藉由一薄層電介質材料分開，構成至少一金氧半場效電晶體元件的閘極區；c)在各該臺面結構中製備導電類型與各該臺面結構內的該基板組合相反的具有一第一導電類型的二摻雜本體區，該基板組合的一裸露部分將該二摻雜本體區分開，在各該摻雜本體區形成一接觸溝槽，沿該基板組合的一部分縱深方向延伸，其中，接觸溝槽的一個末端使將該二摻雜本體區分開的該基板組合的垂直側壁裸露出來；d)在各該摻雜本體區內，製備具有一第二導電類型的二摻雜源極區，該二摻雜源極區位於該接觸溝槽的相對兩側，且與該接觸溝槽的各側邊邊緣相鄰；以及e)在該二摻雜本體區的各該接觸溝槽內，製備含有一肖特基勢壘金屬的一肖特基二極體，在該肖特基勢壘金屬和將該二摻雜本體區分開的該基板組合的該裸露部分的裸露在該接觸溝槽中的垂直側壁之間的交界處，該肖特基勢壘金屬形成一肖特基結。
  14. 如申請專利範圍第13項所述之方法，其中更包括在各該摻雜本體區內製備具有該第一導電類型的一摻雜遮罩區，該摻雜遮罩區沿該摻雜本體區的整體縱深方向延伸到將該二摻雜本體區分開的該基板組合的該裸露部分的一部分裸露在該接觸溝槽中的垂直側壁中。
  15. 如申請專利範圍第14項所述之方法，其中該摻雜遮罩區為重摻雜。
  16. 如申請專利範圍第13項所述之方法，其中該基板組合是一基板。
  17. 如申請專利範圍第13項所述之方法，其中該基板組合是上方具有一外延層的一基板。
  18. 如申請專利範圍第17項所述之方法，其中將該二摻雜本體區分開的該基板組合的該裸露部分為該外延層。
  19. 如申請專利範圍第14項所述之方法，其中該摻雜遮罩區包圍著該摻雜本體區內形成的該接觸溝槽的所有底部拐角，並且延伸到該基板組合的該裸露部分裸露在該接觸溝槽中的垂直側壁的底部中。
  20. 如申請專利範圍第14項所述之方法，其中更包括在將該二摻雜本體區分開的該基板組合的該裸露部分的頂面內，製備具有該第一導電類型的一額外摻雜遮罩區。
  21. 如申請專利範圍第14項所述之方法，其中該摻雜遮罩區沿該摻雜本體區內形成的該接觸溝槽的側壁的整體寬度或長度延伸，該摻雜遮罩區更形成在該基板組合之該裸露部分的一部分裸露在該接觸溝槽中的垂直側壁中，該摻雜遮罩區沿裸露的垂直側壁的整體長度延伸。
  22. 如申請專利範圍第13項所述之方法，其中該第一導電類型為p型。
  23. 如申請專利範圍第13項所述之方法，其中該第二導電類型為n型。
  24. 如申請專利範圍第13項所述之方法，其中該肖特基二極體和該至少一金氧半場效電晶體元件集成在不同的鄰近該臺面結構中。
TW101108798A 2011-04-04 2012-03-15 在金氧半場效電晶體元件中整合肖特基之結構及其方法 TWI464885B (zh)

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