TWI579932B - 與金屬氧化物場效應電晶體集成的增強型耗盡積累/反轉通道器件及其製造方法 - Google Patents

與金屬氧化物場效應電晶體集成的增強型耗盡積累/反轉通道器件及其製造方法 Download PDF

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TWI579932B
TWI579932B TW104140867A TW104140867A TWI579932B TW I579932 B TWI579932 B TW I579932B TW 104140867 A TW104140867 A TW 104140867A TW 104140867 A TW104140867 A TW 104140867A TW I579932 B TWI579932 B TW I579932B
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gate
trench
trenches
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TW201622015A (zh
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馬督兒 博德
燮光 雷
哈姆紥 依瑪茲
金鐘五
時謙 伍
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萬國半導體股份有限公司
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Description

與金屬氧化物場效應電晶體集成的增強型耗盡積累/反轉通道 器件及其製造方法
本發明涉及一種半導體功率器件，更確切地說是關於與功率MOSFET集成的積累/反轉通道FET及其製備方法。
半導體器件常用於功率電子電路中的電流切換。例如，開關器件的一種常用形式是功率MOSFET(金屬氧化物場效應電晶體)。功率MOSFET用作同步整流器，顯著提高了直流-直流降壓轉換器或同步整流器等應用中的傳導損耗。例如，傳統的降壓轉換器擁有一個高端MOSFET作為控制MOSFET，以及一個低端MOSFET作為同步MOSFET。低端MOSFET因其導通時間間隔與體二極體的傳導時間同步，可用作同步整流器。通常來說，當低端MOSFET斷開時，高端MOSFET接通，反之亦然。在高端MOSFET斷開時，隨著負載電流從源極流至汲極，低端MOSFET在其第三象限(VDS<0，ID<0)傳導電流。
當降壓轉換器在高速度下工作，高端和低端MOSFET同時接通時，會發生擊穿狀態，導致擊穿電流在輸入端和接地端之間流動。擊穿狀態導致過度的損耗和效率損失。為了避免擊穿問題，要在高端MOSFET斷開的時間和低端MOSFET接通的時間之間提供死區時間，防 止高端和低端MOSFET同時接通。
任何一個帶有正常源極-本體短接的高端和低端MOSFET，都含有一個本徵體二極體，在其汲極和本體區之間的結處。在死區時間內，感應電流流經較低的MOSFET體二極體，在耗盡區產生存儲電荷。必須清除該存儲電荷，使體二極體的正向閉鎖特性得到恢復。該體二極體通常具有很低的反向恢復性能，會對轉換器的效率產生不良影響。因此，需要使用正向偏壓很低的二極體。
配有P-N結的功率MOSFET具有很多不良的特性，包括：正向傳導損耗很大，在正向偏壓下運行時在本體-外延結處存儲電荷，當功率MOSFET從正向偏壓切換至反向偏壓時過量存儲的少子電荷會產生很大的恢復電流和電壓過沖，在快速切換時產生射頻干擾等。以上這些特性會對器件造成不必要的負擔，導致次優性能。
在許多應用中，包括功率MOSFET(即帶有源極和汲極並聯的體二極體的MOSFET)中，已經使用肖特基二極體代替P-N結二極體。肖特基二極體具有多種優於P-N二極體的優良特性，尤其是在功率MOSFET結構中。肖特基二極體在正向傳導時具有很低的正向壓降，可以降低器件的功率耗散，產生較低的傳導損耗。肖特基的傳導是藉由多數載流子進行的，因此在器件切換時不會發生少子電荷存儲效應。所以在功率MOSFET結構中，最好使用肖特基二極體。
隨著肖特基二極體在功率MOSFET中的採用逐漸推廣，改進器件結構，降低傳導損耗也變得日益重要。一個特別重要的考慮因素是減小肖特基二極體所占的半導體基板表面積。減小肖特基二極體所占的表面積，是降低製造成本，進一步減小電子器件的尺寸和形狀，以便獲得輕便性及其他功能提高的關鍵。
因此，必須在功率半導體設計和製造領域中提出在MOSFET器件中集成第三象限傳導結構的新型器件結構和製造方法。
正是在這樣的背景下，提出了本發明的各個方面。
本發明的一個方面在於提出一種新型改良的器件結構和製造方法，用於製備集成的溝槽閘極MOSFET和ACCUFET(Accumulation Mode FET)或耗盡的本體FET，以改善現有技術中的一個或多個問題。
簡單地說，本發明的各個方面包括在一個第一導電類型的重摻雜半導體基板上，結合一個或多個場效應電晶體以及一個ACCUFET(Accumulation Mode FET，積累型場效應電晶體)或耗盡本體FET的結構。該結構包括多個閘極溝槽，形成在半導體基板上方的第一導電類型的外延區中。一個或多個接觸溝槽形成在外延區中，每個外延區都在兩個鄰近的閘極溝槽之間。一個或多個第一導電類型的重摻雜源極區，形成在外延層頂部中，每個外延區都在一個相應的接觸溝槽和一個相應的閘極溝槽之間。歐姆接觸包括一個勢壘金屬，金屬插頭形成在每個接觸溝槽內。每個閘極溝槽都用導電材料至少部分填充，導電材料與一層電介質材料的溝槽側壁分隔開，以形成一個或多個場效應電晶體的閘極區。一個與第一導電類型相反的第二導電類型的重摻雜阱區，位於每個接觸溝槽底部附近。重摻雜阱區和閘極溝槽之間縫隙的水平寬度約為0.05μm至0.2μm。
在一些實施例中，該結構的特點在於閾值電壓的範圍約為0.2V至0.4V左右。
在一些實施例中，一個或多個場效應電晶體為分裂閘電晶體。
在一些實施例中，一個第二導電類型的輕摻雜區位於外延區 中，以及一個重摻雜阱區和一個閘極溝槽之間。第二導電類型的輕摻雜區的深度延伸到重摻雜阱區的底部附近。
閱讀實施例的以下詳細說明並參照各種圖式，本發明的這些特點和優勢對於本領域的技術人員來說，無疑將顯而易見。
100、201、300、400、400A、500、500A‧‧‧集成結構
101、202、301、401‧‧‧基板
103、403‧‧‧外延層
105、200-1、200-2、200-3、200-4、200-5、305‧‧‧溝槽
107、206、307、411‧‧‧閘極區
216‧‧‧導電材料
108、303、308‧‧‧絕緣層
109、309‧‧‧本體區
111、212、311、413‧‧‧源極區
113、317‧‧‧摻雜區
115、218、315‧‧‧肖特基勢壘金屬
117‧‧‧摻雜遮罩區
119、210、319‧‧‧肖特基二極體
204‧‧‧薄層電介質
208、419‧‧‧阱區
214‧‧‧重本體區
316、415‧‧‧接觸溝槽
407‧‧‧閘極溝槽
409‧‧‧閘極氧化物
412‧‧‧遮罩閘極電極
417‧‧‧勢壘金屬
418‧‧‧金屬插頭
422‧‧‧源極金屬
425‧‧‧輕摻雜區
430‧‧‧汲極接頭
440‧‧‧檯面結構
450‧‧‧區域
w‧‧‧寬度
g‧‧‧縫隙
A-A'、B-B'、C-C'、D-D'‧‧‧剖面線
第1A圖至第1C圖為現有技術中的集成結構的剖面示意圖；第2A圖表示依據本發明的一個實施例所顯示的一種與MOSFET集成的積累型FET的剖面示意圖；第2B圖表示第2A圖所示的集成結構正面部分的三維圖；第2C圖表示第2B圖所示的一部分集成結構沿A-A’面的剖面圖；第2D圖表示第2B圖所示的一部分集成結構沿B-B’面的剖面圖；第2E圖表示依據本發明的一個實施例所顯示的一種與ACCUFET集成的分裂閘電晶體的剖面示意圖；第3A圖表示依據本發明的一個實施例所顯示的一種與MOSFET集成的耗盡通道MOSFET的剖面示意圖；第3B圖表示第3A圖所示的集成結構正面部分的三維圖；第3C圖表示第3B圖所示的一部分集成結構沿C-C’面的剖面圖；第3D圖表示第3B圖所示的一部分集成結構沿D-D’面的 剖面圖；第3E圖表示依據本發明的一個實施例所顯示的一種與耗盡本體FET集成的分裂閘電晶體的剖面示意圖。
第4A圖至第4D圖表示依據本發明的一個實施例所顯示的一種與ACCUFET或耗盡本體MOSFET集成的功率MOSFET的俯視圖。
以下結合圖式，藉由詳細說明較佳的具體實施例，對本發明做進一步闡述。
引言
存在多種結構，可以將肖特基二極體與MOSFET集成以構成功率MOSFET。然而，這些結果都受到許多不良特性的影響，使它們次於功率MOSFET器件。第1A圖至第1C圖表示三種現有技術的結構。
第1A圖表示與多個MOSFET器件集成的原有技術的結構，以及與那些MOSFET器件並聯的結型勢壘肖特基(JBS)。集成結構100包括一個帶有n型外延層103的n+型基板101。多個MOSFET嵌入在集成結構100中。溝槽105位於外延層103中，並用被絕緣層108包圍的導電材料107填充，從而在集成結構100中構成每個MOSFET的每個閘極區107。外延層103包圍著每個溝槽的區域，用p-型材料摻雜，構成每個MOSFET的本體區109。在靠近溝槽105的鄰近側壁部分，用n+型導電摻雜物摻雜每個本體區109，構成每個MOSFET器件的源極區111。N+基板101作為每個MOSFET的汲極區。
結型勢壘肖特基(JBS)119也嵌入在集成結構100中。肖特基二極體119包括肖特基勢壘金屬115，直接形成在n-摻雜區113上方。 N-摻雜區113形成在外延層103中，外延層103在兩個MOSFET本體區109之間的區域中。肖特基結形成在肖特基勢壘金屬115和n-摻雜區113之間的交界面處。因此，勢壘金屬115構成肖特基二極體的陽極，基板101構成肖特基二極體的陰極。另外，一個或多個p+摻雜遮罩區117可以形成在n-摻雜區113中，構成P-N結，用於夾斷肖特基接頭下方的通道區，防止從正向偏壓向反向偏壓切換時形成很大的反向漏電流。
雖然這種特殊結構的確可以製備帶有肖特基二極體的功率MOSFET器件，但是會造成因p+遮罩引起的低肖特基表面積的缺點。對於擊穿電壓較大的肖特基二極體來說，通常需要較深的p+結。因此，對於高擊穿電壓的JBS來說，肖特基表面積的利用率相當低。肖特基二極體的製備需要MOSFET中的專用區域，使晶片面積增大。
第1B圖表示一種可選的原有技術集成結構，包括一個單片集成的肖特基二極體以及一個高性能的溝槽閘極MOSFET。集成結構201包括多個溝槽200-1、200-2、200-3、200-4和200-5，形成圖案並在n型基板202中刻蝕。然後，沿溝槽200的側壁製備一個薄層電介質204，沉積導電材料206，基本填滿每個溝槽200，為集成結構201的每個MOSFET構成一個閘極區。除了要製備肖特基二極體的那些溝槽(例如200-3和200-4)以外，在溝槽200之間，形成一個p-型阱208。P-型阱208為集成結構201的每個MOSFET，構成本體區。然後，在p-型阱區208中，形成N+型源極區212。基板202構成集成結構201的每個MOSFET的汲極區。在製備P+重本體區214之前或之後，在p-阱區208中形成N+源極區212。可以在基板的表面上形成圖案並沉積一層導電材料216(例如鎢化鈦(TiW)或氮化鈦(TiN))，以便與N+源極區212相接觸。
藉由在不包含p-型阱的區域中，在基板202上方沉積肖特 基勢壘金屬218，在集成結構201中形成一個肖特基二極體210。肖特基勢壘金屬218構成肖特基二極體的陽極，基板構成肖特基二極體210的陰極。肖特基二極體的兩側被MOSFET溝槽200包圍。
由於不需要再在肖特基勢壘金屬218和基板202之間製備p-型摻雜區，以避免反向偏壓傳導時出現很大的反向漏電流，因此該結構解決了肖特基表面積的利用率問題。而且，隨著在肖特基二極體的陰極建立起電壓，包圍著二極體的MOSFET溝槽200-3、200-4構成一個耗盡區，有助於降低反向偏壓產生的二極體漏電流。此外，可以調節溝槽200-3和200-4之間的距離W，使每個溝槽周圍正在生長的耗盡區在中間重疊，從而夾斷肖特基勢壘金屬218和基板202之間的漂流區。
雖然，第1B圖所示的集成結構較好地利用了肖特基表面積，但是也要付出代價，僅僅為了製備肖特基二極體，就要在MOSFET之間分配特定的未摻雜區。這使製備過程包含了額外的處理步驟。此外，該集成結構本質上與JBS二極體具有相同的缺點，就是仍然需要較大尺寸的晶片。
第1C圖表示另一種集成結構，在每個MOSFET晶胞中含有一個MOSFET和肖特基二極體。集成結構300包括一個帶有n型外延層303的n+型基板301。多個MOSFET嵌入在集成結構300中。在外延層303中製備溝槽305，並用絕緣層303包圍的導電材料307填充，以便在集成結構300中形成每個MOSFET的每個閘極區307。包圍著每個溝槽的區域用p型材料填充，構成每個MOSFET的本體區309。在溝槽305的鄰近側壁上，每個本體區309都用n+型導電材料311填充，以便形成每個MOSFET器件的源極區311。最終，n+基板101為每個MOSFET提供一個汲極區。
肖特基二極體319也嵌入在集成結構300的每個晶胞中。接觸溝槽316最初形成在每個MOSFET的本體區309中，使接觸溝槽316的尖端在本體區309上方延伸到外延區303中。每個接觸溝槽316都用肖特基勢壘金屬315填充，以便在接觸溝槽316的尖端和外延區303之間的交界面處形成一個肖特基結。內襯接觸溝槽316的肖特基勢壘金屬315，作為肖特基二極體319的陽極，基板301作為肖特基二極體319的陰極。另外，一個或多個p+摻雜區317沿接觸溝槽316的側壁，形成在本體區309中，以增強與本體區的接觸。
藉由消除在MOSFET之間分配指定區域的必要性，以便形成肖特基二極體，在MOSFET有源器件區內(即MOSFET器件的本體區內)集成肖特基二極體，該結構似乎可以修正表面積利用率的問題。
雖然，第1C圖所示的集成結構有效利用了肖特基表面積，消除了為製備肖特基二極體保留額外的器件區域的必要性，但是它仍然受到許多不良性能的影響。由於肖特基勢壘金屬必須與n-型材料直接接觸，因此，為了正確製備肖特基二極體，在p-型本體區內製備的接觸溝槽的深度必須大於本體結的深度。為使每個阱都獲得所需深度，必須採取額外的製備工藝(例如補償摻雜本體區)。該特殊結構複雜的設計體系，使得製備工藝更加複雜、昂貴。遺憾的是，補償摻雜本體區在製備過程中也不好控制。接觸溝槽深度的變化也會影響肖特基的性能。
ACCUFET器件
第2A圖至第2D圖表示依據本發明的一個方面，一種含有MOSFET器件和第三象限傳導器件的集成結構400的不同視圖。第2A圖表示集成結構400的剖面示意圖。集成結構400包括一個或多個積累型FET(ACCUFET)器件，可以並聯，形成一個功率MOSFET。在第三維 度上，還可以包含一個帶有ACCUFET的可選擇的肖特基二極體。集成結構400嵌入在基板401中。作為示例，但不作為局限，基板可以由矽、二氧化矽、氧化鋁、藍寶石、鍺、砷化鎵(GaAs)、矽或鍺的合金、磷化銦(InP)或可以在上面沉積電子器件(例如電晶體、二極體等)的其他任意材料構成。作為示例，但不作為局限，可以重摻雜基板401，形成n+型基板。汲極接頭430電連接到基板401，構成每個MOSFET器件的汲極區。
在基板401上生長一個外延層403。作為示例，但不作為局限，外延層403可以是一個n型層。可以輕摻雜外延層403，以承載較高的器件擊穿電壓，但是這樣會增大器件的內電阻。
在外延層403中製備多個閘極溝槽407。用導電材料411基本填滿溝槽407，導電材料411與溝槽壁被一層電介質材料409隔開。填充每個溝槽的導電材料411作為每個MOSFET器件的閘極區。作為示例，但不作為局限，導電材料可以是多晶矽，電介質材料可以是二氧化矽。
在外延層403中製備一個或多個接觸溝槽415，每個都在兩個鄰近的閘極溝槽407之間。另外，在外延層403的頂部，製備導電類型與外延層相同的一對或多對重摻雜源極區413，每個都在接觸溝槽415和閘極溝槽407的電介質材料409中間。作為示例，但不作為局限，源極區413可以是N+源極區。此外，導電類型與外延層403不同的重摻雜阱區419可以形成在外延區403中，以及接觸溝槽415的底部周圍。作為示例，但不作為局限，阱區419可以是p+型阱區。P+阱區419可以藉由先垂直注入，然後水平擴散形成。要注意的是，雖然在理論上，p+阱區419的頂部可以一直延伸到N+源極區413的底部，但是p+注入的處理限制使得這樣無法實現。由於源極區413和P+阱區419的重摻雜水平(例如在 1e19cm-3範圍內)，利用標準的勢壘金屬，可以形成它們的歐姆接觸。
作為示例，但不作為局限，勢壘金屬417可以是鈦(Ti)或氮化鈦(TiN)。除了勢壘金屬以外，接觸溝槽415可以用金屬插頭418填充。作為示例，但不作為局限，金屬插頭可以由鎢(W)製成。
源極金屬422穿過接觸溝槽415，觸及p+阱區419。作為示例，但不作為局限，源極金屬可以是Al或Cu或其他合適的金屬。
雖然希望閾值電壓越低越好，但是低閾值電壓Vth會導致較高的漏電流。因此，降低閾值電壓的極限，就是當器件斷開時，器件可以承受的漏電流。由於阱區419和閘極溝槽407之間的通道被閘極411以及附近的阱區419完全耗盡，因此可以藉由在閘極氧化物409和阱區419之間設計一個縫隙g，形成勢壘，防止器件斷開時產生從汲極到源極的漏電流。也就是說，為了獲得較低的閾值電壓Vth，閘極溝槽407中的閘極氧化物409和阱區419之間的縫隙g必須很小。在一些實施例中，閘極溝槽407和阱區419之間的縫隙g的水平寬度約為0.05μm至0.2μm左右。ACCUFET或耗盡本體MOSFET的長度大約在0.1μm至0.35μm的範圍內。
帶有低Vth的ACCUFET 400的關鍵參數是N-通道的長度，這由阱區419的垂直厚度、閘極氧化物409和阱區419之間的縫隙g的水平寬度所決定，與閘極氧化物409和接觸溝槽415之間的縫隙到阱區的寬度w、作為N-通道的縫隙g中外延區403的摻雜有關。藉由調節這些參數，可以設計閾值電壓Vth，使其低至0.2V至0.4V左右。
依據本發明所述的一種器件可以比帶有肖特基二極體的傳統器件接通和傳導更多次。尤其是，它允許第三象限上兩種傳導模式。正源極偏壓可以在低偏壓(0.3V)下打開通道，允許第三象限傳導。閘極所 加的正偏壓可以利用極低的Rds,on，進行MOSFET型傳導。
第2B圖表示不含源極金屬422層、勢壘金屬417以及金屬插頭418的集成結構400正面的三維視圖。如圖所示，阱區419靠近閘極溝槽407中的閘極氧化物409，形成勢壘，避免器件斷開時產生從汲極到源極的漏電流。
第2C圖表示集成結構400的ACCUFET沿A-A’面的剖面圖。第2D圖表示帶有所示勢壘金屬417的集成結構400的接面場效電晶體(JFET)沿B-B’面的剖面圖。如圖所示，肖特基二極體垂直形成在勢壘金屬417和外延層403之間的交界面處。
第2E圖表示依據本發明的另一方面，結合了分裂閘電晶體和ACCUFET的集成結構400A的剖面圖。結構400A中除了閘極溝槽包括一個在底部的遮罩閘極電極412以及一個在頂部的閘極電極411之外，其他都與結構400類似。要注意的是，遮罩電極412增加了控制從汲極到源極洩露的額外優勢。
集成耗盡本體FET的MOSFET器件，用於第三象限傳導。
第3A圖至第3D圖表示依據本發明的一個方面，含有MOSFET器件和耗盡本體MOSFET的集成結構500的不同視圖。要注意的是，對於“耗盡本體MOSFET”、“耗盡本體FET”、“耗盡通道MOSFET”以及“耗盡通道FET”等術語，指示相同結構時本領域的技術人員可互換使用。第3A圖表示集成結構500的剖面示意圖。集成結構500包括一個或多個耗盡通道FET器件，這些器件可以並聯，形成一個功率MOSFET。在第三維度上，還可以包含帶有耗盡本體FET和MOSFET的可選擇的肖特基二極體。
結構500中除了一個導電類型與外延層相反的輕摻雜區 425，在源極區413和外延區403之間，以及閘極溝槽407和阱區419之間，其他都與第2A圖所示的結構400類似。作為示例，但不作為局限，輕摻雜區425可以是一個P型區。
除了上述參數值為，結合了耗盡通道MOSFET、閾值電壓很低的集成結構500的關鍵參數，包括輕摻雜區425的摻雜，可以在1e16cm-3至1e17cm-3範圍內。P+阱419的摻雜濃度可以在5e18cm-3至1e19cm-3範圍內。
第3B圖表示不含源極區413和金屬插頭418的集成結構500的肖特基部分的三維圖。另外，第3B圖表示，在勢壘金屬417下方，有一個檯面結構440形成在兩個閘極溝槽在降低半導體外延層403中，閘極溝槽中沒有摻雜阱區419。根據圖例，兩種不同類型的肖特基二極體可以由勢壘金屬垂直構成。確切地說，如第3C圖所示，溝槽MOS勢壘肖特基(TMBS，Trench MOS Barrier Schottky)垂直形成在檯面結構440處。在TMBS中，檯面結構440中多數電荷載流子和閘極溝槽側壁上的導體之間的電荷耦合，改變了肖特基接頭下方的電場形狀，降低了反向漏電流，提高了擊穿屬性。此外，如第3D圖所示，結型勢壘肖特基(JBS)在輕摻雜區425和接觸溝槽415之間，垂直形成到檯面結構440。
第3E圖表示依據本發明的另一方面，結合了分裂閘電晶體和肖特基二極體的集成結構500A的剖面圖。結構500A中除了閘極溝槽包括一個在底部的閘極電極412以及一個在頂部的閘極電極411之外，其他都與結構500類似。
有多種可能的方式，將ACCUFET或耗盡本體MOSFET二極體與功率MOSFET器件集成。作為示例，但不作為局限，第4A圖至第4D圖表示依據本發明的各個方面，功率MOSFET的俯視平面圖。阱區419 位於閘極區411之間。除了區域450之外，大多數的區域都是帶有p-本體440的正規MOSFET區。依據本發明的一個方面，區域450是不含p-本體440的區域，以製備ACCUFET。為了縮小阱區419和閘極氧化物409之間的縫隙，可以如第4C圖所示調節溝槽佈局，使其在製備ACCUFET的區域450處較寬，或者如第4D圖所示調節接觸佈局。
儘管本發明依據現有的較佳實施例進行了詳細說明，但應明確本說明並不用於局限。例如，雖然上述說明是指n-通道器件，但是藉由轉換摻雜區的導電類型，就可將本發明用於p-通道器件。閱讀上述說明後，本發明的各種可選和修正方案對於本領域的技術人員無疑將顯而易見。因此，應由所附的申請專利範圍及其全部等效內容決定本發明的真實意圖及範圍。
400‧‧‧集成結構
401‧‧‧基板
403‧‧‧外延層
407‧‧‧閘極溝槽
409‧‧‧閘極氧化物
411‧‧‧閘極區
413‧‧‧源極區
415‧‧‧接觸溝槽
417‧‧‧勢壘金屬
418‧‧‧金屬插頭
419‧‧‧阱區
422‧‧‧源極金屬
430‧‧‧汲極接頭

Claims (14)

  1. 一種器件結構，其包括：多個閘極溝槽，形成在第一導電類型的半導體基板上方的該第一導電類型的外延區中，每個閘極溝槽都用導電材料至少部分填滿，導電材料與溝槽壁被一層電介質材料隔開，構成一個閘極；一個或多個接觸溝槽，形成在外延區中，每個接觸溝槽都位於兩個鄰近的閘極溝槽之間，其中一個與第一導電類型相反的第二導電類型的重摻雜阱區位於所述的一個或多個接觸溝槽的底部附近，重摻雜阱區和多個閘極溝槽中的其中一個閘極溝槽之間的第一導電類型的外延區的一部分的水平寬度為0.05μm至0.2μm之間；以及一個或多個第一導電類型的重摻雜源極區，形成在外延區頂部，每個重摻雜源極區都在一個相應的接觸溝槽和一個相應的閘極溝槽之間；以及一個勢壘金屬，形成在沒有重摻雜源極區的外延區中的檯面結構上方，其中檯面結構形成在兩個接觸溝槽和位於外延區中的兩個第二導電類型的輕摻雜區之間。
  2. 如申請專利範圍第1項所述之器件結構，其中每個閘極溝槽都有一個閘極區，在閘極溝槽頂部，以及一個遮罩閘極區，在閘極溝槽底部。
  3. 如申請專利範圍第1項所述之器件結構，其中第一導電類型為N-型，第二導電類型為P-型。
  4. 如申請專利範圍第1項所述之器件結構，其中第一導電類型為P-型，第二導電類型為N-型。
  5. 如申請專利範圍第1項所述之器件結構，其中一個或多個第二導電類型的輕摻雜區都位於外延區中，其中一個或多個第二導電類型的輕摻雜區包括一個區域，形成在一個重摻雜阱區和一個閘極溝槽之間。
  6. 如申請專利範圍第1項所述之器件結構，其中該器件結構的閾值電壓在0.2V至0.4V的範圍內。
  7. 如申請專利範圍第1項所述之器件結構，其中外延區的摻雜濃度為1e16cm-3至5e16cm-3之間。
  8. 如申請專利範圍第4項所述的器件結構，其中第二導電類型的輕摻雜區的摻雜濃度在5e16cm-3至1e17cm-3之間。
  9. 一種器件結構，其包括：多個閘極溝槽，形成在第一導電類型的半導體基板上方的該第一導電類型的外延區中，每個閘極溝槽都用導電材料至少部分填滿，導電材料與溝槽壁被一層電介質材料隔開，構成一個閘極；一個或多個接觸溝槽，形成在外延區中，每個接觸溝槽都位於兩個鄰近的閘極溝槽之間，其中一個與第一導電類型相反的第二導電類型的重摻雜阱區位於所述的一個或多個接觸溝槽的底部附近，重摻雜阱區和多個閘極溝槽中的其中一個閘極溝槽之間的缝隙的水平寬度為0.05μm至0.2μm之間；其中藉由加寬部分閘極溝槽，可以調節重摻雜阱區和閘極溝槽之間縫隙的水 平寬度；一個或多個第一導電類型的重摻雜源極區，形成在外延區頂部，每個重摻雜源極區都在一個相應的接觸溝槽和一個相應的閘極溝槽之間；以及一個勢壘金屬，形成在沒有重摻雜源極區的外延區中的檯面結構上方，其中檯面結構形成在兩個接觸溝槽和兩個第二導電類型的輕摻雜區之間。
  10. 一種製造器件結構的方法，其包括：在第一導電類型的半導體基板上方的第一導電類型的外延區中，製備多個閘極溝槽；用導電材料至少部分填滿每個溝槽，導電材料與溝槽壁被一層電介質材料隔開，形成一個閘極；在外延區中，製備一個或多個接觸溝槽，每個接觸溝槽位於兩個鄰近的閘極溝槽之間；在所述的一個或多個接觸溝槽底部附近的外延區中，製備與第一導電類型相反的第二導電類型的重摻雜阱區，其中重摻雜阱區和多個閘極溝槽中的其中一個閘極溝槽之間的第一導電類型的外延區的一部分的水平寬度約為0.05μm至0.2微米左右；在外延區頂部，製備一個或多個第一導電類型的重摻雜源極區，每個重摻雜源極區都在一個相應的接觸溝槽和一個相應的閘極溝槽之間；以及在不含重摻雜源極區的外延區中的檯面結構上方，製備一個勢壘金屬，其中檯面結構形成在兩個接觸溝槽和位於外延區中的 兩個第二導電類型的輕摻雜區之間。
  11. 如申請專利範圍第10項所述之方法，其中每個閘極溝槽都有一個閘極區，在閘極溝槽頂部，以及一個遮罩閘極區，在閘極溝槽底部。
  12. 如申請專利範圍第11項所述之方法，其中第一導電類型為N-型，第二導電類型為P-型。
  13. 如申請專利範圍第10項所述之方法，其中第一導電類型為P-型，第二導電類型為N-型。
  14. 如申請專利範圍第10項所述之方法，其進一步包括在外延區中，製備一個或多個第二導電類型的輕摻雜區，其中一個或多個第二導電類型的輕摻雜區包括一個區域，形成在一個重摻雜阱區和一個閘極溝槽之間。
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