CN105702676A - 与mosfet集成的增强型耗尽积累/反转通道器件 - Google Patents

与mosfet集成的增强型耗尽积累/反转通道器件 Download PDF

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CN105702676A
CN105702676A CN201510826873.2A CN201510826873A CN105702676A CN 105702676 A CN105702676 A CN 105702676A CN 201510826873 A CN201510826873 A CN 201510826873A CN 105702676 A CN105702676 A CN 105702676A
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region
trench
type
gate
conduction type
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CN105702676B (zh
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马督儿·博德
雷燮光
哈姆扎·依玛兹
金钟五
伍时谦
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种与MOSFET集成的增强型耗尽积累/反转通道器件，包含：多个栅极沟槽形成在半导体衬底上方的一个第一导电类型的外延区中；一个或多个接触沟槽形成在外延区中，每个接触沟槽都在两个邻近的栅极沟槽之间；一个或多个第一导电类型的源极区形成在接触沟槽和栅极沟槽之间的外延区顶部；势垒金属形成在每个接触沟槽内；每个栅极沟槽都用导电材料基本填满，导电材料与沟槽壁被一层电介质材料隔开，形成栅极；一个导电类型与第一导电类型相反的重掺杂阱区，位于每个接触沟槽底部附近的外延区中。阱区和栅极沟槽之间的水平宽度约为0.05μm至0.2μm。

Description

与MOSFET集成的增强型耗尽积累/反转通道器件
技术领域
本发明涉及一种半导体功率器件，更确切地说是关于与功率MOSFET集成的积累/反转通道FET及其制备方法。
背景技术
半导体器件常用于功率电子电路中的电流切换。例如，开关器件的一种常用形式是功率MOSFET（金属氧化物场效应晶体管）。功率MOSFET用作同步整流器，显著提高了直流-直流降压转换器或同步整流器等应用中的传导损耗。例如，传统的降压转换器拥有一个高端MOSFET作为控制MOSFET，以及一个低端MOSFET作为同步MOSFET。低端MOSFET因其导通时间间隔与体二极管的传导时间同步，可用作同步整流器。通常来说，当低端MOSFET断开时，高端MOSFET接通，反之亦然。在高端MOSFET断开时，随着负载电流从源极流至漏极，低端MOSFET在其第三象限（VDS<0，ID<0）传导电流。
当降压转换器在高速度下工作，高端和低端MOSFET同时接通时，会发生击穿状态，导致击穿电流在输入端和接地端之间流动。击穿状态导致过度的损耗和效率损失。为了避免击穿问题，要在高端MOSFET断开的时间和低端MOSFET接通的时间之间提供死区时间，防止高端和低端MOSFET同时接通。
任何一个带有正常源极-本体短接的高端和低端MOSFET，都含有一个本征体二极管，在其漏极和本体区之间的结处。在死区时间内，感应电流流经较低的MOSFET体二极管，在耗尽区产生存储电荷。必须清除该存储电荷，使体二极管的正向闭锁特性得到恢复。该体二极管通常具有很低的反向恢复性能，会对转换器的效率产生不良影响。因此，需要使用正向偏压很低的二极管。
配有P-N结的功率MOSFET具有很多不良的特性，包括：正向传导损耗很大，在正向偏压下运行时在本体-外延结处存储电荷，当功率MOSFET从正向偏压切换至反向偏压时过量存储的少子电荷会产生很大的恢复电流和电压过冲，在快速切换时产生射频干扰等。以上这些特性会对器件造成不必要的负担，导致次优性能。
在许多应用中，包括功率MOSFET（即带有源极和漏极并联的体二极管的MOSFET）中，已经使用肖特基二极管代替P-N结二极管。肖特基二极管具有多种优于P-N二极管的优良特性，尤其是在功率MOSFET结构中。肖特基二极管在正向传导时具有很低的正向压降，可以降低器件的功率耗散，产生较低的传导损耗。肖特基的传导是通过多数载流子进行的，因此在器件切换时不会发生少子电荷存储效应。所以在功率MOSFET结构中，最好使用肖特基二极管。
随着肖特基二极管在功率MOSFET中的采用逐渐推广，改进器件结构，降低传导损耗也变得日益重要。一个特别重要的考虑因素是减小肖特基二极管所占的半导体衬底表面积。减小肖特基二极管所占的表面积，是降低制造成本，进一步减小电子器件的尺寸和形状，以便获得轻便性及其他功能提高的关键。
因此，必须在功率半导体设计和制造领域中提出在MOSFET器件中集成第三象限传导结构的新型器件结构和制造方法。
正是在这样的背景下，提出了本发明的各个方面。
发明内容
本发明的一个方面在于提出一种新型改良的器件结构和制造方法，用于制备集成的沟槽栅极MOSFET和ACCUFET或耗尽的本体FET，以改善现有技术中的一个或多个问题。
简单地说，本发明的各个方面包括在一个第一导电类型的重掺杂半导体衬底上，结合一个或多个场效应晶体管以及一个ACCUFET或耗尽本体FET的结构。该结构包括多个栅极沟槽，形成在半导体衬底上方的第一导电类型的外延区中。一个或多个接触沟槽形成在外延区中，每个外延区都在两个邻近的栅极沟槽之间。一个或多个第一导电类型的重掺杂源极区，形成在外延层顶部中，每个外延区都在一个相应的接触沟槽和一个相应的栅极沟槽之间。欧姆接触包括一个势垒金属，金属插头形成在每个接触沟槽内。每个栅极沟槽都用导电材料至少部分填充，导电材料与一层电介质材料的沟槽侧壁分隔开，以形成一个或多个场效应晶体管的栅极区。一个与第一导电类型相反的第二导电类型的重掺杂阱区，位于每个接触沟槽底部附近。重掺杂阱区和栅极沟槽之间缝隙的水平宽度约为0.05μm至0.2μm。
在一些实施例中，该结构的特点在于阈值电压的范围约为0.2V至0.4V左右。
在一些实施例中，一个或多个场效应晶体管为分裂栅晶体管。
在一些实施例中，一个第二导电类型的轻掺杂区位于外延区中，以及一个重掺杂阱区和一个栅极沟槽之间。第二导电类型的轻掺杂区的深度延伸到重掺杂阱区的底部附近。
阅读实施例的以下详细说明并参照各种附图，本发明的这些特点和优势对于本领域的技术人员来说，无疑将显而易见。
附图说明
图1A～1C为现有技术中的集成结构的剖面示意图；
图2A表示依据本发明的一个实施例所显示的一种与MOSFET集成的积累型FET的剖面示意图；
图2B表示图2A所示的集成结构正面部分的三维图；
图2C表示图2B所示的一部分集成结构沿A-A’面的剖面图；
图2D表示图2B所示的一部分集成结构沿B-B’面的剖面图；
图2E表示依据本发明的一个实施例所显示的一种与ACCUFET集成的分裂栅晶体管的剖面示意图；
图3A表示依据本发明的一个实施例所显示的一种与MOSFET集成的耗尽通道MOSFET的剖面示意图；
图3B表示图3A所示的集成结构正面部分的三维图；
图3C表示图3B所示的一部分集成结构沿C-C’面的剖面图；
图3D表示图3B所示的一部分集成结构沿D-D’面的剖面图；
图3E表示依据本发明的一个实施例所显示的一种与耗尽本体FET集成的分裂栅晶体管的剖面示意图。
图4A～4D表示依据本发明的一个实施例所显示的一种与ACCUFET或耗尽本体MOSFET集成的功率MOSFET的俯视图。
具体实施方式
以下结合附图，通过详细说明较佳的具体实施例，对本发明做进一步阐述。
引言
存在多种结构，可以将肖特基二极管与MOSFET集成以构成功率MOSFET。然而，这些结果都受到许多不良特性的影响，使它们次于功率MOSFET器件。图1A-1C表示三种现有技术的结构。
图1A表示与多个MOSFET器件集成的原有技术的结构，以及与那些MOSFET器件并联的结型势垒肖特基（JBS）。集成结构100包括一个带有n型外延层103的n+型衬底101。多个MOSFET嵌入在集成结构100中。沟槽105位于外延层103中，并用被绝缘层108包围的导电材料107填充，从而在集成结构100中构成每个MOSFET的每个栅极区107。外延层103包围着每个沟槽的区域，用p-型材料掺杂，构成每个MOSFET的本体区109。在靠近沟槽105的邻近侧壁部分，用n+型导电掺杂物掺杂每个本体区109，构成每个MOSFET器件的源极区111。N+衬底101作为每个MOSFET的漏极区。
结型势垒肖特基（JBS）119也嵌入在集成结构100中。肖特基二极管119包括肖特基势垒金属115，直接形成在n-掺杂区113上方。N-掺杂区113形成在外延层103中，外延层103在两个MOSFET本体区109之间的区域中。肖特基结形成在肖特基势垒金属115和n-掺杂区113之间的交界面处。因此，势垒金属115构成肖特基二极管的阳极，衬底101构成肖特基二极管的阴极。另外，一个或多个p+掺杂屏蔽区117可以形成在n-掺杂区113中，构成P-N结，用于夹断肖特基接头下方的通道区，防止从正向偏压向反向偏压切换时形成很大的反向漏电流。
虽然这种特殊结构的确可以制备带有肖特基二极管的功率MOSFET器件，但是会造成因p+屏蔽引起的低肖特基表面积的缺点。对于击穿电压较大的肖特基二极管来说，通常需要较深的p+结。因此，对于高击穿电压的JBS来说，肖特基表面积的利用率相当低。肖特基二极管的制备需要MOSFET中的专用区域，使晶片面积增大。
图1B表示一种可选的原有技术集成结构，包括一个单片集成的肖特基二极管以及一个高性能的沟槽栅极MOSFET。集成结构201包括多个沟槽200-1、200-2、200-3和200-4，形成图案并在n型衬底202中刻蚀。然后，沿沟槽200的侧壁制备一个薄层电介质204，沉积导电材料206，基本填满每个沟槽200，为集成结构201的每个MOSFET构成一个栅极区。除了要制备肖特基二极管的那些沟槽（例如200-3和200-4）以外，在沟槽200之间，形成一个p-型阱208。P-型阱208为集成结构201的每个MOSFET，构成本体区。然后，在p-型阱区208中，形成N+型源极区212。衬底202构成集成结构201的每个MOSFET的漏极区。在制备P+重本体区214之前或之后，在p-阱区208中形成N+源极区212。可以在衬底的表面上形成图案并沉积一层导电材料216（例如钨化钛（TiW）或氮化钛（TiN）），以便与N+源极区212相接触。
通过在不包含p-型阱的区域中，在衬底202上方沉积肖特基势垒金属218，在集成结构201中形成一个肖特基二极管210。肖特基势垒金属218构成肖特基二极管的阳极，衬底构成肖特基二极管210的阴极。肖特基二极管的两侧被MOSFET沟槽200包围。
由于不需要再在肖特基势垒金属218和衬底202之间制备p-型掺杂区，以避免反向偏压传导时出现很大的反向漏电流，因此该结构解决了肖特基表面积的利用率问题。而且，随着在肖特基二极管的阴极建立起电压，包围着二极管的MOSFET沟槽200-3、200-4构成一个耗尽区，有助于降低反向偏压产生的二极管漏电流。此外，可以调节沟槽200-3和200-4之间的距离W，使每个沟槽周围正在生长的耗尽区在中间重叠，从而夹断肖特基势垒金属218和衬底202之间的漂流区。
虽然，图1B所示的集成结构较好地利用了肖特基表面积，但是也要付出代价，仅仅为了制备肖特基二极管，就要在MOSFET之间分配特定的未掺杂区。这使制备过程包含了额外的处理步骤。此外，该集成结构本质上与JBS二极管具有相同的缺点，就是仍然需要较大尺寸的晶片。
图1C表示另一种集成结构，在每个MOSFET晶胞中含有一个MOSFET和肖特基二极管。集成结构300包括一个带有n型外延层303的n+型衬底301。多个MOSFET嵌入在集成结构300中。在外延层303中制备沟槽305，并用绝缘层303包围的导电材料307填充，以便在集成结构300中形成每个MOSFET的每个栅极区307。包围着每个沟槽的区域用p型材料填充，构成每个MOSFET的本体区309。在沟槽305的邻近侧壁上，每个本体区309都用n+型导电材料311填充，以便形成每个MOSFET器件的源极区311。最终，n+衬底101为每个MOSFET提供一个漏极区。
肖特基二极管319也嵌入在集成结构300的每个晶胞中。接触沟槽316最初形成在每个MOSFET的本体区309中，使接触沟槽316的尖端在本体区309上方延伸到外延区303中。每个接触沟槽316都用肖特基势垒金属315填充，以便在接触沟槽316的尖端和外延区303之间的交界面处形成一个肖特基结。内衬接触沟槽316的肖特基势垒金属315，作为肖特基二极管319的阳极，衬底301作为肖特基二极管319的阴极。另外，一个或多个p+掺杂区317沿接触沟槽316的侧壁，形成在本体区309中，以增强与本体区的接触。
通过消除在MOSFET之间分配指定区域的必要性，以便形成肖特基二极管，在MOSFET有源器件区内（即MOSFET器件的本体区内）集成肖特基二极管，该结构似乎可以修正表面积利用率的问题。
虽然，图1C所示的集成结构有效利用了肖特基表面积，消除了为制备肖特基二极管保留额外的器件区域的必要性，但是它仍然受到许多不良性能的影响。由于肖特基势垒金属必须与n-型材料直接接触，因此，为了正确制备肖特基二极管，在p-型本体区内制备的接触沟槽的深度必须大于本体结的深度。为使每个阱都获得所需深度，必须采取额外的制备工艺（例如补偿掺杂本体区）。该特殊结构复杂的设计体系，使得制备工艺更加复杂、昂贵。遗憾的是，补偿掺杂本体区在制备过程中也不好控制。接触沟槽深度的变化也会影响肖特基的性能。
ACCUFET器件
图2A-2D表示依据本发明的一个方面，一种含有MOSFET器件和第三象限传导器件的集成结构400的不同视图。图2A表示集成结构400的剖面示意图。集成结构400包括一个或多个积累型FET（ACCUFET）器件，可以并联，形成一个功率MOSFET。在第三维度上，还可以包含一个带有ACCUFET的可选择的肖特基二极管。集成结构400嵌入在衬底401中。作为示例，但不作为局限，衬底可以由硅、二氧化硅、氧化铝、蓝宝石、锗、砷化镓（GaAs）、硅或锗的合金、磷化铟（InP）或可以在上面沉积电子器件（例如晶体管、二极管等）的其他任意材料构成。作为示例，但不作为局限，可以重掺杂衬底401，形成n+型衬底。漏极接头430电连接到衬底401，构成每个MOSFET器件的漏极区。
在衬底401上生长一个外延层403。作为示例，但不作为局限，外延层403可以是一个n型层。可以轻掺杂外延层403，以承载较高的器件击穿电压，但是这样会增大器件的内电阻。
在外延层403中制备多个栅极沟槽407。用导电材料411基本填满沟槽407，导电材料411与沟槽壁被一层电介质材料409隔开。填充每个沟槽的导电材料411作为每个MOSFET器件的栅极区。作为示例，但不作为局限，导电材料可以是多晶硅，电介质材料可以是二氧化硅。
在外延层403中制备一个或多个接触沟槽415，每个都在两个邻近的栅极沟槽407之间。另外，在外延层403的顶部，制备导电类型与外延层相同的一对或多对重掺杂源极区413，每个都在接触沟槽415和栅极沟槽407的电介质材料409中间。作为示例，但不作为局限，源极区413可以是N+源极区。此外，导电类型与外延层403不同的重掺杂阱区419可以形成在外延区403中，以及接触沟槽415的底部周围。作为示例，但不作为局限，阱区419可以是p+型阱区。P+阱区419可以通过先垂直注入，然后水平扩散形成。要注意的是，虽然在理论上，p+阱区419的顶部可以一直延伸到N+源极区413的底部，但是p+注入的处理限制使得这样无法实现。由于源极区413和P+阱区419的重掺杂水平（例如在1e19cm-3范围内），利用标准的势垒金属，可以形成它们的欧姆接触。
作为示例，但不作为局限，势垒金属417可以是钛（Ti）或氮化钛（TiN）。除了势垒金属以外，接触沟槽415可以用金属插头418填充。作为示例，但不作为局限，金属插头可以由钨（W）制成。
源极金属422穿过接触沟槽415，触及p+阱区419。作为示例，但不作为局限，源极金属可以是Al或Cu或其他合适的金属。
虽然希望阈值电压越低越好，但是低阈值电压Vth会导致较高的漏电流。因此，降低阈值电压的极限，就是当器件断开时，器件可以承受的漏电流。由于阱区419和栅极沟槽407之间的通道被栅极411以及附近的阱区419完全耗尽，因此可以通过在栅极氧化物409和阱区419之间设计一个缝隙g，形成势垒，防止器件断开时产生从漏极到源极的漏电流。也就是说，为了获得较低的阈值电压Vth，栅极沟槽407中的栅极氧化物409和阱区419之间的缝隙g必须很小。在一些实施例中，栅极沟槽407和阱区419之间的缝隙g的水平宽度约为0.05μm至0.2μm左右。ACCUFET或耗尽本体MOSFET的长度大约在0.1μm至0.35μm的范围内。
带有低Vth的ACCUFET400的关键参数是N-通道的长度，这由阱区419的垂直厚度、栅极氧化物409和阱区419之间的缝隙g的水平宽度所决定，与栅极氧化物409和接触沟槽415之间的缝隙到阱区的宽度w、作为N-通道的缝隙g中外延区403的掺杂有关。通过调节这些参数，可以设计阈值电压Vth，使其低至0.2V至0.4V左右。
依据本发明所述的一种器件可以比带有肖特基二极管的传统器件接通和传导更多次。尤其是，它允许第三象限上两种传导模式。正源极偏压可以在低偏压（0.3V）下打开通道，允许第三象限传导。栅极所加的正偏压可以利用极低的Rds,on，进行MOSFET型传导。
图2B表示不含源极金属422层、势垒金属417以及金属插头418的集成结构400正面的三维视图。如图所示，阱区419靠近栅极沟槽407中的栅极氧化物409，形成势垒，避免器件断开时产生从漏极到源极的漏电流。
图2C表示集成结构400的ACCUFET沿A-A’面的剖面图。图2D表示带有所示势垒金属417的集成结构400的结FET（JFET）沿B-B’面的剖面图。如图所示，肖特基二极管垂直形成在势垒金属417和外延层403之间的交界面处。
图2E表示依据本发明的另一方面，结合了分裂栅晶体管和ACCUFET的集成结构400A的剖面图。结构400A中除了栅极沟槽包括一个在底部的屏蔽栅极电极412以及一个在顶部的栅极电极411之外，其他都与结构400类似。要注意的是，屏蔽电极412增加了控制从漏极到源极泄露的额外优势。
集成耗尽本体FET的MOSFET器件，用于第三象限传导
图3A-3D表示依据本发明的一个方面，含有MOSFET器件和耗尽本体MOSFET的集成结构500的不同视图。要注意的是，对于“耗尽本体MOSFET”、“耗尽本体FET”、“耗尽通道MOSFET”以及“耗尽通道FET”等术语，指示相同结构时本领域的技术人员可互换使用。图3A表示集成结构500的剖面示意图。集成结构500包括一个或多个耗尽通道FET器件，这些器件可以并联，形成一个功率MOSFET。在第三维度上，还可以包含带有耗尽本体FET和MOSFET的可选择的肖特基二极管。
结构500中除了一个导电类型与外延层相反的轻掺杂区425，在源极区413和外延区403之间，以及栅极沟槽407和阱区419之间，其他都与图2A所示的结构400类似。作为示例，但不作为局限，轻掺杂区425可以是一个P型区。
除了上述参数值为，结合了耗尽通道MOSFET、阈值电压很低的集成结构500的关键参数，包括轻掺杂区425的掺杂，可以在1e16cm-3至1e17cm-3范围内。P+阱419的掺杂浓度可以在5e18cm-3至1e19cm-3范围内。
图3B表示不含源极区413和金属插头418的集成结构500的肖特基部分的三维图。另外，图3B表示，在势垒金属417下方，有一个台面结构440形成在两个栅极沟槽在降低半导体外延层403中，栅极沟槽中没有掺杂阱区419。根据图例，两种不同类型的肖特基二极管可以由势垒金属垂直构成。确切地说，如图3C所示，沟槽MOS势垒肖特基（TMBS）垂直形成在台面结构440处。在TMBS中，台面结构440中多数电荷载流子和栅极沟槽侧壁上的导体之间的电荷耦合，改变了肖特基接头下方的电场形状，降低了反向漏电流，提高了击穿属性。此外，如图3D所示，结型势垒肖特基（JBS）在轻掺杂区425和接触沟槽415之间，垂直形成到台面结构440。
图3E表示依据本发明的另一方面，结合了分裂栅晶体管和肖特基二极管的集成结构500A的剖面图。结构500A中除了栅极沟槽包括一个在底部的栅极电极412以及一个在顶部的栅极电极411之外，其他都与结构500类似。
有多种可能的方式，将ACCUFET或耗尽本体MOSFET二极管与功率MOSFET器件集成。作为示例，但不作为局限，图4A-4D表示依据本发明的各个方面，功率MOSFET的俯视平面图。阱区419位于栅极区411之间。除了区域450之外，大多数的区域都是带有p-本体440的正规MOSFET区。依据本发明的一个方面，区域450是不含p-本体440的区域，以制备ACCUFET。为了缩小阱区419和栅极氧化物409之间的缝隙，可以如图4C所示调节沟槽布局，使其在制备ACCUFET的区域450处较宽，或者如图4D所示调节接触布局。
尽管本发明依据现有的较佳实施例进行了详细说明，但应明确本说明并不用于局限。例如，虽然上述说明是指n-通道器件，但是通过转换掺杂区的导电类型，就可将本发明用于p-通道器件。阅读上述说明后，本发明的各种可选和修正方案对于本领域的技术人员无疑将显而易见。因此，应由所附的权利要求书及其全部等效内容决定本发明的真实意图及范围。

Claims (14)

1.一种器件结构，其特征在于，包括：
多个栅极沟槽，形成在第一导电类型的半导体衬底上方的第一导电类型的外延区中，每个栅极沟槽都用导电材料至少部分填满，导电材料与沟槽壁被一层电介质材料隔开，构成一个栅极；
一个或多个接触沟槽，形成在外延区中，每个接触沟槽都位于两个邻近的栅极沟槽之间，其中一个与第一导电类型相反的第二导电类型的重掺杂阱区位于所述的一个或多个接触沟槽的底部附近，重掺杂阱区和栅极沟槽之间缝隙的水平宽度为0.05μm至0.2μm之间；以及
一个或多个第一导电类型的重掺杂源极区，形成在外延区顶部，每个重掺杂源极区都在一个相应的接触沟槽和一个相应的栅极沟槽之间；以及
一个势垒金属，形成在没有重掺杂源极区的那部分外延区中的台面结构上方，其中台面结构形成在两个接触沟槽和两个第二导电类型的轻掺杂区之间。
2.根据权利要求1所述的器件结构，其特征在于，其中一个或多个场效应晶体管为分裂栅晶体管，其中每个栅极沟槽都有一个栅极区，在栅极沟槽顶部，以及一个屏蔽栅极区，在栅极沟槽底部。
3.根据权利要求1所述的器件结构，其特征在于，其中第一导电类型为N-型，第二导电类型为P-型。
4.根据权利要求1所述的器件结构，其特征在于，其中第一导电类型为P-型，第二导电类型为N-型。
5.根据权利要求1所述的器件结构，其特征在于，其中一个或多个第二导电类型的轻掺杂区都位于外延区中，其中一个或多个第二导电类型的轻掺杂区包括一个特殊区域，形成在一个重掺杂阱区和一个栅极沟槽之间，其中该特殊区域还延伸到重掺杂阱区底部和附近的一个接触沟槽底部之间的深度。
6.根据权利要求1所述的器件结构，其特征在于，其中该结构的阈值电压在0.2V至0.4V的范围内。
7.根据权利要求1所述的器件结构，其特征在于，其中外延区的掺杂浓度为1e16cm-3至5e16cm-3之间。
8.根据权利要求4所述的器件结构，其特征在于，其中第二导电类型的轻掺杂区的掺杂浓度在5e16cm-3至1e17cm-3之间。
9.根据权利要求1所述的器件结构，其特征在于，其中通过加宽部分栅极沟槽，可以调节重掺杂阱区和栅极沟槽之间缝隙的水平宽度。
10.一种方法，其特征在于，包括：
在第一导电类型的半导体衬底上方的第一导电类型的外延区中，制备多个栅极沟槽；
用导电材料至少部分填满每个沟槽，导电材料与沟槽壁被一层电介质材料隔开，形成一个栅极；
在外延区中，制备一个或多个接触沟槽，每个接触沟槽位于两个邻近的栅极沟槽之间；
在所述的一个或多个接触沟槽底部附近的外延区中，制备与第一导电类型相反的第二导电类型的重掺杂阱区，其中重掺杂阱区和栅极沟槽之间的水平宽度约为0.05μm至0.2微米左右；
在外延区顶部，制备一个或多个第一导电类型的重掺杂源极区，每个重掺杂源极区都在一个相应的接触沟槽和一个相应的栅极沟槽之间；并且
在不含重掺杂源极区的那部分外延区中的台面结构上方，制备一个势垒金属，其中台面结构形成在两个接触沟槽和两个第二导电类型的轻掺杂区之间。
11.根据权利要求10所述的方法，其特征在于，其中一个或多个场效应晶体管为分裂栅晶体管，其中每个栅极沟槽都有一个栅极区，在栅极沟槽顶部，以及一个屏蔽栅极区，在栅极沟槽底部。
12.根据权利要求11所述的方法，其特征在于，其中第一导电类型为N-型，第二导电类型为P-型。
13.根据权利要求10所述的方法，其特征在于，其中第一导电类型为P-型，第二导电类型为N-型。
14.根据权利要求10所述的方法，其特征在于，还包括在外延区中，制备一个或多个第二导电类型的轻掺杂区，其中一个或多个第二导电类型的轻掺杂区包括一个特殊区域，形成在一个重掺杂阱区和一个栅极沟槽之间，其中特殊区域延伸到重掺杂阱区的底部和附近的一个接触沟槽底部之间的深处。
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