CN107546268B - 半导体器件及制造其的方法 - Google Patents

半导体器件及制造其的方法 Download PDF

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CN107546268B
CN107546268B CN201611077777.3A CN201611077777A CN107546268B CN 107546268 B CN107546268 B CN 107546268B CN 201611077777 A CN201611077777 A CN 201611077777A CN 107546268 B CN107546268 B CN 107546268B
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CN107546268A (zh
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千大焕
郑永均
李钟锡
金英俊
金台曅
禹赫
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Hyundai Motor Co
Hyundai Mobis Co Ltd
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Abstract

本发明提供一种半导体器件，包括：n‑型层，其设置在n+型碳化硅衬底的第一表面上；第一沟槽，其在n‑型层中形成；p型区域，其设置在第一沟槽的两个侧表面上；n+型区域，其设置在第一沟槽的两个侧表面上，并且设置在n‑型层和p型区域上；栅极绝缘层，其设置在第一沟槽内侧；栅电极，其设置在栅极绝缘层上；氧化物层，其设置在栅电极上；源电极，其设置在氧化物层和n+区域上；以及漏电极，其设置在n+型碳化硅衬底的第二表面上，其中作为累积层沟道的第一沟道和作为反型层沟道的第二沟道设置在第一沟槽的两个侧表面中，并且第一沟道和第二沟道被设置成在n+型碳化硅衬底的第一表面的水平方向上相邻。

Description

半导体器件及制造其的方法
技术领域
本公开涉及包括碳化硅(SiC)的半导体器件及制造其的方法。
背景技术
随着近来大型和大容量应用装置的趋势，具有高击穿电压、高电流容量和高速开关特性的功率半导体器件已经变得必要。
这种功率半导体器件应当具有低导通电阻或低饱和电压，以便当非常大的电流流过时，降低导电状态下的功率损耗。此外，功率半导体器件应当能够承受在关闭状态下或者在开关关闭的时刻施加到功率半导体器件的两个端部的PN接合处的反向高电压，即，高击穿电压特性。
在功率半导体器件中，金属氧化物半导体场效应晶体管(MOSFET)最常用作数字电路和模拟电路中的场效应晶体管。
使用碳化硅(SiC)的MOSFET可降低导通电阻以降低功率消耗，但是沟道的电子迁移率可较低，使得可存在高沟道电阻。已经开发了应用具有累积沟道的沟槽栅极的碳化硅MOSFET，以减轻这种情况。
背景技术部分中公开的上述信息仅仅是为了增强对本公开的背景的理解，因此其可包含不构成该国家本领域普通技术人员已知的现有技术的信息。
发明内容
本公开降低了应用具有累积层沟道的沟槽栅极的碳化硅MOSFET中的半导体器件的工艺的难度。
根据本公开的示例性实施例，一种半导体器件包括：n-型层，其设置在n+型碳化硅衬底的第一表面上；第一沟槽，其在n-型层中形成；p型区域，其设置在第一沟槽的两个侧表面上；n+型区域，其设置在第一沟槽的两个侧表面上，并且设置在n-型层和p型区域上；栅极绝缘层，其设置在第一沟槽内侧；栅电极，其设置在栅极绝缘层上；氧化物层，其设置在栅电极上；源电极，其设置在氧化物层和n+区域上；以及漏电极，其设置在n+型碳化硅衬底的第二表面上，其中作为累积层沟道的第一沟道和作为反型层沟道的第二沟道设置在第一沟槽的两个侧表面中，并且第一沟道和第二沟道被设置成在n+型碳化硅衬底的第一表面的水平方向上相邻。
n-型层可包括接触n+型区域和第一沟槽的侧表面的第一部分。
第一沟道可设置在第一部分处。
p型区域可包括接触n+型区域和第一沟槽的侧表面的第二部分。
第二沟道可设置在第二部分处。
半导体器件可还包括第二沟槽，其设置在p型区域处，并且与第一沟槽分离。
n+型碳化硅衬底的第一表面和第二沟槽的下表面之间的间隔可比n+型碳化硅衬底的第一表面和第一沟槽的下表面之间的间隔长。
p型区域和n-型层彼此接触，并且p型区域和n-型层的接触表面具有台阶形状。
根据本公开中的另一个示例性实施例，一种半导体器件的制造方法包括以下步骤：在n+型碳化硅衬底的第一表面上形成n-型层；在n-型层上形成n+区域；向n+区域注入p型离子，以在n+区域下面形成p型区域；蚀刻n+区域、p型区域和n-型层，以形成第一沟槽；在第一沟槽中形成栅极绝缘层；在栅极绝缘层上形成栅电极；在栅电极上形成氧化物层；在氧化物层和n+区域上形成源电极；以及在n+型碳化硅衬底的第二表面处形成漏电极。作为累积层沟道的第一沟道和作为反型层沟道的第二沟道在第一沟槽的两个侧表面中形成，第一沟道和第二沟道被形成为在n+型碳化硅衬底的第一表面的水平方向上相邻。
在形成p型区域的步骤中，通过使用掩模阻挡可形成第一沟道的部分，并且注入p型离子。
形成第一沟槽的步骤可包括蚀刻n+型区域和p型区域，以形成第二沟槽，以及第一沟槽和第二沟槽可彼此分离。
半导体器件的制造方法可还包括在垂直于第二沟槽的下表面的方向上在第二沟槽的下表面中注入p型离子，以扩展p型区域。
如上所述，根据本公开中的示例性实施例，通过使用掩模来控制累积层的沟道区域的范围，可在容许的误差范围内容易地形成累积层沟道。因此，可提高半导体器件的产率。
另外，通过在垂直于位于p型区域处的第二沟槽的下表面的方向注入p型离子以形成p型区域，可减小第二沟槽的宽度和深度。因此，通过增加半导体器件的沟道密度可减小电阻。
附图说明
图1是示意性地示出根据本公开的示例性实施例的半导体器件的透视图。
图2是示出沿图1的线A-A的截取的横截面的一个示例的视图。
图3是示出沿图1的线B-B的截取的横截面的一个示例的视图。
图4至图8B是示出根据本公开中的示例性实施例的半导体器件的制造方法的视图。
具体实施方式
将参考附图描述本公开中的示例性实施例。本公开可以许多不同的形式进行修改，并且不应被解释为限于本文所阐述的示例性实施例。相反，提供本公开中的示例性实施例，使得本公开将是彻底和完整的，并且将向本领域技术人员充分传达本发明的概念。
在附图中，为了清楚起见，可放大层和区域的厚度。此外，当层被描述要在另一个层上或衬底上形成时，这意味着该层可在另一个层上或衬底上形成，或者第三层可插置在层和另一个层或衬底之间。
图1是示意性地示出根据本公开的示例性实施例的半导体器件的一个示例的透视图。图2是示出沿图1的线A-A的截取的横截面的一个示例的视图。图3是示出沿图1的线B-B的截取的横截面的一个示例的视图。
参考图1至图3，根据本示例性实施例的半导体器件包括n+型碳化硅衬底100、n-型层200、p型区域400、n+型区域300、栅电极600、源电极700和漏电极800。
n-型层200设置在n+型碳化硅衬底100的第一表面上，并且第一沟槽210设置在n-型层200上。
p型区域400设置在第一沟槽210的两个侧表面上，第二沟槽410设置在p型氧化物层域400上。p型氧化物层域400设置在n-型层200上，并且p型氧化物层域400和n-型层200接触的表面具有台阶形状。n+型碳化硅衬底的第一表面100和第二沟槽410的下表面之间的间隔比n+型碳化硅衬底100的第一表面和第一沟槽210的下表面之间的间隔长。
n+型氧化物层域300设置在n-型层200和p型氧化物层域400上。
n-型层200的一部分接触n+型氧化物层域300，并且同时接触第一沟槽210的侧表面。在这种情况下，n-型层200的一部分设置在第一沟槽210的侧表面和p型氧化物层域400之间(参见图2)。
p型氧化物层域400的一部分接触n+型氧化物层域300，并且同时接触第一沟槽210的侧表面(参见图3)。
栅极绝缘层510设置在第一沟槽210中，并且栅电极600设置在栅极绝缘层510上。栅电极600可填充第一沟槽210的内部，并且可突出到第一沟槽210的上侧。栅电极600可包括多晶硅或金属。
氧化物层520设置在栅电极600上。氧化物层520覆盖从第一沟槽210突出的栅电极600的侧表面。
源电极700设置在n+型氧化物层域300上，氧化物层520上，以及第二沟槽410内侧。
漏电极800设置在n+型碳化硅衬底100的第二表面上。在这里，n+型碳化硅衬底100的第二表面指示与n+型碳化硅衬底100的第一表面相对的表面。源电极700和漏电极800可包括金属。在这种情况下，金属可以是欧姆金属。
在图1中，为了清楚地解释根据本示例性实施例的半导体器件的结构，省略了n+型氧化物层域300、氧化物层520和源电极700。
根据本示例性实施例的半导体器件的沟道包括第一沟道250和第二沟道450。第一沟道250和第二沟道450设置在第一沟槽210的两个侧表面上。
第一沟道250设置在接触n+型氧化物层域300，并同时接触第一沟槽210的侧表面的n-型层200中，并且是累积层沟道。第二沟道450设置在接触n+型氧化物层域300，并同时接触第一沟槽210的侧表面的p型氧化物层域400中，并且是反型层沟道。在这里，第一沟道250和第二沟道450被定位成相对于n+型碳化硅衬底100的第一表面在水平方向上是相邻的。
如果电压被施加到栅电极600，则电子和电流通过沟道从源电极700流动到漏电极800。在这种情况下，由于沟道包括作为积累层沟道的第一沟道250，电子和电流被扩散，使得可提高电子和电流的迁移率。因此，可减小半导体器件的导通电阻。
接下来，将参照图4至图8B以及图2和图3详细地描述根据本公开中的示例性实施例的半导体器件的制造方法。
图4至图8B是示出根据本公开中的示例性实施例的半导体器件的制造方法的示例的视图。图5A，6A，7A和8A示出沿图1的线A-A截取的横截面的制造方法的示例，并且图5B，6B，7B和8B示出沿图1的线B-B截取的横截面的制造方法的示例。
参考图4，制备n+型碳化硅衬底100，n-型层200在n+型碳化硅衬底100的第一表面上形成，然后n+型氧化物层域300在n-型层200上形成。通过外延生长或n-离子注入可形成n-型层200。通过外延生长或n-离子注入也可形成n+型氧化物层域300。
参考图5A和图5B，将p型离子注入到n+型氧化物层域300的表面，以形成p型氧化物层域400。p型离子从n+型氧化物层域300扩散到n-型层200，使得p型氧化物层域400在n+型氧化物层域300下面形成。
当注入p型离子时，通过使用掩模来阻挡形成所述积累层沟道的第一沟道250的部分的n-型层200，将p型离子垂直注入到n+型区域300的表面。因此，如图5A中所示，p型区域400的部分被间隔N分开。
当累积沟道区域在大于预定的容许误差范围形成时，其引起漏电流，并且在本示例性实施例中，由于通过使用掩模可控制形成作为积累层沟道的第一沟道250的部分的n-型层200的范围，所以在容许误差范围内可容易地形成作为积累层沟道的第一沟道250。因此，可提高半导体器件的产率。
参考图6A和图6B，蚀刻n+型区域300、p型区域400和n-型层200，以形成第一沟槽210，并且蚀刻n+型区域300和p型区域400，以形成第二沟槽410。第一沟槽210和第二沟槽410彼此分离，并且其深度可不同地形成。n+型碳化硅衬底的第一表面100和第二沟槽410的下表面之间的间隔比n+型碳化硅衬底100的第一表面和第一沟槽210的下表面之间的间隔长。
参考图7A和图7B，在第二沟槽410的下表面中注入p型离子，以形成p型区域400。在这种情况下，p型离子相对于第二沟槽410的下表面被垂直地注入，并且扩散到n-型层200中，并且如果p型区域400和n-型层200接触，则表面具有台阶形状。
如上所述，在注入p型离子以形成p型区域400(参见图5A和5B)之后，形成第二沟槽410，然后在垂直于第二沟槽410的下表面的方向上在第二沟槽410的下表面中注入p型离子，以延伸p型区域400，使得可减小第二沟槽410的宽度和深度。因此，增加半导体器件的沟道密度，从而减小电阻。
参考图8A和图8B，栅极绝缘层510在第一沟槽210中形成，并且栅电极600在栅极绝缘层510上形成。栅电极600填充第一沟槽210的内部，并且可突出到第一沟槽210的上侧。栅电极600可由多晶硅或金属形成。
参考图2和图3，在栅电极600上形成氧化物层520之后，源电极700在n+型区域300和氧化物层520上，以及第二沟槽410内部形成，并且漏电极800在n+型碳化硅衬底100的第二表面上形成。在这里，源电极700和漏电极800可由金属形成。在这种情况下，金属可以是欧姆金属。
虽然已经结合目前认为是实用的示例性实施例描述了本发明，但是应当理解，本发明不限于所公开的实施例，而是相反，其旨在覆盖包括在随附权利要求的精神和范围内的各种修改和等同布置。

Claims (16)

1.一种半导体器件，其包括：
n-型层，其设置在n+型碳化硅衬底的第一表面上；
第一沟槽，其在所述n-型层中形成；
p型区域，其设置在所述第一沟槽的两个侧表面上；
n+型区域，其设置在所述第一沟槽的两个侧表面上，并且设置在所述n-型层和所述p型区域上；
栅极绝缘层，其设置在所述第一沟槽内侧；
栅电极，其设置在所述栅极绝缘层上；
氧化物层，其设置在所述栅电极上；
源电极，其设置在所述氧化物层和所述n+型区域上；以及
漏电极，其设置在所述n+型碳化硅衬底的第二表面上，
其中作为累积层沟道的第一沟道和作为反型层沟道的第二沟道设置在所述第一沟槽的两个侧表面中，并且
所述第一沟道和所述第二沟道被设置成在所述n+型碳化硅衬底的所述第一表面的水平方向上相邻，
所述p型区域包括与所述n+型区域和所述第一沟槽的侧表面接触的多个第二部分和与所述n+型区域接触但不与所述第一沟槽的侧表面接触的多个第三部分，以及
所述多个第二部分和所述多个第三部分沿所述第一沟槽依次交替排列。
2.根据权利要求1所述的半导体器件，其中
所述n-型层包括接触所述n+型区域和所述第一沟槽的所述侧表面的第一部分。
3.根据权利要求2所述的半导体器件，其中
所述第一沟道设置在所述第一部分中。
4.根据权利要求1所述的半导体器件，其中
所述第二沟道设置在所述第二部分处。
5.根据权利要求4所述的半导体器件，其还包括：
第二沟槽，其设置在所述p型区域处，并且与所述第一沟槽分离。
6.根据权利要求5所述的半导体器件，其中
n+型碳化硅衬底的所述第一表面和所述第二沟槽的下表面之间的间隔比所述n+型碳化硅衬底的所述第一表面和所述第一沟槽的下表面之间的间隔长。
7.根据权利要求6所述的半导体器件，其中
所述p型区域和所述n-型层彼此接触，并且
所述p型区域和所述n-型层的接触表面具有台阶形状。
8.一种用于制造半导体器件的方法，其包括以下步骤：
在n+型碳化硅衬底的第一表面上形成n-型层；
在所述n-型层上形成n+型区域；
向所述n+型区域注入p型离子，以在所述n+型区域下面形成p型区域；
蚀刻所述n+型区域、所述p型区域和所述n-型层，以形成第一沟槽；
在所述第一沟槽中形成栅极绝缘层；
在所述栅极绝缘层上形成栅电极；
在所述栅电极上形成氧化物层；
在所述氧化物层和所述n+型区域上形成源电极；以及
在所述n+型碳化硅衬底的第二表面上形成漏电极，
其中作为累积层沟道的第一沟道和作为反型层沟道的第二沟道在所述第一沟槽的两个侧表面中形成，并且
所述第一沟道和所述第二沟道被形成为在所述n+型碳化硅衬底的所述第一表面的水平方向上相邻，
所述p型区域包括与所述n+型区域和所述第一沟槽的侧表面接触的多个第二部分和与所述n+型区域接触但不与所述第一沟槽的侧表面接触的多个第三部分，以及
所述多个第二部分和所述多个第三部分沿所述第一沟槽依次交替排列。
9.根据权利要求8所述的方法，其中
在形成所述p型区域的步骤中，
通过使用掩模来阻挡形成所述第一沟道的部分，并且注入所述p型离子。
10.根据权利要求9所述的方法，其中
所述n-型层包括接触所述n+型区域和所述第一沟槽的所述侧表面的第一部分。
11.根据权利要求10所述的方法，其中
所述第一沟道在所述第一部分中形成。
12.根据权利要求8所述的方法，其中
所述第二沟道在所述第二部分中形成。
13.根据权利要求12所述的方法，其中
形成所述第一沟槽的步骤包括
蚀刻所述n+型区域和所述p型区域，以形成第二沟槽，以及
所述第一沟槽和所述第二沟槽彼此分离。
14.根据权利要求13所述的方法，其中
n+型碳化硅衬底的所述第一表面和所述第二沟槽的下表面之间的间隔比所述n+型碳化硅衬底的所述第一表面和所述第一沟槽的所述下表面之间的间隔长。
15.根据权利要求14所述的方法，其还包括以下步骤：
在垂直于所述第二沟槽的所述下表面的方向上在所述第二沟槽的所述下表面中注入所述p型离子，以扩展所述p型区域。
16.根据权利要求15所述的方法，其中
所述p型区域和所述n-型层彼此接触，并且
所述p型区域和所述n-型层的接触表面具有台阶形状。
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