CN111192917B - 一种横向场效应晶体管 - Google Patents

一种横向场效应晶体管 Download PDF

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CN111192917B
CN111192917B CN201911182510.4A CN201911182510A CN111192917B CN 111192917 B CN111192917 B CN 111192917B CN 201911182510 A CN201911182510 A CN 201911182510A CN 111192917 B CN111192917 B CN 111192917B
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field effect
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schottky barrier
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CN111192917A (zh
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陶宏
傅达平
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本公开的实施例揭露了一种横向场效应晶体管。该横向场效应晶体管包括半导体层、阱区、体区、源区、漏区、栅结构以及沟槽型肖特基势垒结构。该沟槽型肖特基势垒结构由该阱区的上表面开始纵向延伸穿过所述源区、所述体区以及所述阱区的至少一部分使该沟槽型肖特基势垒结构的侧壁与该阱区之间形成纵向肖特基接触。该纵向肖特基接触可以基于制作该横向场效应晶体管的工艺步骤与该横向场效应晶体管同时制作,并且可以大幅缩减集成有肖特基二极管的横向场效应晶体管的横向尺寸,以更好地满足集成电路应用需要其尺寸和体积越来越小的同时具备良好的反向泄漏/反向衬底注入抑制能力的需求。

Description

一种横向场效应晶体管
技术领域
本发明的实施例涉及半导体器件,尤其涉及横向场效应晶体管。
背景技术
横向晶体管,尤其横向双扩散金属氧化物半导体场效应晶体管(LDMOS)广泛应用于各种集成电源管理电路中。然而传统的横向场效应晶体管(例如LDMOS)其本身的体二极管存在反向恢复现象会导致LDMOS作为开关器件工作时(尤其工作于较高开关频率时)功耗增大。因而,当前集成电路应用需要横向场效应晶体管的尺寸和体积越来越小的同时具备良好的反向泄漏/反向衬底注入抑制能力和较低的开关损耗。
发明内容
本公开的实施例提供一种横向场效应晶体管。该横向场效应晶体管可以包括半导体层,具有第一导电类型;阱区,形成于所述半导体层之中或之上,具有与该第一导电类型相反的第二导电类型;体区,形成于所述阱区中,具有所述的第一导电类型;源区,位于所述体区中,具有所述的第二导电类型;漏区,位于所述阱区中,与所述体区分离,具有所述的第二导电类型;栅结构,形成于所述阱区的靠近所述源区一侧的部分之上;以及沟槽型肖特基势垒结构,由所述阱区的上表面开始纵向延伸穿过所述源区、所述体区以及所述阱区的至少一部分使该沟槽型肖特基势垒结构的侧壁与该阱区之间形成纵向肖特基接触。
根据本公开的一个实施例,该沟槽型肖特基势垒结构具有预设的纵向沟槽深度,通过调节其预设的纵向沟槽深度可以调节所述肖特基接触的面积。
根据本公开的一个实施例,所述第二栅区进一步包括导电性场板,制作于该浅沟槽隔离结构中,至少部分纵向延伸进所述浅沟槽隔离结构内部。
根据本公开的一个实施例,该沟槽型肖特基势垒结构可以纵向延伸直至与所述半导体层接触或延伸入所述半导体层的一部分之中。
根据本公开的一个实施例,该横向场效应晶体管可以进一步包括体接触区,位于所述体区中,并且横向分布在所述源区与所述沟槽型肖特基势垒结构之间,该体接触区具有所述第一导电类型,并且具有体接触区掺杂浓度,该体接触区掺杂浓度高于所述体区的掺杂浓度。
根据本公开的一个实施例,该横向场效应晶体管可以进一步包括保护环区,具有所述第一导电类型,形成于所述沟槽型肖特基势垒结构的底部周围,包络该沟槽型肖特基势垒结构的底部区域以使该保护环区与该沟槽型肖特基势垒结构的底部区域之间形成欧姆接触。
根据本公开的一个实施例,该保护环区具有保护环区掺杂浓度,该保护环区掺杂浓度大于所述半导体层的掺杂浓度。
根据本公开的一个实施例,该横向场效应晶体管可以进一步包括掩埋层,制作于所述半导体层中,位于所述阱区的下方,所述保护环区与所述掩埋层接触或至少部分地被所述掩埋层包络。
根据本公开的一个实施例,该横向场效应晶体管可以选择性地包括所述掩埋层但不包括所述保护环区,则所述掩埋层制作于所述半导体层中,位于所述阱区的下方,包络所述沟槽型肖特基势垒结构的底部区域并与所述沟槽型肖特基势垒结构的底部及一部分侧壁接触。
根据本公开的一个实施例,该横向场效应晶体管的所述体接触区,可以选择性地不横向分布在所述源区与所述沟槽型肖特基势垒结构之间,而是在与所述横向和所述纵向均垂直的第三方向上与所述源区交替排布,并且与所述源区和所述沟槽型肖特基势垒结构均接触。
根据本公开的一个实施例,该横向场效应晶体管的所述体接触区,可以选择性地不横向分布在所述源区与所述沟槽型肖特基势垒结构之间,也不在所述第三方向上与所述源区交替排布,而是纵向位于所述源区的下方,并且与所述源区和所述沟槽型肖特基势垒结构均接触。
根据本公开的一个实施例,该横向场效应晶体管的所述沟槽型肖特基势垒结构包括第一槽型部分和第二槽型部分,其中该第一槽型部分具有第一沟槽深度,该第一沟槽深度大于所述源区的源区深度并且小于所述体区的体区深度。该第一槽型部分具有第一沟槽宽度,该第二槽型部分具有第二沟槽宽度,该第二沟槽宽度小于所述第一沟槽宽度。该第二槽型部分具有第二沟槽深度,该第二沟槽深度决定所述纵向肖特基接触的深度。
根据本公开各实施例的横向场效应晶体管,通过制作所述沟槽型肖特基势垒结构将肖特基二极管与该横向场效应晶体管集成,并可以基于制作该横向场效应晶体管的工艺步骤将肖特基二极管与该横向场效应晶体管同时制作。由于该沟槽型肖特基势垒结构纵向延伸进入所述阱区与该阱区形成纵向肖特基接触,因而肖特基二极管的肖特基接触面积主要取决于该沟槽型肖特基势垒结构的预设纵向沟槽深度,则该沟槽型肖特基势垒结构的横向尺寸(宽度)可以最低缩减至工艺所允许制作的沟槽最小横向尺寸,可以大幅缩减集成有肖特基二极管的横向场效应晶体管的横向尺寸,这在当前集成电路应用中具有非常大的优势,能够更好地满足当今集成电路应用需要其尺寸和体积越来越小的同时具备良好的反向泄漏/反向衬底注入抑制能力的需求。
附图说明
下面的附图有助于更好地理解接下来对本发明不同实施例的描述。这些附图并非按照实际的特征、尺寸及比例绘制,而是示意性地示出了本发明一些实施方式的主要特征。这些附图和实施方式以非限制性、非穷举性的方式提供了本发明的一些实施例。为简明起见,不同附图中具有相同功能的相同或类似的组件或结构采用相同的附图标记。
图1示出了根据本公开一个实施例的横向场效应晶体管100的纵向剖面示意图;
图2示出了根据本公开又一个实施例的横向场效应晶体管100的纵向剖面示意图;
图3示出了根据本公开又一个实施例的横向场效应晶体管100的纵向剖面示意图;
图4示出了根据本公开又一个实施例的横向场效应晶体管100的纵向剖面示意图;
图5示出了根据本公开再一个实施例的横向场效应晶体管100的纵向剖面示意图;
图6A和图6B示出了根据本公开一个变型实施例的横向场效应晶体管100的纵向剖面示意图;
图7示出了根据本公开又一个变型实施例的横向场效应晶体管100的纵向剖面示意图;
图8示出了根据本公开再一个变型实施例的横向场效应晶体管100的纵向剖面示意图。
具体实施方式
下面将详细说明本发明的一些实施例。在接下来的说明中,一些具体的细节,例如实施例中的具体电路结构和这些电路元件的具体参数,都用于对本发明的实施例提供更好的理解。本技术领域的技术人员可以理解,即使在缺少一些细节或者其他方法、元件、材料等结合的情况下,本发明的实施例也可以被实现。
在本发明的说明书及权利要求书中,若采用了诸如“左、右、内、外、前、后、上、下、顶、之上、底、之下”等一类的词,均只是为了便于描述,而不表示组件/结构的必然或永久的相对位置。本领域的技术人员应该理解这类词在合适的情况下是可以互换的,例如,以使得本发明的实施例可以在不同于本说明书描绘的方向下仍可以运作。此外,“耦接”一词意味着以直接或者间接的电气的或者非电气的方式连接。
图1示出了根据本公开一个实施例的横向场效应晶体管100的部分纵向剖面示意图。该纵向剖面示意图在由相互垂直的x轴、y轴和z轴定义的三维坐标系中示出,可以理解为由平行于x轴和y轴定义的切面对该横向场效应晶体管100的一部分进行剖割所得的剖面示意图。本公开中,除另有特别说明外,“横向”均指平行于x轴的方向,“宽度”均指平行于x轴方向上的尺寸;“纵向”指平行于y轴的方向,“深度”或“厚度”指平行于y轴方向上的尺寸。该横向场效应晶体管100可以包括:半导体层10,具有第一导电类型(例如:图1中示意为P型),并具有衬底掺杂浓度n1;阱区20,具有与该第一导电类型相反的第二导电类型(例如:图1中示意为N型),该阱区20可以位于所述半导体层10之中/之上,并且具有阱区掺杂浓度n2(例如该阱区掺杂浓度n2可以在1x1014cm-3到1x1017cm-3之间);体区30,具有所述的第一导电类型(例如:图1中以DP区表示),形成于阱区20中,并具有体区掺杂浓度n3;源区40,具有所述的第二导电类型(例如:图1中以N+区表示),该源区40位于所述体区30中并且具有源区掺杂浓度n4(例如该源区掺杂浓度n4可以高于1x1019cm-3),该源区掺杂浓度n4高于所述阱区掺杂浓度n2;漏区50,具有所述的第二导电类型(例如:图1中以另一个N+区表示),该漏区50形成于所述阱区20中,与所述体区分离,并具有漏区掺杂浓度n5,该漏区掺杂浓度n5高于所述阱区掺杂浓度n2;栅结构60,形成于阱区20的靠近所述源区40一侧的部分之上并覆盖所述源区40的一部分;以及沟槽型肖特基势垒结构70,由所述阱区20的上表面20S开始纵向延伸穿过所述源区40、所述体区30以及所述阱区20的至少一部分使该沟槽型肖特基势垒结构70的侧壁与阱区20之间形成纵向金属-半导体接触(即肖特基接触)70SB从而构成肖特基势垒或肖特基二极管(为简明器件也标记为70SB,参见图1中用同样标记为70SB的虚线框指示出的部分)。该沟槽型肖特基势垒结构70具有预设的纵向沟槽深度D1,通过调节其预设的纵向沟槽深度D1可以灵活调节其侧壁与阱区20之间形成的肖特基接触70SB所具有的纵向肖特基接触深度D2,从而也可以灵活调节该肖特基接触70SB的肖特接触面积。其中该沟槽型肖特基势垒结构70可以由高导电性能的金属(例如钛Ti、钴Co、钨W、镍Ni等)、金属化合物(例如TiC、TiN、TiSi)或合金材料亦或前述材料的组合物制作而成,可以作为该肖特基势垒70SB的阳极,该阱区20可以作为该肖特基势垒70SB的阴极。
该肖特基势垒/肖特基接触70SB可以用作肖特基二极管,耦接于横向场效应晶体管100的体区30和漏区50之间。该肖特基势垒70SB的正向导通压降Vfsb通常比该横向场效应晶体管100的体二极管(在体区30与阱区20之间形成)的正向导通压降Vfbd低(即:Vfsb<Vfbd,例如通常Vfsb大约为0.3V,而Vfbd大约为0.7V)。因而,当该横向场效应晶体管100作为功率开关器件应用于例如功率变换器中时,该肖特基势垒70SB有助于减小二极管导通损耗,尤其是横向场效应晶体管100工作于较高的开关频率时,效果更明显。另外,该肖特基势垒70SB相比于横向场效应晶体管100的体二极管具有更低的反向恢复电荷Qrr,因而可以由于该体二极管提供更快的反向恢复时间,有助于降低横向场效应晶体管100的体二极管引发的反向恢复损耗。
根据本公开各实施例的横向场效应晶体管100,通过制作所述沟槽型肖特基势垒结构70将肖特基势垒(肖特基二极管)70SB与该横向场效应晶体管100集成,并可以基于制作该横向场效应晶体管100的工艺步骤与该横向场效应晶体管100同时制作。由于该沟槽型肖特基势垒结构70纵向延伸进入所述阱区20与该阱区20形成纵向肖特基接触70SB,因而肖特基势垒(肖特基二极管)70SB的面积主要取决于该沟槽型肖特基势垒结构70的预设纵向沟槽深度D1,则该沟槽型肖特基势垒结构70的横向尺寸(宽度)W1可以最低缩减至工艺所允许制作的沟槽最小横向尺寸。相比于例如美国专利US8,686,502B2公开的在N型轻掺杂外延层900上表面制作金属化层(比如硅化钴层)910以形成横向肖特基接触的方案,本公开采用沟槽型肖特基势垒结构70可以大幅缩减横向场效应晶体管100的横向尺寸,这在当前集成电路应用中具有非常大的优势,能够更好地满足当今集成电路应用需要横向晶体管的尺寸和体积越来越小的同时具备良好的反向泄漏/反向衬底注入抑制能力的需求。
根据根据本公开的一个实施例,该横向场效应晶体管100还可以进一步包括体接触区31,位于所述体区30中,并且横向分布在所述源区40与所述沟槽型肖特基势垒结构70之间,参考图1所示。该体接触区31具有所述第一导电类型,并且具有体接触区掺杂浓度n6,该体接触区掺杂浓度n6高于所述体区掺杂浓度n3(即:n6>n3,例如n6可以大于1x1019cm-3)。图1中用位于源区40旁边的P+区域表示该体接触区31。该体接触区31有利于提升源区40至阱区20的电气接触性能,并有助于增大横向场效应晶体管100的安全工作区(SOA)。
根据根据本公开的一个实施例,如图2所示,所述沟槽型肖特基势垒结构70可以纵向延伸直至与半导体层10接触或延伸入半导体层10的一部分之中以使肖特基接触70SB的纵向肖特基接触深度D2(同时使其肖特基接触面积)最大化。另外,在图1示意的实施例中,沟槽型肖特基势垒结构70的底部区域(在图1中用虚线框70BT指示出的部分)存在拐角,因而并不希望其底部区域70BT与阱区20之间形成肖特基接触。图2示意的实施例中,沟槽型肖特基势垒结构70的底部区域与半导体层10接触或延伸入半导体层10的一部分之中则有助于避免沟槽型肖特基势垒结构70的底部区域70BT与阱区20之间形成肖特基接触。
根据根据本公开的一个实施例,如图3所示,该横向场效应晶体管100可选地还可以进一步包括具有所述第一导电类型的保护环区81,该保护环区81可以具有保护环区掺杂浓度n7,该保护环区掺杂浓度n7大于所述半导体层10的衬底掺杂浓度n1(即:n7>n1,例如n1可以在1x1014cm-3至1x1015cm-3之间,n7可以高于1x1019cm-3)。该保护环区掺杂浓度n7也可以大于所述体区掺杂浓度n3(即:n7>n3)。该保护环区81形成于所述沟槽型肖特基势垒结构70的底部周围,包络该沟槽型肖特基势垒结构70的底部区域70BT以使该保护环区81与该沟槽型肖特基势垒结构70的底部区域70BT之间形成欧姆接触。另外,该保护环区81可以用作该沟槽型肖特基势垒结构70的底部区域70BT的保护环以减小肖特基势垒(肖特基二极管)70SB的反向泄漏电流,并降低该沟槽型肖特基势垒结构70的底部区域70BT所承受的电场强度。
根据根据本公开的一个实施例,参考图4示意,该横向场效应晶体管100可选地还可以进一步包括掩埋层80,制作于所述半导体层10中,位于所述阱区20的下方,包络所述沟槽型肖特基势垒结构70的底部区域70BT并与所述沟槽型肖特基势垒结构70的底部及一部分侧壁接触。该掩埋层80可以具有所述第一导电类型(例如图1的示例中示意为P型,以PBL区表示),并具有掩埋层掺杂浓度n8,该掩埋层掺杂浓度n8大于所述半导体层10的衬底掺杂浓度n1(即:n8>n1,例如n1可以在1x1014cm-3至1x1015cm-3之间,n8可以在1x1016cm-3至1x1017cm-3之间)。一方面,该掩埋层80可以用作所述沟槽型肖特基势垒结构70的保护环,在该横向场效应晶体管100关断并且施加有较高的漏源电压(漏区50至源区40的压降)时,有助于降低肖特基势垒(肖特基二极管)70SB所承受的电场强度,并减小该肖特基势垒(肖特基二极管)70SB的反向泄漏电流。另一方面,该掩埋层80可以看作掩埋的降低表面电场(RESURF)层,其有助于进一步增大横向场效应晶体管100的击穿电压。同时,与不具有该掩埋层80的情况相比,该掩埋层80上方的阱区20可以具有更高的掺杂浓度,从而在保证横向场效应晶体管100的击穿电压得到改善或者至少不变的情况下,使横向场效应晶体管100的导通电阻能够进一步有效地降低。在一个实施例中,如图1示意,该掩埋层80横向延展至位于所述栅结构60的下方以更好发挥RESURF的作用。图1的示例中该掩埋层80部分纵向向上扩散至所述阱区20中,以在所述沟槽型肖特基势垒结构70未纵向延时进所述半导体层10的情况下保证该掩埋层80仍包络其底部区域70BT。在一个实施例中,该掩埋层80可以横向延展至位于体区30的下方(图中未示出)。在一个实施例中,该掩埋层80可以横向延展布满整个阱区20的下方(图中未示出)。
根据根据本公开的一个实施例,参考图5示意,横向场效应晶体管100可选地可以同时包括所述保护环区81和所述掩埋层80,该保护换区81形成于所述沟槽型肖特基势垒结构70的底部周围,包络该沟槽型肖特基势垒结构70的底部区域70BT以使该保护环区81与该沟槽型肖特基势垒结构70的底部区域70BT之间形成欧姆接触。该保护环区81可以与所述掩埋层80接触,可以至少部分地被所述掩埋层80包络,也可以如图5所示整体被所述掩埋层80包络。
图6A和图6B示出了根据本公开一个变型实施例的横向场效应晶体管100的部分示意图。图6A示出了该变型实施例的横向场效应晶体管100的平面俯视图,可以理解为由平行于x轴和z轴定义的切面对该横向场效应晶体管100的一部分进行切割所得的切面示意图。图6B示出了对图6A所示的横向场效应晶体管100以Y-Y’切割线沿y轴纵向切割所得的对应纵向剖面示意图。图6A和图6B实施例所示的横向场效应晶体管100与图1至图5实施例所示的横向场效应晶体管100不同在于其体接触区31并非横向分布在所述源区40与所述沟槽型肖特基势垒结构70之间,而是沿z轴方向与所述源区40交替排布(从图6A所示的平面俯视图看更易于理解),并且与所述源区40和所述沟槽型肖特基势垒结构70均接触。这样,体接触区31不再占用沿x轴方向的尺寸,因而有助于进一步缩减横向场效应晶体管100的横向尺寸。
图7示出了根据本公开一个变型实施例的横向场效应晶体管100的部分纵向剖面示意图。图7实施例所示的横向场效应晶体管100与图1至图6B实施例所示的横向场效应晶体管100不同在于,其体接触区31并非横向分布在所述源区40与所述沟槽型肖特基势垒结构70之间,也非沿z轴方向与所述源区40交替排布,而是纵向(沿y轴方向)位于所述源区40的下方,并且与所述源区40和所述沟槽型肖特基势垒结构70均接触。这样,一方面该体接触区31不再占用沿x轴方向的尺寸,因而有助于进一步缩减横向场效应晶体管100的横向尺寸。另一方面,纵向位于所述源区40的下方的该体接触区31可以更好地提升体区30与所述沟槽型肖特基势垒结构70之间的欧姆接触,降低由源区40、体区30和阱区20构成的寄生双极型晶体管(BJT)的基区电阻,进而可以提高该寄生BJT的开启电流,有助于抑制该寄生BJT的开启。
图8示出了根据本公开一个变型实施例的横向场效应晶体管100的部分纵向剖面示意图。与图7实施例所示的横向场效应晶体管100相比,图8实施例所示的横向场效应晶体管100中,其沟槽型肖特基势垒结构70可以包括第一槽型部分71和第二槽型部分72。该第一二槽型部分71位于该第一槽型部分71下方与该第一槽型部分71相连接。其中该第一槽型部分71具有第一沟槽深度D71和第一沟槽宽度W71,该第一沟槽深度D71大于所述源区40的源区深度D40(该源区深度D40指该源区40从阱区20上表面20S纵向扩散进该阱区中的纵向深度)并且小于所述体区30的体区深度D30(该体区深度D30指该体区30从阱区20上表面20S纵向扩散进该阱区中的纵向深度)。该第二槽型部分72具有第二沟槽深度D72和第二沟槽宽度W72,该第二沟槽宽度W72小于所述第一沟槽宽度W71,该第二沟槽深度D72与所述第一沟槽深度D71共同决定所述沟槽型肖特基势垒结构70的深度D1,该第二沟槽深度D72决定所述所述沟槽型肖特基势垒结构70的纵向肖特基接触深度D2(或者肖特基势垒/肖特基二极管70SB的面积)。在一个示例性实施例中,体区深度D30可以在0.3μm~1.5μm的范围,可以在源区深度D40可以在0.1μm~1.2μm的范围,第一沟槽深度D71可以在0.2μm~0.8μm的范围,所述沟槽型肖特基势垒结构70的深度D1可以在0.5μm~8μm的范围或者2μm~8μm的范围。本领域的技术人员应该理解这些深度范围仅仅是举例以帮助理解本公开的实施例,并不用于对本公开进行其它限定。
图1至图8所示的横向场效应晶体管100仅仅是示例性的,并不用于对本发明进行限定。本领域的技术人员应该理解在与根据本公开各实施例的横向场效应晶体管100的各方面特征以及其制造工艺相兼容的情况下,所述具有第一导电类型的半导体层10可能被提供并形成于其它层上(图1中未示出)。例如,在一个实施例中,半导体层10被提供并形成于具有所述第一导电类型的半导体衬底上;在另一实施例中,半导体层10可能被提供并形成于具有所述第一导电类型的外延层上,该外延层形成于具有所述第一导电类型的半导体衬底上;在又一实施例中,半导体层10甚至可能被提供并形成于硅氧化物(SOI)层上,该硅氧化物层形成于具有所述第一导电类型的半导体衬底上。根据本发明的各实施例倾向于覆盖所有包括了半导体层10并在其上形成横向场效应晶体管100的等同实施方式和/或者变形实施方式。
根据根据本公开的一个实施例,如图1至图8所示,横向场效应晶体管100还可以进一步选择性地包括场介电层90,形成于所述阱区20的位于栅结构60与漏区50之间的部分之上(例如可以制作为传统的厚场氧层)或之中(例如可以制作为浅沟槽型场介电层)。
本领域的技术人员应该理解,根据本公开各实施例的横向场效应晶体管100均可以根据实际应用需求选择性地同时包括所述掩埋层80和所述第一导电类型的保护环区81,也可以只包括其中之一,或者不包括所述掩埋层80和所述第一导电类型的保护环区81。本领域的技术人员还应该理解,根据本公开各实施例的横向场效应晶体管100均可以根据实际应用需求选择性地使所述沟槽型肖特基势垒结构70纵向延伸至阱区20的一部分钟,或者选择性地使其进一步纵向延伸直至与半导体层10接触或延伸入半导体层10的一部分之中。本领域的技术人员还应该理解,根据本公开各实施例的横向场效应晶体管100也可以根据实际应用需求选择性地不包括所述场介电层90,比如将横向晶体管100用在中低压(比如低于30V)应用中时。这些基于本公开各实施例所作出的结构选择、组合或简单变化均落入本公开的保护范围,不管这些变型后的结构有无在本公开的附图中示出,均视为可以由本申请所记载的内容直接毫无疑义地得出。
虽然本说明书中以N沟道横向DMOS为例对根据本发明各实施例的横向DMOS进行了示意与描述,但这并不意味着对本发明的限定,本领域的技术人员应该理解这里给出的结构及原理同样适用于P沟道横向晶体管及其它类型的半导体材料及半导体器件。
因此,上述本发明的说明书和实施方式仅仅以示例性的方式对本发明实施例的高压晶体管器件及其制造方法进行了说明,并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的,其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其他变化和修改并不超出本发明的精神和保护范围。

Claims (11)

1.一种横向场效应晶体管,包括:
半导体层,具有第一导电类型;
阱区,形成于所述半导体层之中或之上,具有与该第一导电类型相反的第二导电类型;
体区,形成于所述阱区中,具有所述的第一导电类型;
源区,位于所述体区中,具有所述的第二导电类型;
漏区,位于所述阱区中,与所述体区分离,具有所述的第二导电类型;
栅结构,形成于所述阱区的靠近所述源区一侧的部分之上;
沟槽型肖特基势垒结构,由所述阱区的上表面开始纵向延伸穿过所述源区、所述体区以及所述阱区的至少一部分使该沟槽型肖特基势垒结构的侧壁与该阱区之间形成纵向肖特基接触;以及
体接触区,位于所述体区中,纵向位于所述源区的下方,并且与所述源区和所述沟槽型肖特基势垒结构均接触;
其中所述沟槽型肖特基势垒结构包括第一槽型部分和第二槽型部分,其中该第一槽型部分具有第一沟槽深度,该第一沟槽深度大于所述源区的源区深度并且小于所述体区的体区深度;
该第一槽型部分具有第一沟槽宽度,该第二槽型部分具有第二沟槽宽度,该第二沟槽宽度小于所述第一沟槽宽度。
2.如权利要求1所述的横向场效应晶体管,其中,该沟槽型肖特基势垒结构具有预设的纵向沟槽深度,通过调节其预设的纵向沟槽深度可以调节所述肖特基接触的面积。
3.如权利要求1所述的横向场效应晶体管,其中所述沟槽型肖特基势垒结构纵向延伸直至与所述半导体层接触或延伸入所述半导体层的一部分之中。
4.如权利要求1所述的横向场效应晶体管,进一步包括:
保护环区,具有所述第一导电类型,形成于所述沟槽型肖特基势垒结构的底部周围,包络该沟槽型肖特基势垒结构的底部区域以使该保护环区与该沟槽型肖特基势垒结构的底部区域之间形成欧姆接触。
5.如权利要求4所述的横向场效应晶体管,其中该保护环区具有保护环区掺杂浓度,该保护环区掺杂浓度大于所述半导体层的掺杂浓度。
6.如权利要求5所述的横向场效应晶体管,其中该保护环区掺杂浓度大于所述体区的体区掺杂浓度。
7.如权利要求6所述的横向场效应晶体管,进一步包括:
掩埋层,制作于所述半导体层中,位于所述阱区的下方,所述保护环区与所述掩埋层接触或至少部分地被所述掩埋层包络。
8.如权利要求1所述的横向场效应晶体管,进一步包括:
掩埋层,制作于所述半导体层中,位于所述阱区的下方,包络所述沟槽型肖特基势垒结构的底部区域并与所述沟槽型肖特基势垒结构的底部及一部分侧壁接触。
9.如权利要求1所述的横向场效应晶体管,所述体接触区,位于所述体区中,在与所述横向和所述纵向均垂直的第三方向上与所述源区交替排布,并且与所述源区和所述沟槽型肖特基势垒结构均接触,该体接触区具有所述第一导电类型,并且具有体接触区掺杂浓度,该体接触区掺杂浓度高于所述体区的掺杂浓度。
10.如权利要求1所述的横向场效应晶体管,其中该第二槽型部分具有第二沟槽深度,该第二沟槽深度决定所述纵向肖特基接触的深度。
11.如权利要求1所述的横向场效应晶体管,进一步包括:
场介电层,形成于所述阱区的位于所述栅结构与所述漏区之间的部分之上。
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