CN110649090A - 半导体装置、半导体装置的制造方法 - Google Patents

半导体装置、半导体装置的制造方法 Download PDF

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CN110649090A
CN110649090A CN201910544776.2A CN201910544776A CN110649090A CN 110649090 A CN110649090 A CN 110649090A CN 201910544776 A CN201910544776 A CN 201910544776A CN 110649090 A CN110649090 A CN 110649090A
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region
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semiconductor device
transistor region
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上马场龙
高桥彻雄
古川彰彦
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Mitsubishi Corp
Mitsubishi Electric Corp
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Abstract

本发明的目的在于针对晶体管区域和二极管区域形成于同一衬底的半导体装置，提供在二极管的恢复动作时具有良好的耐受性的半导体装置。该半导体装置具备晶体管区域和二极管区域，该晶体管区域和二极管区域在具有第1导电型的漂移层的半导体衬底相邻地形成，该晶体管区域在该漂移层之上具有第2导电型的基极层以及扩散层、第1导电型的发射极层以及栅极电极，在该漂移层的下侧具有第2导电型的集电极层，该二极管区域在该漂移层之上具有第2导电型的阳极层，在该漂移层的下侧具有第1导电型的阴极层，该阴极层越接近该晶体管区域则从该半导体衬底的下表面算起的深度越浅，且第1导电型杂质浓度越小。

Description

半导体装置、半导体装置的制造方法
技术领域
本发明涉及半导体装置和半导体装置的制造方法。
背景技术
在家电产品、电动汽车、或者铁路等广泛的领域中使用的逆变器装置大多是对感应电动机等电感性负载进行驱动。逆变器装置具备多个IGBT(Insulated Gate BipolarTransistor)或MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)等开关元件以及续流二极管(下面，简称为“二极管”)等电力用半导体装置。逆变器装置谋求高效率、小功率，因此市场上要求电力用半导体装置的高性能化和低成本化。
为了电力用半导体装置的高性能化和低成本化，开发了沟槽MOS栅极构造、半导体衬底的薄板化、反向导通型IGBT(RC-IGBT：Reverse Conducting IGBT)等。RC-IGBT是将IGBT和二极管内置于同一半导体衬底而一体化得到的。RC-IGBT得到良好的电气特性的方法之一是分别在IGBT和二极管形成最佳的扩散层。
在专利文献1中公开有RC-IGBT。在专利文献1的半导体装置的背面，在二极管区域，交替地形成有多个n+型扩散层和p型扩散层。专利文献1提出了通过对在二极管动作时从背面侧供给的电子全体地进行抑制，从而降低恢复特性，同时抑制恢复耐量的下降。这些对于高频动作是有效的。但是，存在以下可能性，即，在低频动作时，如果将p型扩散层的有效面积减少而进行对应，则恢复耐量下降。
专利文献1：日本特开2012-129504号公报
在RC-IGBT的晶体管区域，通常，设置半导体衬底、阻挡金属、钨插塞以及表面电极的层叠构造。在半导体衬底的表面侧设置p+型扩散层、p型基极层以及n+型发射极层。另一方面，在RC-IGBT的二极管区域设置半导体衬底和表面电极。由于未在二极管区域形成阻挡金属和钨插塞，因此即使设置杂质浓度低的p-型阳极层，也能够在p-型阳极层与表面电极之间形成欧姆接触。
但是，在与二极管区域相邻的晶体管区域形成p型基极层或者p+型扩散层。因此，在RC-IGBT进行二极管动作时这些层产生较大的影响。特别地，存在以下问题，即，在二极管从导通切换至断开时的恢复动作时，空穴载流子向电阻比p-型阳极层低的p型基极层或者p+扩散层集中，切断电流变大。
发明内容
本发明就是为了解决上述这样的课题而提出的，其目的在于针对晶体管区域和二极管区域形成于同一衬底的半导体装置，提供在二极管的恢复动作时具有良好的耐受性的半导体装置及该半导体装置的制造方法。
本发明涉及的半导体装置的特征在于，具备：晶体管区域，其形成于具有第1导电型的漂移层的半导体衬底；以及二极管区域，其形成于该半导体衬底，是与该晶体管区域相邻地形成的，该晶体管区域具有：第2导电型的基极层，其形成于该漂移层之上；扩散层，其形成于该基极层之上，与该基极层相比第2导电型的杂质浓度高；第1导电型的发射极层，其形成于该基极层之上；栅极电极，其隔着绝缘膜而与该基极层接触；以及第2导电型的集电极层，其形成于该漂移层的下侧，该二极管区域具有：第2导电型的阳极层，其形成于该漂移层之上；以及第1导电型的阴极层，其形成于该漂移层的下侧，该阴极层具有与该晶体管区域接触的相邻区域，该相邻区域越接近该晶体管区域，则从该半导体衬底的下表面算起的深度越浅，且第1导电型杂质浓度越小。
本发明涉及的半导体装置的制造方法的特征在于，具备以下工序：在半导体衬底的下表面侧形成晶体管区域的集电极层；以及在该半导体衬底的下表面侧形成与该晶体管区域相邻的二极管区域的阴极层，在该阴极层的形成中，使用将该晶体管区域的下表面的至少一部分覆盖，在该二极管区域的下表面中的与该晶体管区域相邻的相邻区域，越接近该晶体管区域则开口密度越小的抗蚀掩模，向该半导体衬底的下表面进行离子注入。
本发明的其他特征在下面得以明确。
发明的效果
根据本发明，使阴极层的深度和杂质浓度越接近晶体管区域而越小，因而能够在二极管的恢复动作时提供良好的耐受性。
附图说明
图1是实施方式1涉及的半导体装置的俯视图。
图2是实施方式1涉及的半导体装置的仰视图。
图3是图1的A-A′线处的剖面图。
图4是图1的B-B′线处的剖面图。
图5是对二极管的接通动作进行说明的图。
图6是对二极管的断开动作进行说明的图。
图7是抗蚀掩模的俯视图。
图8是实施方式2涉及的半导体装置的剖面图。
图9是实施方式2涉及的半导体装置的剖面图。
标号的说明
1晶体管区域，2二极管区域，3漂移层，4基极层，5扩散层，6发射极层，14缓冲层，15集电极层，15A p型层，20阴极层，20A相邻区域，20B非相邻区域，50抗蚀掩模，50a、50b开口，100、101半导体装置。
具体实施方式
下面，一边参照附图一边对实施方式进行说明。附图是示意性地示出的，因此在不同的附图分别示出的图像的尺寸以及位置的相互关系未必是准确的，可以适当进行变更。另外，在下面的说明中，对相同或相应的结构要素标注相同的标号而进行图示，它们的名称以及功能也是相同的。因此，有时会省略关于它们的详细说明。
另外，在下面的说明中，有时会使用“上”、“下”、“侧”、“底”、“表”或者“背”等表示特定的位置以及方向的术语，但这些术语是为了使实施方式的内容容易理解，出于方便而使用的，并不对实际实施时的方向进行限定。另外，针对半导体的导电型，将第1导电型设为n型，将第2导电型设为p型而进行说明。但是，也可以将上述导电型调换，将第1导电型设为p型，将第2导电型设为n型。另外，n+型表示与n型相比杂质浓度高，n-型表示与n型相比杂质浓度低。同样地，p+型表示与p型相比杂质浓度高，p-型表示与p型相比杂质浓度低。
实施方式1.
图1是半导体装置100的俯视图。半导体装置100例如是RC-IGBT。图2是半导体装置100的仰视图。在图1、2中，省略半导体装置100的表面构造和背面构造。图3是图1的A-A′线处的剖面图。图1的A-A′线是穿过半导体装置100的p+型扩散层5的线。图4是图1的B-B′线处的剖面图。图1的B-B′线是穿过半导体装置100的n+型发射极层6的线。图1-4示出了晶体管区域1和二极管区域2相邻地形成于同一衬底。图1是图3、4的半导体衬底30的俯视图，图2是图3、4的半导体衬底30的仰视图。半导体衬底30的材料例如是硅。
首先，对晶体管区域1的结构进行说明。在晶体管区域1形成有例如IGBT。如图3、4所示的那样，晶体管区域1具有n-型漂移层3、p型基极层4、p+型扩散层5、n+型发射极层6、栅极绝缘膜8、栅极电极9、缓冲层14以及集电极层15。基极层4是在漂移层3之上形成的p型的层。扩散层5形成于基极层4之上，是与基极层4相比p型的杂质浓度高的层。发射极层6是在基极层4之上形成的n型的层。因此，在基极层4之上选择性地形成p+型扩散层5或者n+型发射极层6。具体地说，在图1的A-A′线处的剖面，在基极层4的上表面形成扩散层5，在图1的B-B′线处的剖面，在基极层4的上表面形成发射极层6。在图1中图示了n+型发射极层6在俯视观察时包围p+型扩散层5。
形成有多个沟槽7，这些沟槽7从p+型扩散层5或者n+型发射极层6的上表面贯穿发射极层6以及基极层4而到达漂移层3。在各沟槽7的内部隔着栅极绝缘膜8而埋入有栅极电极9。栅极电极9隔着栅极绝缘膜8而与基极层4相对。换言之，栅极电极9隔着栅极绝缘膜8而与基极层4接触。集电极层15是在漂移层3的下侧隔着n型缓冲层14而形成的p型的层。晶体管区域1能够形成于具有n-型漂移层3的半导体衬底30。
半导体装置100的表面构造在晶体管区域1具有作为发射极电极而起作用的上部电极10、层间绝缘膜11以及阻挡金属13。层间绝缘膜11覆盖栅极电极9，由此实现栅极电极9与上部电极10的绝缘。在层间绝缘膜11形成有接触孔12，扩散层5和发射极层6从接触孔12露出。
在层间绝缘膜11之上和接触孔12的内部形成阻挡金属13。接触孔12中的阻挡金属13通过形成于扩散层5和发射极层6之上，从而与扩散层5和发射极层6的上表面接触。阻挡金属13通过例如与以硅作为材料的半导体衬底30接触而硅化物化，具有降低与扩散层5以及发射极层6之间的接触电阻的效果。为了实现设计规则的细微化，也可以在阻挡金属13之上形成钨插塞。在对接触孔12使用钨插塞的情况下，为了得到上述效果，阻挡金属13能够使用过渡金属，或者例如钛或氮化钛的多层构造。在阻挡金属13或者阻挡金属13和钨插塞之上形成上部电极10。上部电极10例如是铝合金。上部电极10隔着阻挡金属13而与扩散层5以及发射极层6接触。
在晶体管区域1的背面侧设置有n型缓冲层14、p型集电极层15以及集电极(collector)电极(electrode)16。半导体装置100能够通过具有基极层4、扩散层5、栅极绝缘膜8以及栅极电极9的沟槽MOS栅极构造而实现高沟道密度，通过使漂移层3变薄而实现低损耗化。如果使漂移层3变薄，则需要在开关断开时从基极层4与漂移层3的pn结向漂移层3延伸的耗尽层的阻挡部，因此作为该阻挡部设置与漂移层3相比杂质浓度高的n型缓冲层14。但是，缓冲层14的有无使根据产品用途决定的，有时根据产品用途而省略。
在形成于晶体管区域1的IGBT的接通时，具有基极层4、发射极层6、栅极绝缘膜8以及栅极电极9的n沟道MOSFET变为接通，在集电极层15、缓冲层14、漂移层3、基极层4、发射极层6的路径中流过电流。基极层4、发射极层6、栅极绝缘膜8以及栅极电极9是晶体管构造，更具体而言是沟槽MOS栅极构造。在晶体管区域1形成多个沟槽MOS栅极构造。扩散层5具有清除在IGBT的断开时所产生的载流子的效果，以及降低与上部电极10之间的接触电阻的效果。
接下来，对二极管区域2的结构进行说明。如图3、4所示的那样，在半导体衬底30形成有二极管区域2。二极管区域2具备n-型漂移层3、伪栅极电极18、p-型阳极层19、n型缓冲层14以及n+型阴极层20。漂移层3在晶体管区域1和二极管区域2是共通的。在二极管区域2，在漂移层3的上表面形成p-型阳极层19。形成有多个沟槽7，这些沟槽7从阳极层19的上表面贯穿阳极层19而到达漂移层3。在各沟槽7的内部隔着伪栅极绝缘膜17而埋入有伪栅极电极18。
在二极管区域2作为表面构造设置有上部电极10。上部电极10在晶体管区域1和二极管区域2是共通的，例如能够设为铝合金等。通过在晶体管区域1和二极管区域2共用上部电极10，从而能够在半导体装置100的装配工艺中，使导线键合或者焊料润湿性这些条件在晶体管区域1和二极管区域2相同。p-型阳极层19的p型杂质浓度低，因此能够得到良好的二极管特性。但是，如果使p-型阳极层19与阻挡金属13接触，则成为肖特基结，接触电阻变大。因此，不在二极管区域2设置阻挡金属13。上部电极10在晶体管区域1与阻挡金属13直接接触，在二极管区域2与阳极层19直接接触。
在二极管区域2作为背面侧的构造形成有n型缓冲层14、n+型阴极层20以及集电极电极16。缓冲层14和集电极电极16在晶体管区域1和二极管区域2是共通的。阴极层20是在漂移层3的下侧隔着缓冲层14而形成的n+型的层。
图3、4示出了阴极层20具备相邻区域20A和非相邻区域20B。相邻区域20A与晶体管区域1接触。非相邻区域20B与相邻区域20A接触，不与晶体管区域1接触。相邻区域20A是设置了深度和杂质浓度的梯度的区域。具体地说，相邻区域20A是越接近晶体管区域1，则从半导体衬底30的下表面30B算起的深度越浅，且n型杂质浓度越小的区域。换言之，相邻区域20A在接近晶体管区域1的方向，即图3的纸面的左右方向具有深度和杂质浓度的梯度。其结果，例如如图3所示相邻区域20A的上表面倾斜。
这样，通过设置越接近晶体管区域1则深度和浓度越小的相邻区域20A，从而从n+型阴极层20供给至漂移层3的电子随着接近晶体管区域1而被抑制。因此，能够将电气特性的恶化抑制到最小限度，而不用完全切断晶体管区域1与二极管区域2的边界部附近的二极管动作。
图3、4示出了在相邻区域20A之上形成的p型层15A。p型层15A设置在相邻区域20A与缓冲层14之间。在半导体装置100的制造过程中，能够使p型集电极层15形成于半导体衬底30的下表面整面，然后，形成阴极层20。在这种情况下，p型层15A与集电极层15通过同一工艺形成，因而p型层15A的p型杂质浓度与集电极层15的p型杂质浓度相同或者实质上相同。通过设置p型层15A，从而缓冲层14与集电极层15的上表面、p型层15A的上表面以及阴极层20的上表面接触。
如图3所示，非相邻区域20B是与相邻区域20A接触，与晶体管区域1以一定距离分离的区域。非相邻区域20B是从半导体衬底30的下表面30B算起的深度恒定的区域。另外，非相邻区域20B的杂质浓度是均匀的或者实质上均匀的。非相邻区域20B对由相邻区域20A引起的晶体管性能的下降进行抑制，其中，在相邻区域20A对阴极层20的深度和杂质浓度设置梯度。将晶体管区域1与非相邻区域20B的距离23设定为何种程度，是根据半导体装置100的产品用途、漂移层3的厚度或者阳极层19的浓度等各种各样的要素而设定的。
图5是对在二极管区域2形成的二极管的接通动作进行说明的图。如果向上部电极10与集电极电极16之间施加正电压，则空穴载流子21从p-型阳极层19注入至漂移层3，电子载流子22从n+型阴极层20注入至漂移层3。并且，如果施加电压变得大于或等于电压降，则二极管成为接通状态。如果二极管成为接通状态，则在上部电极10、p-型阳极层19、n-型漂移层3、n+型阴极层20、集电极电极16的路径中流过电流。
图6是对二极管的断开动作进行说明的图。通常，二极管在从导通切换至断开时进行恢复动作。恢复动作是指，在暂时向二极管的负侧流过电流之后，返回至断开状态的动作。将产生恢复动作的期间称为反向恢复时间。并且，将在反向恢复时间内产生的负电流的峰值称为恢复电流，将产生的损耗称为恢复损耗。就仅具有二极管的元件而言，如果进入反向恢复时间，则空穴载流子流向p-型阳极层，电子载流子流向n+型阴极层。但是，半导体装置100在晶体管区域1具有p+型扩散层5以及p型基极层4，这些层的电阻比p-型阳极层19低。因此，如图6所示，在恢复动作时空穴载流子21流入晶体管区域1，在二极管区域2与晶体管区域1的边界部有可能发生电流集中。但是，通过设置上述的相邻区域20A，从而使得从阴极层20供给至漂移层3的电子量随着接近晶体管区域1与二极管区域2的边界而受到抑制。并且，从晶体管区域1供给至漂移层3的空穴载流子也受到抑制。因此，在断开动作时滞留于漂移层3的空穴载流子21的排出不会集中于p+型扩散层5和p型基极层4，能够得到良好的恢复耐量。
这样的恢复耐量的改善是在二极管的接通动作时以不改变作为晶体管来说有效的面积的状态实现的。另外，实施方式1的半导体装置100具备阻挡金属13，该阻挡金属13形成于上部电极10与p+型扩散层5之间以及上部电极10与n+型发射极层6之间。并且，p-型阳极层19与上部电极10直接接触。这样，不在二极管区域2形成阻挡金属13，因此能够降低p-型阳极层19的杂质浓度，能够改善恢复特性。
并且，在晶体管区域1和二极管区域2共用上部电极10，因此在使用了RC-IGBT的装配工艺中，能够使导线键合或者焊料润湿性这些条件在晶体管区域1和二极管区域2相同。另外，通过由上部电极10将接触孔12填埋，使上部电极10与MOS栅极构造的半导体层接触，从而能够避免使用钨插塞等昂贵的接触插塞。这会使RC-IGBT的制造成本下降。
对半导体装置100的制造方法进行说明。首先，在晶体管区域1和二极管区域2，在n-型漂移层3的下表面形成n型缓冲层14。并且，在半导体衬底30的下表面侧整面形成p型集电极层。形成的集电极层的一部分成为晶体管区域1的集电极层15和二极管区域2的p型层15A。
接着，在二极管区域2，在n型缓冲层14之下形成n+型阴极层20。即，在半导体衬底30的下表面侧形成n+型阴极层20。图7是表示阴极层20的形成所使用的抗蚀掩模50的例子的俯视图。抗蚀掩模50覆盖晶体管区域1的整面，但在二极管区域2具有开口50a、50b。开口50a是点图案。形成有多个开口50a。从非相邻区域20B起越接近晶体管区域1则开口50a的密度越小。换言之，接近晶体管区域1的部分处的开口50a的密度比远离晶体管区域1的部分处的开口50a的密度小。开口50b是整面开口的部分。通过开口50b，从而抗蚀掩模50使半导体衬底30的下表面30B的形成非相邻区域20B的部分露出。
通过开口50a而注入相邻区域20A的杂质，通过开口50b而注入非相邻区域20B的杂质。点图案的开口50a使离子注入密度的控制成为可能。通过在杂质注入之后进行退火处理，从而形成具有相邻区域20A和非相邻区域20B的阴极层20。
图7示出了抗蚀掩模50的开口50a、50b的一个例子，但开口的尺寸、点图案的形状以及密度不限定于此。可以采用满足以下条件的各种各样的开口图案，即，覆盖晶体管区域1的下表面的至少一部分，在二极管区域2的下表面中的形成相邻区域20A的部分，越接近晶体管区域1则开口密度越小。此外，也可以通过抗蚀掩模50而覆盖晶体管区域1的背面整体，还可以通过抗蚀掩模而使晶体管区域1的背面的一部分露出，向晶体管区域1的一部分进行离子注入。
通过使用越接近晶体管区域1则开口密度越小的抗蚀掩模，从而能够通过1次离子注入而形成上述的阴极层20。另外，如果n+型阴极层20的杂质浓度下降，则扩散深度变浅，因此在二极管区域2残留p型层15A。
为了使n+型阴极层20的深度以及杂质浓度具有梯度，想到进行多次光刻工序和离子注入工序，对离子注入工序中的注入能量以及剂量进行控制。但是，在这样的方法中晶片工艺的处理工序增加，因此成本增加。
实施方式2.
图8、9是实施方式2涉及的半导体装置101的剖面图。包含p+型扩散层5的剖面图是图8，包含发射极层6的剖面图是图9。实施方式2的半导体装置101在漂移层3与基极层4之间具备与漂移层3相比n型杂质浓度高的n型载流子积蓄层24。即，在晶体管区域1，在p型基极层4的下表面侧设置有n型载流子积蓄层24。由设置载流子积蓄层24而实现的第1效果是能够抑制被从p+型扩散层5以及p型基极层4向漂移层3提供的空穴载流子。由设置载流子积蓄层24而实现的第2效果是在晶体管的导通时能够使p型基极层4与n-型漂移层3的接通电阻下降、接通电压下降，使稳态损耗减小。

Claims (9)

1.一种半导体装置，其特征在于，具备：
晶体管区域，其形成于具有第1导电型的漂移层的半导体衬底；以及
二极管区域，其在所述半导体衬底与所述晶体管区域相邻地形成，
所述晶体管区域具有：第2导电型的基极层，其形成于所述漂移层之上；扩散层，其形成于所述基极层之上，与所述基极层相比第2导电型的杂质浓度高；第1导电型的发射极层，其形成于所述基极层之上；栅极电极，其隔着绝缘膜而与所述基极层接触；以及第2导电型的集电极层，其形成于所述漂移层的下侧，
所述二极管区域具有：第2导电型的阳极层，其形成于所述漂移层之上；以及第1导电型的阴极层，其形成于所述漂移层的下侧，
所述阴极层具有与所述晶体管区域接触的相邻区域，所述相邻区域越接近所述晶体管区域，则从所述半导体衬底的下表面算起的深度越浅，且第1导电型杂质浓度越小。
2.根据权利要求1所述的半导体装置，其特征在于，
所述阴极层具备与所述相邻区域接触，从所述半导体衬底的下表面算起的深度恒定的非相邻区域。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述相邻区域的上表面倾斜。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
在所述相邻区域之上具备与所述集电极层杂质浓度相同的p型层。
5.根据权利要求4所述的半导体装置，其特征在于，具备：
第1导电型的缓冲层，其与所述集电极层的上表面、所述p型层的上表面以及所述阴极层的上表面接触。
6.根据权利要求1至5中任一项所述的半导体装置，其特征在于，具备：
阻挡金属，其形成于所述扩散层和所述发射极层之上；以及
上部电极，其与所述阻挡金属以及所述阳极层直接接触。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
在所述漂移层与所述基极层之间具备与所述漂移层相比第1导电型的杂质浓度高的第1导电型的载流子积蓄层。
8.一种半导体装置的制造方法，其特征在于，具备以下工序：
在半导体衬底的下表面侧形成晶体管区域的集电极层；以及
在所述半导体衬底的下表面侧形成与所述晶体管区域相邻的二极管区域的阴极层，
在所述阴极层的形成中，使用将所述晶体管区域的下表面的至少一部分覆盖，在所述二极管区域的下表面中的与所述晶体管区域相邻的相邻区域，越接近所述晶体管区域则开口密度越小的抗蚀掩模，向所述半导体衬底的下表面进行离子注入。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，
所述抗蚀掩模使所述半导体衬底的下表面的与所述相邻区域接触的区域即非相邻区域露出。
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