WO2022247262A1 - 半导体器件的元胞结构及半导体器件 - Google Patents

半导体器件的元胞结构及半导体器件 Download PDF

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Publication number
WO2022247262A1
WO2022247262A1 PCT/CN2021/141280 CN2021141280W WO2022247262A1 WO 2022247262 A1 WO2022247262 A1 WO 2022247262A1 CN 2021141280 W CN2021141280 W CN 2021141280W WO 2022247262 A1 WO2022247262 A1 WO 2022247262A1
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gate
trench
trench gate
semiconductor device
substrate
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PCT/CN2021/141280
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English (en)
French (fr)
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林苡任
史波
肖婷
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珠海格力电器股份有限公司
珠海零边界集成电路有限公司
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Priority to JP2023567226A priority Critical patent/JP2024516448A/ja
Publication of WO2022247262A1 publication Critical patent/WO2022247262A1/zh
Priority to US18/472,136 priority patent/US20240014301A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

Definitions

  • the present disclosure relates to the technical field of semiconductor devices, in particular to a cell structure of a semiconductor device and the semiconductor device.
  • IGBT Insulated Gate Bipolar Transistor
  • 4C communication, computer, consumer electronics, automotive electronics
  • home appliances and other industrial fields as the core semiconductor device for weak current control and strong current.
  • IGBT devices have dozens of parameters, so the difficulty of IGBT design is the balance between the parameters.
  • the reverse withstand voltage and the forward conduction voltage drop are a pair of compromise parameters, the breakdown voltage (BV) increases, and the saturation voltage drop (Vcesat, the smaller the better) increases; for example, the Vcesat decreases and the off time increases.
  • BV breakdown voltage
  • Vcesat saturation voltage drop
  • short-circuit tolerance There is also a compromise between saturation current, conduction voltage drop, and short-circuit tolerance. Generally, if the saturation current increases, Vcesat decreases, and the short-circuit tolerance decreases; therefore, it is particularly important to design various parameters reasonably.
  • the current mainstream IGBT structure includes field stop type, which is specifically divided into planar gate field stop type IGBT as shown in Figure 1 (including N-type drift region, Pbody base region, N+ source region, planar gate, interlayer dielectric layer, emission Pole, N-type field stop layer FS, P+ collector region and collector) and trench gate field stop type IGBT as shown in Figure 2 (including N-type drift region, Pbody base region, N+ source region, trench gate , interlayer dielectric layer, emitter, N-type field stop layer FS, P+ collector region and collector).
  • the current most mainstream IGBT structure is the trench gate field stop type.
  • the cell size of the trench gate IGBT is reduced, which increases the current density of the IGBT, but the increase of the current density leads to a decrease in the short circuit time. That is, the short circuit safe operating area (Short Circuit Safe Operating Area, SCSOA) is reduced, resulting in the trench gate IGBT being unable to achieve a compromise between the three parameters of saturation current, Vcesat, and short circuit tolerance.
  • SCSOA Short Circuit Safe Operating Area
  • the present disclosure provides a cellular structure of a semiconductor device and a semiconductor device, which solves the technology that the trench gate IGBT cannot achieve a compromise between the three parameters of saturation current, Vcesat, and short-circuit tolerance in the related art question.
  • the present disclosure provides a cellular structure of a semiconductor device, including:
  • At least one first trench gate, at least one second trench gate, at least one third trench gate and at least one fourth trench gate arranged side by side in the upper surface of the substrate in sequence;
  • a second conductivity type well region located in the upper surface of the substrate and disposed between any two adjacent trench gates;
  • a source region of the first conductivity type located in the upper surface of the well region and disposed on both sides of the first trench gate, both sides of the third trench gate and both sides of the fourth trench gate; wherein, The first trench gate, the third trench gate and the fourth trench gate are respectively in contact with the source regions on both sides thereof;
  • an emitter metal layer located above the substrate and electrically connected to the source region
  • first trench gate, the second trench gate and the third trench gate are isolated from the emitter metal layer by a first interlayer dielectric layer, and the fourth trench gate electrically connected to the emitter metal layer.
  • the first trench gate, the second trench gate and the third trench gate are connected to an external gate driving circuit.
  • the depths of the first trench gate, the second trench gate, the third trench gate and the fourth trench gate are all greater than the The depth of the well region.
  • it also includes:
  • the second interlayer dielectric layer includes a contact hole penetrating through the second interlayer dielectric layer, and the emitter metal layer is realized by the conductive material filled in the contact hole and the fourth trench gate. electrical connection.
  • the first trench gate includes a first gate trench located in the upper surface of the substrate and a first gate trench disposed in the first gate trench.
  • the second trench gate includes a second gate trench located in the upper surface of the substrate and a first gate trench disposed in the second gate trench. Two gates, and a second gate insulating layer disposed between the second gate trench and the second gate.
  • the third trench gate includes a third gate trench located in the upper surface of the substrate and a first gate trench disposed in the third gate trench.
  • the fourth trench gate includes a fourth gate trench located in the upper surface of the substrate and a first gate trench disposed in the fourth gate trench.
  • it also includes:
  • a first conductivity type field stop layer located under the substrate
  • a collector metal layer located below the collector region and electrically connected to the collector region.
  • the present disclosure provides a semiconductor device, including several cell structures of the semiconductor device according to any one of the first aspect.
  • the present disclosure provides a cellular structure of a semiconductor device and a semiconductor device.
  • the cellular structure of the semiconductor device includes a substrate of a first conductivity type; at least one first trench gate, At least one second trench gate, at least one third trench gate and at least one fourth trench gate; a well of the second conductivity type located in the upper surface of the substrate and between any two adjacent trench gates region; a source region of the first conductivity type located in the upper surface of the well region and located on both sides of the first trench gate, on both sides of the third trench gate and on both sides of the fourth trench gate; An emitter metal layer above the substrate and electrically connected to the source region; wherein, the first trench gate, the second trench gate and the third trench gate are connected to the emitter The metal layers are isolated by the first interlayer dielectric layer, and the fourth trench gate is electrically connected to the emitter metal layer.
  • This cellular structure can achieve a better balance of the three parameters of conduction voltage drop, saturation current, and short-circuit time, and can also improve the dv
  • FIG. 1 is a schematic cross-sectional structure diagram of a cell structure of an existing planar gate stop type IGBT;
  • FIG. 2 is a schematic cross-sectional structure diagram of a cell structure of an existing trench gate stop type IGBT
  • Fig. 3 is a schematic cross-sectional structure diagram of a cell structure of a semiconductor device shown in an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic front top view of a cell structure of a semiconductor device shown in an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional structure diagram of a semiconductor device shown in an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic flowchart of a method for preparing a cell structure of a semiconductor device shown in an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional structure diagram of a first intermediate structure formed in related steps of a method for manufacturing a cellular structure of a semiconductor device shown in an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic cross-sectional structure diagram of a second intermediate structure formed in related steps of a method for manufacturing a cellular structure of a semiconductor device shown in an exemplary embodiment of the present disclosure
  • FIG. 9 is a schematic cross-sectional structure diagram of a third intermediate structure formed in related steps of a method for manufacturing a cell structure of a semiconductor device shown in an exemplary embodiment of the present disclosure.
  • first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections do not should be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • spatial relational terms such as “above”, “over”, “below”, “below” and the like may be used herein for convenience of description to describe The relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the figure If the device is turned over, elements or features described as “below” other elements or features will then be oriented “above” the other elements or features. Hence, the exemplary terms “beneath” and “beneath” " may include both orientations above and below. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptors used herein are interpreted accordingly.
  • Embodiments of the disclosure are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. As such, variations from the shapes shown are to be expected due to, for example, manufacturing technique and/or tolerances. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
  • an embodiment of the present disclosure provides a cell structure of a semiconductor device, including a substrate 101, at least one first trench gate 102, at least one second trench gate 103, at least one third trench gate Trench gate 104, at least one fourth trench gate 105, well region 106, source region 107, first interlayer dielectric layer 108, second interlayer dielectric layer 109, emitter metal layer 110, field stop layer 111, collector The electrode region 112 and the collector metal layer (not shown in the figure).
  • first trench gate 102, the second trench gate 103, the third trench gate 104 and the fourth trench gate 105 in FIG. 4 they are not shown in FIG. Out-well region 106, source region 107, first interlayer dielectric layer 108, second interlayer dielectric layer 109, emitter metal layer 110, field stop layer 111, collector region 112 and collector metal layer.
  • FIG. 3 it can be understood that the well region 106, the source region 107, the first interlayer dielectric layer 108, the second interlayer dielectric layer 109, the emitter metal layer 110, the field stop layer 111, the collector region 112 and the collector The shape and location of the metal layer.
  • the substrate 101 is a substrate of the first conductivity type.
  • the substrate 101 may be an epitaxially grown drift layer.
  • At least one first trench gate 102 , at least one second trench gate 103 , at least one third trench gate 104 , and at least one fourth trench gate 105 are arranged side by side in sequence on the upper surface of the substrate 101 .
  • the first trench gate 102 , the second trench gate 103 , the third trench gate 104 and the fourth trench gate 105 extend along the same direction.
  • the first trench gate 102 includes a first gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a first gate (not marked in the figure) disposed in the first gate trench, and A first gate insulating layer (not shown in the figure) disposed between the first gate trench and the first gate, the first gate insulating layer isolates the first gate from the substrate 101 .
  • the second trench gate 103 includes a second gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a second gate (not marked in the figure) disposed in the second gate trench, and A second gate insulating layer (not shown in the figure) is disposed between the second gate trench and the second gate, and the second gate insulating layer isolates the second gate from the substrate 101 .
  • the third trench gate 104 includes a third gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a third gate (not marked in the figure) disposed in the third gate trench, and A third gate insulating layer (not shown in the figure) is disposed between the third gate trench and the third gate, and the third gate insulating layer isolates the third gate from the substrate 101 .
  • the fourth trench gate 105 includes a fourth gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a fourth gate (not marked in the figure) disposed in the fourth gate trench, and A fourth gate insulating layer (not shown in the figure) is disposed between the fourth gate trench and the fourth gate, and the fourth gate insulating layer isolates the fourth gate from the substrate 101 .
  • the well region 106 is a well region of the second conductivity type, and the well region 106 is located between any two adjacent trench gates, the first trench gate 102, the second trench gate 103, the third trench gate 104 and the fourth trench gate
  • the depth of the trench gate 105 is greater than the depth of the well region 106 .
  • the upper surface of the well region 106 is flush with the upper surface of the substrate 101 .
  • Each trench gate is in contact with well regions 106 on both sides thereof.
  • the junction depth of the well region 106 may be 2.5um.
  • the source region 107 is a source region of the first conductivity type, and the source region 107 is arranged in the surface of the well region 106, and is arranged on both sides of the first trench gate 102, on both sides of the third trench gate 104 and on the fourth trench gate 105.
  • the first trench gate 102 is in contact with the source regions 107 on both sides
  • the third trench gate 104 is in contact with the source regions 107 on both sides
  • the fourth trench gate 105 is in contact with the source regions on both sides.
  • the upper surface of the source region 107 is flush with the upper surface of the well region 106 .
  • the junction depth of the source region 107 is smaller than the junction depth of the well region 106, and the junction depth of the source region 107 may be 0.8um.
  • the first interlayer dielectric layer 108 is disposed above the first trench gate 102, the second trench gate 103 and the third trench gate 104, and covers the first trench gate 102, the second trench gate 103 and the third trench gate.
  • the upper surface of the trench gate 104 is used to isolate the first trench gate 102 , the second trench gate 103 and the third trench gate 104 from the emitter metal layer 110 .
  • the second interlayer dielectric layer 109 is disposed above the fourth trench gate 105 . And the second interlayer dielectric layer 109 includes a contact hole (not marked in the figure) penetrating through the second interlayer dielectric layer 109 .
  • the contact hole is filled with a conductive material, and the conductive material may be the same as that of the emitter metal layer 110 .
  • the first interlayer dielectric layer 108 may be made of the same material as the second interlayer dielectric layer 109, which may be borophosphosilicate glass (BPSG) with a thickness of 1 ⁇ m.
  • BPSG borophosphosilicate glass
  • the emitter metal layer 110 is located above the substrate 101 and covers the upper surface of the source region 107 , is electrically connected to the source region 107 , and is electrically connected to the fourth trench gate 105 through the conductive material filled in the contact hole.
  • the first trench gate 102 , the second trench gate 103 and the third trench gate 104 are connected to an external gate driving circuit.
  • first trench gate 102 and the third trench gate 104 are not only connected to the external gate drive circuit, but also contact the source regions 107 on both sides thereof, so the first trench gate 102 and the third trench gate 104 are both true. gate, the first grooved gate 102, the third grooved gate 104, and the emitter.
  • the source region 107 can realize the passage of electrons in the inversion electron channel from the emitter to the collector, forming a conduction current.
  • the second trenched gate 103 is connected to an external gate drive circuit, there is no source region 107 on both sides of the second trenched gate 103, so the second trenched gate 103 is a dummy gate, and the second trenched gate 103 and the emitter are applied with a voltage Afterwards, an inversion channel (carrier accumulation) is first formed in the well region 106, but because there is no source region 107, the inversion electron channel cannot be formed, and the conduction current cannot be formed.
  • the presence of anti-type electrons can attract the holes of the collector upward at a uniform speed, which is beneficial to the current transport of the holes, so that Vcesat can be reduced and the conduction loss can be reduced.
  • the fourth trenched gate 105 is in contact with the source regions 107 on both sides, the fourth trenched gate 105 is electrically connected to the emitter metal layer 110, and is not connected to an external gate control circuit, so gate control cannot be realized, and there is no inversion Electrons are formed in the well region 106, and the passage of electrons cannot be realized, and a conductive channel cannot be formed, which reduces the saturation current and increases the short-circuit time Tsc.
  • the real gates and dummy gates are arranged alternately, the first trench gate 102 and the third trench gate 104 are separated by at least one second trench gate 103, and the gap between the second trench gate 103 and the fourth trench gate 105 is are isolated by at least one third trench gate 104.
  • the quantity of the first trench gate 102, the second trench gate 103, the third trench gate 104 and the fourth trench gate 105 is related to the size of the cell structure, the first trench gate 102, the second trench gate
  • the numbers of the trench gates 103 , the third trench gates 104 and the fourth trench gates 105 are selected to achieve a compromise among saturation current, Vcesat and short-circuit tolerance.
  • the real gates are separated by virtual gates, which can avoid excessive current density and improve the dv/dt resistance of the device.
  • the number of the first trench gate 102 may be 1, the number of the second trench gate 103 may be 2, the number of the third trench gate 104 may be 1, and the number of the fourth trench gate
  • the number of grids 105 may be two.
  • the field stop layer 111 is a field stop layer of the first conductivity type, and the field stop layer 111 is located under the substrate 101 .
  • the collector region 112 is a collector region of the second conductivity type, and the collector region 112 is located under the field stop layer 111 .
  • the collector metal layer is located under the collector region 112 and is electrically connected to the collector region 112 .
  • the first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P type
  • the first conductivity type is P type
  • the second conductivity type is N type.
  • the cell structure of the semiconductor device is the cell structure of the IGBT.
  • a cellular structure of a semiconductor device including a substrate 101 of a first conductivity type; Grooved gate 103, at least one third trenched gate 104 and at least one fourth trenched gate 105; second conductivity type well region 106 located in the upper surface of substrate 101 and between any two adjacent trenched gates; The first conductivity type source region 107 located in the upper surface of the well region 106 and located on both sides of the first trench gate 102, on both sides of the third trench gate 104 and on both sides of the fourth trench gate 105; located above the substrate 101 and At the same time, the emitter metal layer 110 is electrically connected to the source region 107; wherein, the first trench gate 102, the second trench gate 103 and the third trench gate 104 are connected to the emitter metal layer 110 through a first interlayer dielectric The fourth trench gate 105 is electrically connected to the emitter metal layer 110 .
  • This cellular structure can achieve a better balance of the three parameters of conduction voltage drop, saturation current, and short-circuit time,
  • this embodiment provides a semiconductor device, which includes several cell structures as in the first embodiment, the structure of which is shown in FIG. 5 .
  • FIG. 6 is a schematic flowchart of a method for preparing a cell structure of a semiconductor device shown in an embodiment of the present disclosure.
  • 7 to 9 are schematic cross-sectional structure diagrams formed in related steps of a method for manufacturing a cell structure of a semiconductor device shown in an embodiment of the present disclosure.
  • FIGS. 6 and 7-9 detailed steps of an exemplary method of a method for manufacturing a cell structure of a semiconductor device proposed by an embodiment of the present disclosure will be described with reference to FIGS. 6 and 7-9 .
  • the method for preparing the cellular structure of the semiconductor device of this embodiment includes the following steps:
  • Step S110 providing a substrate 101 of a first conductivity type.
  • the substrate 101 is an epitaxial silicon wafer or a silicon wafer grown by a zone melting method (ie, FZ method).
  • the substrate 101 may be an epitaxially grown drift layer.
  • Step S120 forming at least one first trench gate 102 , at least one second trench gate 103 , at least one third trench gate 104 and at least one fourth trench gate 105 in sequence on the upper surface of the substrate 101 .
  • the first trench gate 102 , the second trench gate 103 , the third trench gate 104 and the fourth trench gate 105 extend along the same direction.
  • the first trench gate 102 includes a first gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a first gate (not marked in the figure) disposed in the first gate trench, and A first gate insulating layer (not shown in the figure) disposed between the first gate trench and the first gate, the first gate insulating layer isolates the first gate from the substrate 101 .
  • the second trench gate 103 includes a second gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a second gate (not marked in the figure) disposed in the second gate trench, and A second gate insulating layer (not shown in the figure) is disposed between the second gate trench and the second gate, and the second gate insulating layer isolates the second gate from the substrate 101 .
  • the third trench gate 104 includes a third gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a third gate (not marked in the figure) disposed in the third gate trench, and A third gate insulating layer (not shown in the figure) is disposed between the third gate trench and the third gate, and the third gate insulating layer isolates the third gate from the substrate 101 .
  • the fourth trench gate 105 includes a fourth gate trench (not marked in the figure) located in the upper surface of the substrate 101 and a fourth gate (not marked in the figure) disposed in the fourth gate trench, and A fourth gate insulating layer (not shown in the figure) is disposed between the fourth gate trench and the fourth gate, and the fourth gate insulating layer isolates the fourth gate from the substrate 101 .
  • the gate material of each trench gate includes polysilicon.
  • Step S130 forming a well region 106 of the second conductivity type between any two adjacent trench gates in the upper surface of the substrate 101 .
  • the well region 106 is a well region of the second conductivity type, and the well region 106 is located between any two adjacent trench gates, the first trench gate 102, the second trench gate 103, the third trench gate 104 and the fourth trench gate
  • the depth of the trench gate 105 is greater than the depth of the well region 106 .
  • the upper surface of the well region 106 is flush with the upper surface of the substrate 101 .
  • Each trench gate is in contact with well regions 106 on both sides thereof.
  • the P-type well region 106 is formed by boron ion implantation, the implantation energy is 100KeV, and a doped junction of about 2.5um is formed through a 1000-degree thermal process. Deep, the ion implantation of the P-type well region 106 is full-surface ion implantation without a mask.
  • the grid of each trench gate is implanted with boron ions, which has little influence on the performance of the grid.
  • Step S140 As shown in FIG. 7 , the source regions of the first conductivity type on both sides of the first trench gate 102 , on both sides of the third trench gate 104 and on both sides of the fourth trench gate 105 in the upper surface of the well region 106 107 ; wherein, the first trench gate 102 , the third trench gate 104 and the fourth trench gate 105 are respectively in contact with the source regions 107 on both sides thereof.
  • the source region 107 is a source region of the first conductivity type, and the source region 107 is arranged in the surface of the well region 106, and is arranged on both sides of the first trench gate 102, on both sides of the third trench gate 104 and on the fourth trench gate 105.
  • the first trench gate 102 is in contact with the source regions 107 on both sides
  • the third trench gate 104 is in contact with the source regions 107 on both sides
  • the fourth trench gate 105 is in contact with the source regions on both sides. 107 contacts.
  • the upper surface of the source region 107 is flush with the upper surface of the well region 106 .
  • the N-type source region 107 is formed by phosphorus ion implantation, the implantation energy is 90Kev, and then a 950-degree thermal process forms a doped junction depth of 0.8um , the ion implantation of the N-type source region 107 requires a mask.
  • step S140 the following steps are also included:
  • S144 As shown in FIG. 9, pattern the dielectric layer 113 to form a first interlayer dielectric layer 108 above the first trench gate 102, the second trench gate 103, and the third trench gate 104.
  • a second interlayer dielectric layer 109 is formed above the four-trench gate 105 ; wherein, the second interlayer dielectric layer 109 includes a contact hole penetrating through the second interlayer dielectric layer 109 .
  • the material of the above-mentioned dielectric layer includes borophosphosilicate glass (BPSG), and the deposition thickness is 1um.
  • BPSG borophosphosilicate glass
  • the patterning process of the dielectric layer is mainly a hole etching process.
  • Step S150 forming an emitter metal layer 110 electrically connected to the source region 107 above the substrate 101; wherein, the first trench gate 102, the second trench gate 103 and the third trench gate 104 are connected to the emitter metal layer 110 are isolated by the first interlayer dielectric layer 108 , and the fourth trench gate 105 is electrically connected to the emitter metal layer 110 .
  • the emitter metal layer 110 is electrically connected to the fourth trench gate 105 through the conductive material filled in the contact hole.
  • the conductive material may be the same as that of the emitter metal layer 110 .
  • the first trench gate 102 , the second trench gate 103 and the third trench gate 104 are connected to an external gate driving circuit.
  • first trench gate 102 and the third trench gate 104 are not only connected to the external gate drive circuit, but also contact the source regions 107 on both sides thereof, so the first trench gate 102 and the third trench gate 104 are both true. gate, the first grooved gate 102, the third grooved gate 104, and the emitter.
  • the source region 107 can realize the passage of electrons in the inversion electron channel from the emitter to the collector, forming a conduction current.
  • the second trenched gate 103 is connected to an external gate drive circuit, there is no source region 107 on both sides of the second trenched gate 103, so the second trenched gate 103 is a dummy gate, and the second trenched gate 103 and the emitter are applied with a voltage Afterwards, an inversion channel (carrier accumulation) is first formed in the well region 106, but because there is no source region 107, the inversion electron channel cannot be formed, and the conduction current cannot be formed.
  • the presence of anti-type electrons can attract the holes of the collector upward at a uniform speed, which is beneficial to the current transport of the holes, so that Vcesat can be reduced and the conduction loss can be reduced.
  • the fourth trenched gate 105 is in contact with the source regions 107 on both sides, the fourth trenched gate 105 is electrically connected to the emitter metal layer 110, and is not connected to an external gate control circuit, so gate control cannot be realized, and there is no inversion Electrons are formed in the well region 106, and the passage of electrons cannot be realized, and a conductive channel cannot be formed, which reduces the saturation current and increases the short-circuit time Tsc.
  • the real gates and dummy gates are arranged alternately, the first trench gate 102 and the third trench gate 104 are separated by at least one second trench gate 103, and the gap between the second trench gate 103 and the fourth trench gate 105 is The gaps are isolated by at least one third trench gate 104 .
  • the quantity of the first trench gate 102, the second trench gate 103, the third trench gate 104 and the fourth trench gate 105 is related to the size of the cell structure, the first trench gate 102, the second trench gate
  • the number of trench gates 103 , third trench gates 104 and fourth trench gates 105 is selected to achieve a compromise among saturation current, Vcesat, and short-circuit tolerance.
  • the real gates are separated by virtual gates, which can avoid excessive current density and improve the dv/dt resistance of the device.
  • the number of the first trench gate 102 may be 1, the number of the second trench gate 103 may be 2, the number of the third trench gate 104 may be 1, and the number of the fourth trench gate 105 may be 2.
  • step S150 it is necessary to deposit and etch the front passivation layer, then perform the back thinning process, and then perform ion implantation. metallization etc.
  • Step S160 forming a field stop layer 111 of the first conductivity type under the substrate 101 .
  • the field stop layer 111 is a field stop layer of the first conductivity type, and the field stop layer 111 is located under the substrate 101 .
  • Step S170 forming the second conductivity type collector region 112 under the field stop layer 111 .
  • the collector region 112 is a collector region of the second conductivity type, and the collector region 112 is located under the field stop layer 111 .
  • Step S180 forming a collector metal layer electrically connected to the collector region 112 under the collector region 112 .
  • the first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P type
  • the first conductivity type is P type
  • the second conductivity type is N type.
  • the manufacturing process flow of the semiconductor device in the present disclosure is consistent with that of the traditional trench gate IGBT, and does not increase the complexity of the process and the cost.
  • a method for preparing a cellular structure of a semiconductor device including: providing a substrate 101 of a first conductivity type; forming at least one first trench gate 102, At least one second trench gate 103, at least one third trench gate 104, and at least one fourth trench gate 105; a second conductivity type is formed between any adjacent two trench gates on the upper surface of the substrate 101 Well region 106; the first conductivity type source region 107 on both sides of the first trench gate 102, on both sides of the third trench gate 104 and on both sides of the fourth trench gate 105 in the upper surface of the well region 106; A trench gate 102, a third trench gate 104 and a fourth trench gate 105 are respectively in contact with source regions 107 on both sides thereof; an emitter metal layer 110 electrically connected to the source region 107 is formed above the substrate 101; wherein , the first trench gate 102, the second trench gate 103 and the third trench gate 104 are isolated from the emitter metal layer 110 by the first interlayer dielectric layer

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Abstract

本公开提供一种半导体器件的元胞结构及半导体器件，该元胞结构包括第一导电类型衬底；依次并排设置于所述衬底上表面内的至少一个第一沟槽栅、至少一个第二沟槽栅、至少一个第三沟槽栅和至少一个第四沟槽栅；位于所述阱区上表面内并位于所述第一沟槽栅两侧、所述第三沟槽栅两侧和所述第四沟槽栅两侧的第一导电类型源区；位于所述衬底上方并同时与所述源区电连接的发射极金属层；其中，所述第一沟槽栅、所述第二沟槽栅和所述第三沟槽栅与所述发射极金属层之间通过第一层间介质层隔离，所述第四沟槽栅与所述发射极金属层电连接。这种元胞结构可以实现更好的导通压降、饱和电流、短路时间三大参数的折中平衡。

Description

半导体器件的元胞结构及半导体器件
本公开要求于2021年05月26日提交中国专利局、申请号为202121152384.0、发明名称为“半导体器件的元胞结构及半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体器件技术领域，具体涉及一种半导体器件的元胞结构及半导体器件。
背景技术
IGBT(Insulated Gate Bipolar Transistor)，即绝缘栅双极型晶体管，作为弱电控制强电的核心半导体器件广泛应用于工业、4C(通信、计算机、消费电子、汽车电子)、家电等产业领域。IGBT器件具有几十项参数，因此IGBT的设计难点也是各参数之间的平衡。例如反向耐压与正向导通压降为一对折中参数，击穿电压(BV)增加，饱和压降(Vcesat，越小越好)增加；例如Vcesat降低，关断时间增加。饱和电流与导通压降、短路耐量也存在一个折中，一般如果饱和电流增加，则Vcesat减小、短路耐量减小；因此合理设计各参数显得尤为重要。
目前主流的IGBT结构包括场截止型，具体分为如图1所示的平面栅场截止型IGBT(包括N型漂移区、Pbody基区、N+源区、平面栅极、层间介质层、发射极、N型场截止层FS、P+集电区和集电极)和如图2所示的沟槽栅场截止型IGBT(包括N型漂移区、Pbody基区、N+源区、沟槽栅极、层间介质层、发射极、N型场截止层FS、P+集电区和集电极)。其中，目前最为主流的IGBT结构为沟槽栅场截止型，沟槽栅IGBT相对于平面栅IGBT的元胞尺寸减小，增加了IGBT的电流密度，但电流密度的增加导致短路时间的下降，即短路安全工作区(Short Circuit Safe Operating Area，SCSOA)减小，导致沟槽栅IGBT无法实现饱和电流、Vcesat、短路耐量这三个参数之间的折中平衡。
发明内容
针对上述问题，本公开提供了一种半导体器件的元胞结构及半导体器件，解决了相关技术中沟槽栅IGBT无法实现饱和电流、Vcesat、短路耐量这三个参数之间的折中平衡的技术问题。
第一方面，本公开提供一种半导体器件的元胞结构，包括：
第一导电类型衬底；
依次并排设置于所述衬底上表面内的至少一个第一沟槽栅、至少一个第二沟槽栅、至少一个第三沟槽栅和至少一个第四沟槽栅；
位于所述衬底上表面内并设置于任意相邻两个沟槽栅之间的第二导电类型阱区；
位于所述阱区上表面内并设置于所述第一沟槽栅两侧、所述第三沟槽栅两侧和所述第四沟槽栅两侧的第一导电类型源区；其中，所述第一沟槽栅、所述第三沟槽栅和所述第四沟槽栅分别与其两侧的所述源区相接触；
位于所述衬底上方并同时与所述源区电连接的发射极金属层；
其中，所述第一沟槽栅、所述第二沟槽栅和所述第三沟槽栅与所述发射极金属层之间通过第一层间介质层隔离，所述第四沟槽栅与所述发射极金属层电连接。
根据本公开的实施例，在一些实施方式中，所述第一沟槽栅、所述第二沟槽栅和所述第三沟槽栅连接外部栅极驱动电路。
根据本公开的实施例，在一些实施方式中，所述第一沟槽栅、所述第二沟槽栅、所述第三沟槽栅和所述第四沟槽栅的深度均大于所述阱区的深度。
根据本公开的实施例，在一些实施方式中，还包括：
位于所述第四沟槽栅上方的第二层间介质层；
其中，所述第二层间介质层包括贯穿所述第二层间介质层的接触孔，所述发射极金属层通过填充于所述接触孔内的导电材料与所述第四沟槽栅实现电连接。
根据本公开的实施例，在一些实施方式中，所述第一沟槽栅包括位于所述衬底上表面内的第一栅极沟槽和设置于所述第一栅极沟槽内的第一栅极，以及设置于所述第一栅极沟槽和所述第一栅极之间的第一栅极绝缘层。
根据本公开的实施例，在一些实施方式中，所述第二沟槽栅包括位于所述衬底上表面内的第二栅极沟槽和设置于所述第二栅极沟槽内的第二栅极，以及设置于所述第二栅极沟槽和所述第二栅极之间的第二栅极绝缘层。
根据本公开的实施例，在一些实施方式中，所述第三沟槽栅包括位于所述衬底上表面内的第三栅极沟槽和设置于所述第三栅极沟槽内的第三栅极，以及设置于所述第三栅极沟槽和所述第三栅极之间的第三栅极绝缘层。
根据本公开的实施例，在一些实施方式中，所述第四沟槽栅包括位于所述衬底上表面内的第四栅极沟槽和设置于所述第四栅极沟槽内的第四栅极，以及设置于所述第四栅极沟槽和所述第四栅极之间的第四栅极绝缘层。
根据本公开的实施例，在一些实施方式中，还包括：
位于所述衬底下方的第一导电类型场截止层；
位于所述场截止层下方的第二导电类型集电极区；
位于所述集电极区下方并与所述集电极区电连接的集电极金属层。
第二方面，本公开提供一种半导体器件，包括若干如第一方面任一项所述的半导体器件的元胞结构。
采用上述技术方案，至少能够达到如下技术效果：
本公开提供一种半导体器件的元胞结构及半导体器件，该半导体器件的元胞结构包括第一导电类型衬底；依次并排设置于所述衬底上表面内的至少一个第一沟槽栅、至少一个第二沟槽栅、至少一个第三沟槽栅和至少一个第四沟槽栅；位于所述衬底上表面内并位于任意相邻两个沟槽栅之间的第二导电类型阱区；位于所述阱区上表面内并位于所述第一沟槽栅两侧、所述第三沟槽栅两侧和所述第四沟槽栅两侧的第一导电类型源区；位于所述衬底上方并同时与所述源区电连接的发射极金属层；其中，所述第一沟槽栅、所述第二沟槽栅和所述第三沟槽栅与所述发射极金属层之间通过第一层间介质层隔离，所述第四沟槽栅与所述发射极金属层电连接。这种元胞结构可以实现更好的导通压降、饱和电流、短路时间三大参数的折中平衡，还可以提升器件的抗dv/dt能力。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是现有的平面栅截止型IGBT的元胞结构的剖面结构示意图；
图2是现有的沟槽栅截止型IGBT的元胞结构的剖面结构示意图；
图3是本公开一示例性实施例示出的一种半导体器件的元胞结构的剖面结构 示意图；
图4是本公开一示例性实施例示出的一种半导体器件的元胞结构的正面俯视示意图；
图5是本公开一示例性实施例示出的一种半导体器件的剖面结构示意图；
图6是本公开一示例性实施例示出的一种半导体器件的元胞结构的制备方法流程示意图；
图7是本公开一示例性实施例示出的一种半导体器件的元胞结构的制备方法的相关步骤形成的第一中间结构的剖面结构示意图；
图8是本公开一示例性实施例示出的一种半导体器件的元胞结构的制备方法的相关步骤形成的第二中间结构的剖面结构示意图；
图9是本公开一示例性实施例示出的一种半导体器件的元胞结构的制备方法的相关步骤形成的第三中间结构的剖面结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本公开的实施方式，借此对本公开如何应用技术手段来解决技术问题，并达到相应技术效果的实现过程能充分理解并据以实施。本公开实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本公开的保护范围之内。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应理解，尽管可使用术语“第一”、“第二”、“第三”等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
应理解，空间关系术语例如“在...上方”、位于...上方”、“在...下方”、“位于...下方”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下方”的元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下方”和“在...下”可包括上和下两个取向。器件可以 另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述本公开的实施例。这样，可以预期由于例如制备技术和/或容差导致的从所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制备导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本公开的范围。
为了彻底理解本公开，将在下列的描述中提出详细的结构以及步骤，以便阐释本公开提出的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
实施例一
如图3和图4所示，本公开实施例提供一种半导体器件的元胞结构，包括衬底101、至少一个第一沟槽栅102、至少一个第二沟槽栅103、至少一个第三沟槽栅104、至少一个第四沟槽栅105、阱区106、源区107、第一层间介质层108、第二层间介质层109、发射极金属层110、场截止层111、集电极区112和集电极金属层(图中未示出)。
需要说明的是，为了在图4中清楚显示第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105的形状和位置，图4中并未示出阱区106、源区107、第一层间介质层108、第二层间介质层109、发射极金属层110、场截止层111、集电极区112和集电极金属层。但是结合图3是可以理解到阱区106、源区107、第一层间介质层108、第二层间介质层109、发射极金属层110、场截 止层111、集电极区112和集电极金属层的形状和位置。
示例性地，衬底101为第一导电类型的衬底。衬底101可以为外延生长的漂移层。
至少一个第一沟槽栅102、至少一个第二沟槽栅103、至少一个第三沟槽栅104、至少一个第四沟槽栅105依次并排设置于衬底101上表面内。
第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105延同一方向延伸。
第一沟槽栅102包括位于衬底101上表面内的第一栅极沟槽(图中未标注)和设置于第一栅极沟槽内的第一栅极(图中未标注)，以及设置于第一栅极沟槽和第一栅极之间的第一栅极绝缘层(图中未示出)，第一栅极绝缘层将第一栅极与衬底101隔离。
第二沟槽栅103包括位于衬底101上表面内的第二栅极沟槽(图中未标注)和设置于第二栅极沟槽内的第二栅极(图中未标注)，以及设置于第二栅极沟槽和第二栅极之间的第二栅极绝缘层(图中未示出)，第二栅极绝缘层将第二栅极与衬底101隔离。
第三沟槽栅104包括位于衬底101上表面内的第三栅极沟槽(图中未标注)和设置于第三栅极沟槽内的第三栅极(图中未标注)，以及设置于第三栅极沟槽和第三栅极之间的第三栅极绝缘层(图中未示出)，第三栅极绝缘层将第三栅极与衬底101隔离。
第四沟槽栅105包括位于衬底101上表面内的第四栅极沟槽(图中未标注)和设置于第四栅极沟槽内的第四栅极(图中未标注)，以及设置于第四栅极沟槽和第四栅极之间的第四栅极绝缘层(图中未示出)，第四栅极绝缘层将第四栅极与衬底101隔离。
阱区106为第二导电类型的阱区，阱区106位于任意相邻两个沟槽栅之间，第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105的深度均大于阱区106的深度。阱区106的上表面与衬底101的上表面相平齐。每个沟槽栅与其两侧的阱区106接触。阱区106的结深可以为2.5um。
源区107为第一导电类型的源区，源区107设置于阱区106表面内，并设置于第一沟槽栅102两侧、第三沟槽栅104两侧和第四沟槽栅105两侧，第一沟槽栅102分别与其两侧的源区107相接触，第三沟槽栅104分别与其两侧的源区107 相接触，第四沟槽栅105分别与其两侧的源区107相接触。源区107的上表面与阱区106的上表面平齐。源区107的结深小于阱区106的结深，源区107的结深可以为0.8um。
第一层间介质层108设置于第一沟槽栅102、第二沟槽栅103和第三沟槽栅104上方，并覆盖第一沟槽栅102、第二沟槽栅103和第三沟槽栅104的上表面，以使第一沟槽栅102、第二沟槽栅103和第三沟槽栅104与发射极金属层110隔离。
第二层间介质层109设置于第四沟槽栅105上方。且第二层间介质层109包括贯穿第二层间介质层109的接触孔(图中未标注)。接触孔内填充有导电材料，该导电材料可以与发射极金属层110的材料相同。
第一层间介质层108可以与第二层间介质层109的材料相同，材料可以为硼磷硅玻璃(BPSG)，厚度为1um。
发射极金属层110位于衬底101上方并覆盖源区107的上表面，与源区107形成电连接，并通过填充于接触孔内的导电材料与第四沟槽栅105实现电连接。
第一沟槽栅102、第二沟槽栅103和第三沟槽栅104连接外部栅极驱动电路。
可见，第一沟槽栅102和第三沟槽栅104既连接外部栅极驱动电路，又与其两侧的源区107接触，所以第一沟槽栅102和第三沟槽栅104均为真栅，第一沟槽栅102、第三沟槽栅104和发射极外加电压以后首先是阱区106中形成反型沟道，然后第一沟槽栅102和第三沟槽栅104两侧的源区107可以实现反型电子沟道中电子从发射极到集电极的通路，形成导通电流。
第二沟槽栅103虽然连接外部栅极驱动电路，但是第二沟槽栅103两侧没有源区107，所以第二沟槽栅103为虚栅，第二沟槽栅103和发射极外加电压以后首先是阱区106中形成反型沟道(载流子积累)，但是由于没有源区107，导致反型电子通道不能形成，不能形成导通电流。但是，在第二沟槽栅103和发射极外加电压以后，反型电子的存在可以吸引集电极的空穴向上匀速，有利于空穴电流运输，因此可以降低Vcesat，降低导通损耗。
第四沟槽栅105虽然与其两侧的源区107接触，但是第四沟槽栅105与发射极金属层110电连接，不连外部栅极控制电路，不能实现栅极控制，既没有反型电子在阱区106中形成，也无法实现电子的通路，不能形成导电沟道，减小了饱和电流，提升短路时间Tsc。
其中，真栅与虚栅交替设置，第一沟槽栅102和第三沟槽栅104之间通过至少一个第二沟槽栅103隔离，第二沟槽栅103和第四沟槽栅105之间通过至少一个第三沟槽栅104隔离。
其中，第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105的数量与该元胞结构的大小有关，第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105的数量被选择成能够实现饱和电流、Vcesat、短路耐量之间的折中平衡。
且真栅之间通过虚栅间隔开，可以避免过大的电流密度，可以提升器件的抗dv/dt能力。
示例性的，如图3所示，第一沟槽栅102的数量可以为1，第二沟槽栅103的数量可以为2，第三沟槽栅104的数量可以为1，第四沟槽栅105的数量可以为2。
场截止层111为第一导电类型的场截止层，场截止层111位于衬底101下方。
集电极区112为第二导电类型的集电极区，集电极区112位于场截止层111下方。
集电极金属层位于集电极区112下方并与集电极区112形成电连接。
在本实施例中，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。具体地，根据实际需要制备的器件类型进行合理选择即可。
该半导体器件的元胞结构为IGBT的元胞结构。
在本实施例中，提供一种半导体器件的元胞结构，包括第一导电类型衬底101；依次并排设置于衬底101上表面内的至少一个第一沟槽栅102、至少一个第二沟槽栅103、至少一个第三沟槽栅104和至少一个第四沟槽栅105；位于衬底101上表面内并位于任意相邻两个沟槽栅之间的第二导电类型阱区106；位于阱区106上表面内并位于第一沟槽栅102两侧、第三沟槽栅104两侧和第四沟槽栅105两侧的第一导电类型源区107；位于衬底101上方并同时与源区107电连接的发射极金属层110；其中，第一沟槽栅102、第二沟槽栅103和第三沟槽栅104与发射极金属层110之间通过第一层间介质层108隔离，第四沟槽栅105与发射极金属层110电连接。这种元胞结构可以实现更好的导通压降、饱和电流、短路时间三大参数的折中平衡，还可以提升器件的抗dv/dt能力。
实施例二
在实施例一的基础上，本实施例提供一种半导体器件，其包括若干如实施例一中的元胞结构，其结构如图5所示。
实施例三
在实施例一的基础上，本实施例提供一种半导体器件的元胞结构的制备方法。图6是本公开实施例示出的一种半导体器件的元胞结构的制备方法流程示意图。图7-图9是本公开实施例示出的一种半导体器件的元胞结构的制备方法的相关步骤形成的剖面结构示意图。下面，参照图6和图7-图9来描述本公开实施例提出的半导体器件的元胞结构的制备方法一个示例性方法的详细步骤。
如图6所示，本实施例的半导体器件的元胞结构的制备方法，包括如下步骤：
步骤S110：提供第一导电类型衬底101。
衬底101为外延硅片或者区熔法(即FZ法)生长的硅片。衬底101可以为外延生长的漂移层。
步骤S120：在衬底101上表面内形成依次并排的至少一个第一沟槽栅102、至少一个第二沟槽栅103、至少一个第三沟槽栅104和至少一个第四沟槽栅105。
第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105延同一方向延伸。
第一沟槽栅102包括位于衬底101上表面内的第一栅极沟槽(图中未标注)和设置于第一栅极沟槽内的第一栅极(图中未标注)，以及设置于第一栅极沟槽和第一栅极之间的第一栅极绝缘层(图中未示出)，第一栅极绝缘层将第一栅极与衬底101隔离。
第二沟槽栅103包括位于衬底101上表面内的第二栅极沟槽(图中未标注)和设置于第二栅极沟槽内的第二栅极(图中未标注)，以及设置于第二栅极沟槽和第二栅极之间的第二栅极绝缘层(图中未示出)，第二栅极绝缘层将第二栅极与衬底101隔离。
第三沟槽栅104包括位于衬底101上表面内的第三栅极沟槽(图中未标注)和设置于第三栅极沟槽内的第三栅极(图中未标注)，以及设置于第三栅极沟槽和第三栅极之间的第三栅极绝缘层(图中未示出)，第三栅极绝缘层将第三栅极 与衬底101隔离。
第四沟槽栅105包括位于衬底101上表面内的第四栅极沟槽(图中未标注)和设置于第四栅极沟槽内的第四栅极(图中未标注)，以及设置于第四栅极沟槽和第四栅极之间的第四栅极绝缘层(图中未示出)，第四栅极绝缘层将第四栅极与衬底101隔离。
各个沟槽栅的栅极的材料包括多晶硅。
步骤S130：在衬底101上表面内于任意相邻两个沟槽栅之间形成第二导电类型阱区106。
阱区106为第二导电类型的阱区，阱区106位于任意相邻两个沟槽栅之间，第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105的深度均大于阱区106的深度。阱区106的上表面与衬底101的上表面相平齐。每个沟槽栅与其两侧的阱区106接触。
其中，当第一导电类型为N型时，第二导电类型为P型时，P型阱区106采用硼离子注入形成，注入能量为100KeV，通过1000度热制程形成约2.5um的掺杂结深，P型阱区106的离子注入为整面离子注入，无需掩膜版。各个沟槽栅的栅极注入硼离子，对栅极性能的影响较小。
步骤S140：如图7所示，在阱区106上表面内于第一沟槽栅102两侧、第三沟槽栅104两侧和第四沟槽栅105两侧的第一导电类型源区107；其中，第一沟槽栅102、第三沟槽栅104和第四沟槽栅105分别与其两侧的源区107相接触。
源区107为第一导电类型的源区，源区107设置于阱区106表面内，并设置于第一沟槽栅102两侧、第三沟槽栅104两侧和第四沟槽栅105两侧，第一沟槽栅102分别与其两侧的源区107相接触，第三沟槽栅104分别与其两侧的源区107相接触，第四沟槽栅105分别与其两侧的源区107相接触。源区107的上表面与阱区106的上表面平齐。
其中，当第一导电类型为N型时，第二导电类型为P型时，N型源区107通过磷离子注入形成，注入能量为90Kev，然后950度热制程形成0.8um的掺杂结深，N型源区107的离子注入需要掩膜版。
步骤S140之后，还包括一下步骤：
S142：如图8所示，在衬底101上方沉积介质层113；
S144：如图9所示，对介质层113进行图案化，以在第一沟槽栅102、第二 沟槽栅103和第三沟槽栅104上方形成第一层间介质层108，在第四沟槽栅105上方形成第二层间介质层109；其中，第二层间介质层109包括贯穿第二层间介质层109的接触孔。
上述介质层的材料包括硼磷硅玻璃(BPSG)，沉积厚度为1um。
介质层的图案化工艺主要是孔刻蚀工艺，孔刻蚀工艺有两种，一种是开在源区107上方的孔，使源区107与发射极金属层110连接；第二种是开在第四沟槽栅105上方的孔(即上述接触孔)，以使第四沟槽栅105与后面形成的发射极金属层110电连接。
步骤S150：在衬底101上方形成与源区107电连接的发射极金属层110；其中，第一沟槽栅102、第二沟槽栅103和第三沟槽栅104与发射极金属层110之间通过第一层间介质层108隔离，第四沟槽栅105与发射极金属层110电连接。
具体的，发射极金属层110通过填充于接触孔内的导电材料与第四沟槽栅105实现电连接。该导电材料可以与发射极金属层110的材料相同。
第一沟槽栅102、第二沟槽栅103和第三沟槽栅104连接外部栅极驱动电路。
可见，第一沟槽栅102和第三沟槽栅104既连接外部栅极驱动电路，又与其两侧的源区107接触，所以第一沟槽栅102和第三沟槽栅104均为真栅，第一沟槽栅102、第三沟槽栅104和发射极外加电压以后首先是阱区106中形成反型沟道，然后第一沟槽栅102和第三沟槽栅104两侧的源区107可以实现反型电子沟道中电子从发射极到集电极的通路，形成导通电流。
第二沟槽栅103虽然连接外部栅极驱动电路，但是第二沟槽栅103两侧没有源区107，所以第二沟槽栅103为虚栅，第二沟槽栅103和发射极外加电压以后首先是阱区106中形成反型沟道(载流子积累)，但是由于没有源区107，导致反型电子通道不能形成，不能形成导通电流。但是，在第二沟槽栅103和发射极外加电压以后，反型电子的存在可以吸引集电极的空穴向上匀速，有利于空穴电流运输，因此可以降低Vcesat，降低导通损耗。
第四沟槽栅105虽然与其两侧的源区107接触，但是第四沟槽栅105与发射极金属层110电连接，不连外部栅极控制电路，不能实现栅极控制，既没有反型电子在阱区106中形成，也无法实现电子的通路，不能形成导电沟道，减小了饱和电流，提升短路时间Tsc。
其中，真栅与虚栅交替设置，第一沟槽栅102和第三沟槽栅104之间通过至 少一个第二沟槽栅103隔离，第二沟槽栅103和第四沟槽栅105之间通过至少一个第三沟槽栅104隔离。
其中，第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105的数量与该元胞结构的大小有关，第一沟槽栅102、第二沟槽栅103、第三沟槽栅104和第四沟槽栅105的数量选择成能够实现饱和电流、Vcesat、短路耐量之间的折中平衡。
且真栅之间通过虚栅间隔开，可以避免过大的电流密度，可以提升器件的抗dv/dt能力。
示例性的，第一沟槽栅102的数量可以为1，第二沟槽栅103的数量可以为2，第三沟槽栅104的数量可以为1，第四沟槽栅105的数量可以为2。
步骤S150之后，还需要进行正面钝化层的淀积、刻蚀，然后进行背面减薄工艺，接着再进行离子注入。金属化等工艺。
步骤S160：在衬底101下方形成第一导电类型场截止层111。
场截止层111为第一导电类型的场截止层，场截止层111位于衬底101下方。
步骤S170：在场截止层111下方形成第二导电类型集电极区112。
集电极区112为第二导电类型的集电极区，集电极区112位于场截止层111下方。
步骤S180：在集电极区112下方形成与集电极区112电连接的集电极金属层。
在本实施例中，第一导电类型和第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。具体地，根据实际需要制备的器件类型进行合理选择即可。
可见，本公开中的半导体器件与传统沟槽栅IGBT的制备工艺流程一致，不增加工艺复杂性，不增加成本。
在本实施例中，提供一种半导体器件的元胞结构的制备方法，包括：提供第一导电类型衬底101；在衬底101上表面内形成依次并排的至少一个第一沟槽栅102、至少一个第二沟槽栅103、至少一个第三沟槽栅104和至少一个第四沟槽栅105；在衬底101上表面内于任意相邻两个沟槽栅之间形成第二导电类型阱区106；在阱区106上表面内于第一沟槽栅102两侧、第三沟槽栅104两侧和第四沟槽栅105两侧的第一导电类型源区107；其中，第一沟槽栅102、第三沟槽栅104和第四沟槽栅105分别与其两侧的源区107相接触；在衬底101上方形成与源区107 电连接的发射极金属层110；其中，第一沟槽栅102、第二沟槽栅103和第三沟槽栅104与发射极金属层110之间通过第一层间介质层108隔离，第四沟槽栅105与发射极金属层110电连接。该制备方法制备出的元胞结构可以实现更好的导通压降、饱和电流、短路时间三大参数的折中平衡，还可以提升器件的抗dv/dt能力。
以上仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。虽然本公开所公开的实施方式如上，但的内容只是为了便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属技术领域内的技术人员，在不脱离本公开所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种半导体器件的元胞结构，包括：
    第一导电类型衬底；
    依次并排设置于所述衬底上表面内的至少一个第一沟槽栅、至少一个第二沟槽栅、至少一个第三沟槽栅和至少一个第四沟槽栅；
    位于所述衬底上表面内并设置于任意相邻两个沟槽栅之间的第二导电类型阱区；
    位于所述阱区上表面内并设置于所述第一沟槽栅两侧、所述第三沟槽栅两侧和所述第四沟槽栅两侧的第一导电类型源区；其中，所述第一沟槽栅、所述第三沟槽栅和所述第四沟槽栅分别与其两侧的所述源区相接触；
    位于所述衬底上方并同时与所述源区电连接的发射极金属层；
    其中，所述第一沟槽栅、所述第二沟槽栅和所述第三沟槽栅与所述发射极金属层之间通过第一层间介质层隔离，所述第四沟槽栅与所述发射极金属层电连接。
  2. 根据权利要求1所述的半导体器件的元胞结构，其中，所述第一沟槽栅、所述第二沟槽栅和所述第三沟槽栅连接外部栅极驱动电路。
  3. 根据权利要求1所述的半导体器件的元胞结构，其中，所述第一沟槽栅、所述第二沟槽栅、所述第三沟槽栅和所述第四沟槽栅的深度均大于所述阱区的深度。
  4. 根据权利要求1所述的半导体器件的元胞结构，其中，还包括：
    位于所述第四沟槽栅上方的第二层间介质层；
    其中，所述第二层间介质层包括贯穿所述第二层间介质层的接触孔，所述发射极金属层通过填充于所述接触孔内的导电材料与所述第四沟槽栅实现电连接。
  5. 根据权利要求1所述的半导体器件的元胞结构，其中，所述第一沟槽栅包括位于所述衬底上表面内的第一栅极沟槽和设置于所述第一栅极沟槽内的第一栅极，以及设置于所述第一栅极沟槽和所述第一栅极之间的第一栅极绝缘层。
  6. 根据权利要求1所述的半导体器件的元胞结构，其中，所述第二沟槽栅包括位于所述衬底上表面内的第二栅极沟槽和设置于所述第二栅极沟槽内的第二栅极，以及设置于所述第二栅极沟槽和所述第二栅极之间的第二栅极绝缘层。
  7. 根据权利要求1所述的半导体器件的元胞结构，其中，所述第三沟槽栅包括位于所述衬底上表面内的第三栅极沟槽和设置于所述第三栅极沟槽内的第三栅极，以及设置于所述第三栅极沟槽和所述第三栅极之间的第三栅极绝缘层。
  8. 根据权利要求1所述的半导体器件的元胞结构，其中，所述第四沟槽栅包括位于所述衬底上表面内的第四栅极沟槽和设置于所述第四栅极沟槽内的第四栅极，以及设置于所述第四栅极沟槽和所述第四栅极之间的第四栅极绝缘层。
  9. 根据权利要求1所述的半导体器件的元胞结构，其中，还包括：
    位于所述衬底下方的第一导电类型场截止层；
    位于所述场截止层下方的第二导电类型集电极区；
    位于所述集电极区下方并与所述集电极区电连接的集电极金属层。
  10. 一种半导体器件，包括若干如权利要求1至9任一项所述的半导体器件的元胞结构。
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