WO2016107504A1 - 垂直隧穿场效应晶体管及其制备方法 - Google Patents

垂直隧穿场效应晶体管及其制备方法 Download PDF

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Publication number
WO2016107504A1
WO2016107504A1 PCT/CN2015/098997 CN2015098997W WO2016107504A1 WO 2016107504 A1 WO2016107504 A1 WO 2016107504A1 CN 2015098997 W CN2015098997 W CN 2015098997W WO 2016107504 A1 WO2016107504 A1 WO 2016107504A1
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trench
region
epitaxial layer
gate
layer
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PCT/CN2015/098997
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English (en)
French (fr)
Inventor
赵静
杨喜超
张臣雄
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to a vertical tunneling field effect transistor and a preparation method thereof.
  • TFET tunneling field effect transistor
  • the process of increasing the output current as the drain terminal voltage increases is through the drain terminal voltage drop at the source tunneling junction, which is very effective in changing the tunneling tunneling width.
  • the output tunneling current is increased to achieve.
  • the tunneling current is small, so improving the tunneling current of a tunneling field effect transistor (TFET) is a very important problem.
  • tunneling field effect transistors generally adopt vertical tunneling, and the source region and the channel region undergo vertical tunneling under the action of the gate region.
  • this method can increase the tunneling probability, in the prior art, The overlap area between the source region and the gate region is limited, so that the tunneling area is small and the tunneling current is small.
  • the invention provides a vertical tunneling field effect transistor and a preparation method thereof, which can increase the tunneling area and effectively improve the tunneling current.
  • a vertical tunneling field effect transistor is provided, the vertical tunneling field effect crystal
  • the tube includes a source region, a first epitaxial layer, a gate dielectric layer, a gate region and two drain regions; the first epitaxial layer, the gate dielectric layer and the gate region are sequentially superposed on the source region;
  • a first trench is disposed on a surface of the source region facing the first epitaxial layer; a second trench is disposed on the first epitaxial layer, and the second trench is formed in the first trench The second trench is oriented in the same direction as the opening of the first trench; the first epitaxial layer forms a tunneling channel between the gate region and the source region;
  • the gate dielectric layer and the gate region are both disposed in the second trench; the gate dielectric layer is disposed on the first epitaxial layer, the gate dielectric layer is the gate region and the first epitaxial layer Layer isolation
  • Two drain regions are respectively disposed at opposite sides of the second trench, the drain region being isolated from the gate region; the first epitaxial layer extending to the drain region and the source Between the regions, and forming a channel between the drain region and the source region.
  • the gate region extends outside the second trench, and an extension portion is formed to extend toward the drain region, and the extension portion is disposed between the first epitaxial layer and the first epitaxial layer There is the gate dielectric layer.
  • a gap is formed between the extended portion of the gate region and the drain region.
  • the gate dielectric layer extends between the extended portion of the gate region and the drain region, and the drain region is isolated from the gate region by an insulating material.
  • the cross section of the first trench and the cross section of the second trench are both rectangular.
  • a third trench is disposed on the gate region, and the third trench is oriented in the same direction as the opening of the first trench.
  • a channel layer is further disposed between the drain region and the first epitaxial layer.
  • a second epitaxial layer is further disposed between the source region and the first epitaxial layer, and a doping type of the second epitaxial layer and a doping type of the source region Similarly, the doping concentration of the second epitaxial layer is greater than the doping concentration of the source region.
  • a method of fabricating a vertical tunneling field effect transistor includes the following steps:
  • the step of “forming a gate region and two drain regions on the first epitaxial layer” includes two steps: forming a gate dielectric layer sequentially on the second trench of the first epitaxial layer and a gate region, the gate dielectric layer isolating the gate region from the first epitaxial layer; and
  • a drain region is formed on each of the opposite sides of the first epitaxial layer outside the second trench, and the drain region is isolated from the gate region.
  • the step of “stabilizing a gate dielectric layer and a gate region on the second trench of the first epitaxial layer” when the step of “stabilizing a gate dielectric layer and a gate region on the second trench of the first epitaxial layer” is performed in the step “on the first epitaxial layer.
  • the step of "forming a gate dielectric layer and a gate region sequentially on the second trench of the first epitaxial layer” includes, before, respectively, forming a drain region at two opposite sides of the second trench. The following steps:
  • a gate dielectric layer and a gate region on all or a portion of opposite sides of the second trench of the first epitaxial layer are removed.
  • the step of “stabilizing a gate dielectric layer and a gate region on the second trench of the first epitaxial layer” when the step of “stabilizing a gate dielectric layer and a gate region on the second trench of the first epitaxial layer” is performed in the step “on the first epitaxial layer After forming a drain region respectively at two opposite sides of the second trench, the step of “stabilizing the gate dielectric layer and the gate region on the second trench of the first epitaxial layer” includes The following steps:
  • the surface of the first epitaxial layer and the two drain regions are covered with a gate dielectric material, and the covered gate dielectric material has a symmetrical step shape on both sides thereof, and forms a groove and a receiving groove; the groove Formed in the gate dielectric material of the second trench, the accommodating trench is formed between the two drain regions In the material, the groove is located at the bottom of the groove of the accommodating groove;
  • the gate dielectric material and the gate region material on the drain region are removed.
  • the step of “forming a gate region and two drain regions on the first epitaxial layer” further includes the steps of: forming a third trench on the gate region, The third groove is oriented in the same direction as the first groove opening;
  • the step of “forming a drain region at two opposite sides of the second trench outside the first trench on the first epitaxial layer” includes the following steps:
  • the drain region is formed on the channel layer.
  • the step of “forming a first trench on the source region material to prepare a source region” and the step “covering the first epitaxy on the source region Layer material, and forming a second trench on the first epitaxial layer material in the first trench to be prepared between the first epitaxial layers” the method for preparing the vertical tunneling field effect transistor The method includes the steps of: forming a second epitaxial layer on the source region, the doping type of the second epitaxial layer is the same as the doping type of the source region, and the doping concentration of the second epitaxial layer is greater than Doping concentration of the source region.
  • the current carrying electrons in the region where the first trench and the gate region of the source region overlap each other to the electric field of the gate region, and the first trench of the source region can be tunneled, that is, the first trench increases the overlapping area between the source region and the gate region, thereby increasing the tunneling area; the first epitaxial layer can form the gate region and the source region.
  • the tunneling type belongs to linear tunneling, and the electric field direction of the gate region and the electron tunneling direction of the source region are in a line, and the tunneling probability is large, thereby increasing the tunneling current.
  • FIG. 1 is a schematic cross-sectional view of a vertical tunneling field effect transistor according to a first embodiment of the present invention
  • FIG. 2 is an exploded cross-sectional view of the vertical tunneling field effect transistor of FIG. 1;
  • FIG. 3 is a flow chart of a method of fabricating the vertical tunneling field effect transistor of FIG. 1;
  • step S11 of the method for fabricating the vertical tunneling field effect transistor of FIG. 3;
  • FIG. 5 is a cross-sectional view corresponding to step S12 of the method for fabricating the vertical tunneling field effect transistor of FIG. 3;
  • step S13 is a flow chart of step S13 of the method for fabricating the vertical tunneling field effect transistor of FIG. 3;
  • step S133 of the method for fabricating the vertical tunneling field effect transistor of FIG. 6;
  • step S14 is a cross-sectional view corresponding to step S14 of the method for fabricating the vertical tunneling field effect transistor of FIG. 3;
  • step S15 of the method for fabricating the vertical tunneling field effect transistor of FIG. 3;
  • step S1511 is a cross-sectional view corresponding to step S1511 of the method for fabricating the vertical tunneling field effect transistor of FIG. 10;
  • Figure 12 is a cross-sectional view corresponding to step S1512 of the method of fabricating the vertical tunneling field effect transistor of Figure 10;
  • step S1514 of the method for fabricating the vertical tunneling field effect transistor of FIG. 10;
  • FIG. 14 and FIG. 15 are cross-sectional views corresponding to step S152 of the method for fabricating the vertical tunneling field effect transistor of FIG. 10;
  • step S16 is a cross-sectional view corresponding to step S16 of the method for fabricating the vertical tunneling field effect transistor of FIG. 3;
  • FIG. 17 is a cross-sectional view of a vertical tunneling field effect transistor according to a second embodiment of the present invention.
  • FIG. 18 is a schematic cross-sectional view of a vertical tunneling field effect transistor according to a third embodiment of the present invention.
  • Figure 19 is a flow chart showing the step S25 of the method of fabricating the vertical tunneling field effect transistor of Figure 18;
  • Figure 20 is a cross-sectional view corresponding to step S2511 of the method of fabricating the vertical tunneling field effect transistor of Figure 19;
  • 21 is a cross-sectional view corresponding to step S2513 of the method for fabricating the vertical tunneling field effect transistor of FIG. 19;
  • Figure 22 is a cross-sectional view corresponding to step S2515 of the method of fabricating the vertical tunneling field effect transistor of Figure 19;
  • step S2521 is a cross-sectional view corresponding to step S2521 of the method for fabricating the vertical tunneling field effect transistor of FIG. 19;
  • Figure 24 is a cross-sectional view corresponding to step S2522 of the method of fabricating the vertical tunneling field effect transistor of Figure 19;
  • Figure 25 is a cross-sectional view corresponding to step S2524 of the method of fabricating the vertical tunneling field effect transistor of Figure 19;
  • 26 is a schematic cross-sectional view of a vertical tunneling field effect transistor according to a fourth embodiment of the present invention.
  • the vertical tunneling field effect transistor includes a source region 1, a first epitaxial layer 2, a gate dielectric layer 3, a gate region 4, and two drain regions 5; the first epitaxial layer 2, the gate dielectric layer 3, and the gate region 4 are sequentially stacked on the source On area 1.
  • a first trench 11 is disposed on a surface of the source region 1 facing the first epitaxial layer 2; the first epitaxial layer 2 extends a second trench 21 is formed in the first trench, and a second trench 21 is formed in the first trench 11 and the openings of the two are oriented in the same direction; the first epitaxial layer 2 forms the gate region 4 and the source region 1 Between the channels.
  • the gate dielectric layer 3 and the gate region 4 are both disposed in the second trench 21.
  • the gate dielectric layer 3 is disposed on the first epitaxial layer 2, and the gate dielectric layer 3 isolates the gate region 4 from the first epitaxial layer 2.
  • Two drain regions 5 are respectively disposed at opposite sides of the second trench, and the drain region 5 is separated from the gate region 4; the first epitaxial layer 2 extends between the drain region 5 and the source region 1, and forms a drain region. 5 channel between source region 1.
  • the gate region 4 is located in the second trench 21, and the second trench 21 is formed in the first trench 11, so that the gate region 4 is in the first trench 11, and the first trench 11 and the gate of the source region 1 are
  • the currents in the overlapping regions of the region 4 all go to the electric field of the gate region 4, and the currents on the respective faces in the first trench of the source region 1 can be tunneled, that is, the first trench 11 is utilized.
  • the overlap area between the source region 1 and the gate region 4 is increased, thereby increasing the tunneling area; the first epitaxial layer 2 can form a channel between the gate region 4 and the source region 1, and the tunneling type belongs to linear tunneling, and the gate The electric field direction of the region 4 and the electron tunneling direction of the source region 1 are in a line, and the tunneling probability is large, thereby increasing the tunneling current.
  • the first epitaxial layer 2 as a channel between the drain region 5 and the source region 1, the channel can be eliminated, and the process steps can be reduced.
  • the source region 1 is an in-situ doped P+ type (P-type heavily doped) semiconductor layer, and the material thereof may be a silicon material, or may be a germanium, a germanium silicon material, a III-V material, or a III-V compound. Any of them.
  • the P+ type semiconductor layer may be formed by deposition or by implanting P+ type ions by an ion implantation process.
  • the P+ type impurity generally includes not limited to boron ions, boron fluoride ions, and the like.
  • the first epitaxial layer 2 is a doped N+ type (N-type heavily doped) semiconductor layer, and the material thereof may be silicon, germanium, germanium silicon, III-V material, etc., and the doping concentration may be undoped or Lightly doped.
  • N-type impurities generally include, but are not limited to, arsenic ions, phosphorus ions, and the like.
  • the first epitaxial layer 2 may form a p-n tunneling junction with the source region 1.
  • the gate dielectric layer 3 may be a high-k dielectric material, silicon oxide, HfSiON or other oxide material or the like which may function as an insulator to isolate the gate region 4 from the first epitaxial layer 2.
  • the material of the gate region 4 may be metal or polysilicon or the like.
  • the first trench 11 in the direction in which the source region 1 and the first epitaxial layer 2 are stacked, the first trench 11 has a rectangular cross section, and the second trench 21 has a rectangular cross section, thereby facilitating the source region 1 and the first epitaxy.
  • the etching of layer 2 to form first trench 11 and second trench 21 is convenient for fabrication.
  • the first trench 11 and the second trench 21 have the same cross section, which facilitates tunneling.
  • the cross section of the second groove 21 may be any of a triangular shape, a U shape, a trapezoid shape or the like.
  • the gate region 4 is provided with a third trench 40 formed on the surface of the gate region 4 away from the source region 1, and the third trench 40 is oriented the same as the opening of the first trench 11 through the third trench 40 can reduce the gate area 4 consumables and reduce the weight of the vertical tunneling field effect transistor.
  • the third trench 40 may not be disposed on the gate region 4.
  • the gate dielectric layer 3 and the gate region 4 are entirely located in the second trench 21 of the first epitaxial layer 2, and both the gate dielectric layer 3 and the gate region 4 are almost flush with the opening of the second trench 21. .
  • the drain region 5 is located outside the second trench 21, the edge of which is aligned with the opening edge of the second trench 21, and the lateral width of the drain region 5 coincides with the lateral width of the two portions of the first epitaxial layer 2, so that the first portion can be fully utilized.
  • the upper surface space of the epitaxial layer 2 facilitates the preparation of the drain region 5.
  • the drain region 5 is disposed outside the second trench 21, and the gate region 4 is disposed in the second trench 21 to isolate the drain region 5 from the gate region 4.
  • the vertical tunneling field effect transistor further includes a substrate 9 and an electrode contact structure, and the substrate 9 is disposed on the source region 1 away from the surface of the first epitaxial layer 2. Through the substrate 9, the entire vertical tunneling field effect transistor can be supported, and the processing of the source region 1 can be facilitated.
  • An electrode contact structure is respectively connected to the source region, the gate region and the drain region to form a source, a gate and a drain, respectively. Thereby, the electrical connection between the vertical tunneling field effect transistor and other components is realized.
  • each drain region 5 is formed with a drain 8 respectively.
  • the drain electrode 8 includes a metal post 82 and a side wall 81. The metal post 82 is connected to the drain region 5.
  • the side wall 81 is made of an insulating material and is surrounded by Around the metal column 82.
  • the electrode contact structure 8 can be the same as the electrode contact structure of the vertical tunneling field effect transistor in the prior art, and will not be described in further detail in the embodiments of the present invention.
  • FIG. 3 is a flowchart of a method for fabricating a vertical tunneling field effect transistor according to a first embodiment of the present invention.
  • the method of preparing the vertical tunneling field effect transistor includes, but is not limited to, the following steps.
  • a substrate 9 is provided.
  • the material of the substrate is silicon.
  • the substrate can be a rectangular substrate.
  • the substrate may also be a binary or ternary compound semiconductor of a group II-IV, or a group III-V, or a group IV-IV of germanium (Ge) or silicon germanium, gallium arsenide, or the like, and an insulating substrate. Any of silicon (Silicon on Insulator, SOI) or germanium on Insulator (GeOI) on an insulating substrate.
  • the P-type impurities herein generally include not limited to boron ions, boron fluoride ions, and the like.
  • Step S12 covering the source material 10 on the substrate 9, as shown in FIG. 5, in this embodiment,
  • An in-situ doped P+ type semiconductor layer is deposited on the substrate, and the material thereof may be a silicon material, or may be any one of a germanium, a germanium silicon material, a III-V material, or a III-V compound.
  • the source region can also be formed by implanting P+ ions by an ion implantation process, and at the same time, the doping ions need to be activated by an annealing process.
  • step S13 a first trench 11 is formed on the source material 10 to be prepared as the source region 1. As shown in FIG. 6, in the step S13, but not limited to the following sub-steps.
  • Step S131 depositing a first mask layer 101 on the source material 10 and etching the middle portion of the first mask layer to expose the central region of the source region.
  • the first mask layer is used to protect the surface of the source region covered by the first mask layer, and the etching liquid is prevented from affecting the source region under the first mask layer during etching.
  • the material of the first mask layer 21 may be, but not limited to, a silicon oxide material, silicon nitride, or silicon oxynitride or the like.
  • Step S132 etching a central region of the exposed source region by using the first mask layer as a mask, thereby forming a first trench.
  • step S133 the remaining first mask layer is removed to prepare a source region, as shown in FIG.
  • Step S14 covering the source region with the first epitaxial layer material, and forming a second trench 21 on the first epitaxial layer material in the first trench, the second trench 21 and the first trench
  • the openings of the grooves 11 are oriented the same to prepare a first epitaxial layer 2 as shown in FIG.
  • the first epitaxial layer is a doped semiconductor layer as a tunneling channel and a first epitaxial layer (pocket region), and the material thereof may be silicon, germanium, germanium silicon, III-V material, or the like.
  • the doping type is n-type, and the doping concentration may be undoped or lightly doped.
  • the first epitaxial layer can be formed by epitaxy, such as Chemical Vapor Deposition (CVD) technology, Molecular beam epitaxy (MBE) technology.
  • CVD Chemical Vapor Deposition
  • MBE Molecular beam epitaxy
  • step S14 first, a doped semiconductor layer covering the source region is formed, and the doped semiconductor layer covers the entire upper surface of the source region, and fills the first trench;
  • the semiconductor layer in the first trench is etched to form a second trench, thereby processing the semiconductor layer into a first epitaxial layer.
  • the specific etching manner of the second trench may be the same as that of the first trench, and details are not described herein again.
  • Step S15 forming a gate dielectric layer, a gate region and two drain regions on the first epitaxial layer. As shown in FIG. 10, it is the flowchart of step S15, and includes, but is not limited to, the following sub-steps in this step.
  • Step S151 sequentially forming a gate dielectric layer and a gate region on the second trench of the first epitaxial layer.
  • the gate dielectric layer isolates the gate region from the first epitaxial layer. This step further includes the following steps.
  • Step S1511 as shown in FIG. 11, the gate dielectric material 30 is covered on the entire surface of the first epitaxial layer, and a recess 31 is formed on the gate dielectric material in the second trench.
  • a gate dielectric material is overlaid on the entire upper surface of the first epitaxial layer, and the second trench is filled; then the gate dielectric material filled in the second trench is etched to form a recess.
  • the groove may be etched in the same manner as the first trench.
  • Step S1512 as shown in FIG. 12, the gate region material 40 is covered on the entire surface of the gate dielectric layer, and the gate region material 40 fills the recess.
  • Step S1513 removing the gate dielectric layer material 30 and the gate region material 40 on both opposite sides of the second trench of the first epitaxial layer 2, and exposing at two opposite sides of the second trench
  • the first epitaxial layer retains only the gate dielectric layer material and the gate region material located in the second trench 21, as shown in FIG. 13, thereby preparing a gate dielectric layer and a gate region.
  • the removal operation can be performed by setting a mask layer and etching.
  • Step S1514 as shown in FIG. 13, a third trench is disposed on the gate region, and the third trench is formed on a surface of the gate region away from the source region, and the third trench is oriented in the same direction as the first trench opening.
  • the third trench may be formed by providing a mask layer and etching.
  • Step S152 forming a drain region on the opposite sides of the first epitaxial layer outside the second trench, and the drain region is isolated from the gate region.
  • the entire upper surface of the first epitaxial layer 2, the gate dielectric layer 3, and the gate region 4 is covered with a second mask layer, and a portion of the second mask layer located at opposite sides of the second trench is removed.
  • a corresponding portion of the first epitaxial layer is exposed, such as the second mask layer 50 formed as shown in FIG.
  • a drain region 5 on the first epitaxial layer 2 is formed on both sides of the second mask layer 50, and finally the second mask layer 50 is removed, thereby forming a structure as shown in FIG.
  • ion implantation may be performed on the first epitaxial layer 2 to form the drain region 5; or, it may be provided to provide an in-situ doped N+ type silicon material over the first epitaxial layer 2, the gate dielectric layer 3, and the gate region 4.
  • the entire upper surface is then provided with a second mask layer overlying the N+ type silicon material, etching the intermediate portion of the second mask layer, and then etching the intermediate region of the N+ silicon material leaving the regions on both sides as drain regions.
  • Step S16 forming an electrode contact structure on the drain region, the source region, and the gate region respectively to form a drain, a source, and a gate correspondingly to obtain a complete vertical tunneling field effect transistor.
  • the drain, source and gate can be used to facilitate the electrical connection of the vertical tunneling field effect transistor to other components.
  • a schematic structural view of the drain 8 is formed on the drain region 5.
  • the sidewall material is first deposited on each of the drain regions 5, and the sidewall material may be silicon oxide, silicon nitride, high-k dielectric or other insulating material.
  • an argon ion beam etching is performed, and a through hole is etched at a center position of the sidewall to expose the drain region; and then cobalt (Co) and titanium nitride (TiN) ion beam precipitation is performed on the exposed drain region, followed by A rapid annealing process, followed by removal of titanium nitride and cobalt, and finally deposition of a passivation layer, opening contact holes and metallization, etc., forms a complete vertical tunneling field effect transistor.
  • the preparation method of the electrode contact structure in this step is similar to that in the prior art, and will not be specifically described in the embodiment of the present invention.
  • step S1514 may be omitted, that is, the third trench may not be disposed on the gate region.
  • step S1514 may be followed by step S1512, and may be in no particular order with other steps after step S1512.
  • the deposition process may be performed by low pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD) or the like.
  • LPCVD low pressure chemical vapor deposition
  • PVD physical vapor deposition
  • FIG. 17 is a vertical tunneling field effect transistor according to a second embodiment of the present invention.
  • the gate region 4a extends outside the second trench, and an extended portion 40a is formed to extend toward the drain region 5a, and a gate dielectric layer 3a is disposed between the expanded portion and the first epitaxial layer 2.
  • the tunneling area can be further increased by the extension portion to further increase the tunneling current.
  • the gate region 4a and the gate dielectric layer 3a extend to both side regions of the second trench on the first epitaxial layer 2a, the lateral widths of the two drain regions 5a are correspondingly reduced, and in order to prevent the drain region 5a from contacting the gate region 4a, the drain region 5a A gap is provided between the gate region 4a to isolate the two.
  • Other portions of the vertical tunneling field effect transistor in this embodiment are the same as those in the first embodiment, and are not described herein again.
  • the method for fabricating the vertical tunneling field effect transistor in the second embodiment differs from the method for fabricating the vertical tunneling field effect transistor in the first embodiment only in steps S1513 and S152, and the implementation of the other steps and the first implementation The method is the same and will not be described here.
  • step S1513 the gate dielectric layer material and the gate region material on the opposite sides of the second trench of the first epitaxial layer 2a are removed, and the gate dielectric layer material at the edge of the second trench is retained.
  • the gate region material that is, the expanded portion 40a of the gate region is formed, and the gate dielectric layer 3a is left between the expanded portion 40a and the first epitaxial layer 2.
  • step S152 the entirety of the first epitaxial layer 2a, the gate dielectric layer 3a, and the gate region 4a are shown. Covering the mask layer and removing portions of the mask layer at opposite sides of the second trench to expose the corresponding portion of the first epitaxial layer, and respectively remaining on both sides of the gate dielectric layer 3a and the gate region 4a A portion of the mask layer is formed to form a gap between the gate dielectric layer 3a and the drain region 5a.
  • FIG. 18 is a vertical tunneling field effect transistor according to a third embodiment of the present invention.
  • the gap between the drain region 5b and the gate region 4a is provided with an insulating material, which is separated by an insulating material, specifically, between the drain region 5b and the gate region 4a.
  • the gate dielectric layer 3a and the sidewall are provided, wherein the sidewall is made of an insulating material such as silicon nitride, and the sidewall is used to isolate the gate region 4a from the drain region 5a, and the entire gate dielectric layer 3a can be formed at one time, thereby facilitating the whole Preparation of vertical tunneling field effect transistors.
  • the drain region 5b and the gate region 4a may be filled with other insulating materials to isolate the two.
  • FIG. 19 is a flow chart of a method for fabricating a vertical tunneling field effect transistor according to a third embodiment, which includes, but is not limited to, the following steps.
  • step S21 a substrate 9b is provided.
  • Step S22 covering the source region material on the substrate.
  • step S23 a first trench is formed on the source region material to prepare a source region 1b.
  • Step S24 covering the source region with a first epitaxial layer material, and forming a second trench on the first epitaxial layer material in the first trench to prepare a first epitaxial layer 2b.
  • step S21 to the step S24 may be the same as the step S11 to the step S14 in the first embodiment of the vertical tunneling field effect transistor, and details are not described herein again.
  • Step S25 forming a gate dielectric layer 3b, a gate region 4b, and two drain regions 5b on the first epitaxial layer.
  • Figure 19 is a schematic flow chart of this step. In this step, including but not limited to the following sub-steps.
  • Step S251 forming a drain region 5b at two opposite sides of the first epitaxial layer outside the second trench. This step further includes the following steps.
  • step S2511 the entire upper surface of the first epitaxial layer 2b is covered with the drain region material 50b as shown in FIG.
  • a mask layer 52b is provided on the entire upper surface of the drain region material 50b.
  • Step S2513 removing a portion of the mask layer located in the lateral center region to expose a portion of the drain region material; the exposed drain region material has a lateral width greater than a lateral width of the second trench, as shown in FIG.
  • Step S2514 etching the exposed drain region material to expose a portion of the first epitaxial layer.
  • step S2515 the remaining mask layer 52b is removed, and the unetched drain region material portion forms the drain region 5b as shown in FIG.
  • Step S252 sequentially forming a gate dielectric layer and a gate region on the second trench of the first epitaxial layer 2b. This step further includes the following steps.
  • Step S2521 The surface of the first epitaxial layer 2b and the two drain regions are covered with a gate dielectric material 30b.
  • the covered gate dielectric material has a symmetrical step shape on both sides, and a recess 301 and a receiving recess 302 are formed.
  • the groove 301 is formed in the gate dielectric material of the second trench, and the accommodating groove 302 is formed in the gate dielectric material between the two drain regions 5b, and the groove 301 is located at the groove bottom of the accommodating groove 302.
  • step S2522 the gate region material 40b is covered on the entire upper surface of the gate dielectric material 30b, and the gate region material 40b fills the recess 301 and the accommodating trench 302. As shown in FIG. 24, the gate dielectric material can make the gate region material and the drain region. District isolation.
  • Step S2523 removing the gate dielectric material and the gate region material on the drain region.
  • Step S2524 removing a portion of the gate region material in the accommodating trench 302 and the recess 301 to form a third trench 41b on the gate region material, thereby preparing a formed gate region 4b and a gate dielectric layer 3b, such as Figure 25 shows.
  • the step S2524 can also be omitted.
  • Step S26 forming an electrode contact structure on the drain region, the source region, and the gate region respectively to form a drain, a source, and a gate correspondingly to obtain a complete vertical tunneling field effect transistor.
  • the drain, source and gate can be used to facilitate the electrical connection of the vertical tunneling field effect transistor to other components.
  • etching is performed at a side near the drain region to form a gap between the drain region and the gate dielectric layer, and a sidewall is prepared in the gap to isolate the drain region from the gate region. .
  • step S26 This step is the same as step S26 in the first embodiment, and details are not described herein again.
  • FIG. 26 is a vertical tunneling field effect transistor according to a fourth embodiment of the present invention.
  • a channel layer 6c is further disposed between the first epitaxial layer 2c and the drain region 5c, and a tunneling channel between the source region 1c and the drain region 5c can be formed by the channel layer 6c.
  • a gate dielectric layer is formed between the expanded portion 40c of the gate region 4c and the channel layer 6 to isolate the gate region 4c and the channel layer 6c, and the upper surface of the channel layer 6c is higher than the upper surface of the expanded portion 40c of the gate region 4c. Therefore, the gate region 4 and the drain region 5 can be isolated, and the processing of the drain region 5c can be facilitated.
  • a channel layer 6c is formed on the first epitaxial layer 2c, and a drain region is formed on the channel layer 6c.
  • a channel layer 6c is added between the epitaxial layer 2c and the drain region 5c.
  • a channel layer may be added between the first epitaxial layer and the drain region.
  • a channel layer may be added between the first epitaxial layer and the drain region.
  • the method further includes the step of: positioning on the first epitaxial layer. Forming a channel layer at two opposite sides of the second trench; forming the drain region on the channel layer.
  • a second epitaxial layer is further disposed between the source region and the first epitaxial layer, and a doping type of the second epitaxial layer and the source region are The doping type is the same, and the doping concentration of the second epitaxial layer is greater than the doping concentration of the source region.
  • a very steep concentration gradient can be formed on the source region, that is, a steep tunneling junction is formed between the source region and the first epitaxial layer, thereby increasing the tunneling probability and increasing the tunneling current.
  • a second epitaxial layer is first formed on the source region, and then the first epitaxial layer is formed.

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Abstract

提供一种垂直隧穿场效应晶体管及其制备方法。垂直隧穿场效应晶体管包括：源区（1）、第一外延层（2）、栅介质层（3）、栅区（4）及两个漏区（5）；源区上设有第一沟槽（11）；第一外延层上设有第二沟槽（21），第一外延层形成栅区与源区之间的隧穿沟道；栅介质层及栅区均设置于第二沟槽中；两个漏区分别设置在第二沟槽外的两相对侧处。源区的第一沟槽与栅区有重叠的区域内的载流电子均可以发生隧穿，即利用第一沟槽增加了源区与栅区之间的重叠面积，从而增加了隧穿面积；第一外延层可以形成栅区与源区之间的沟道，属于线性隧穿，栅区电场方向和源区的电子隧穿方向处于一条线上，隧穿几率大，从而提高了隧穿电流。

Description

垂直隧穿场效应晶体管及其制备方法
本申请要求于2015年1月04日提交中国专利局、申请号为201510003744.3、发明名称为“垂直隧穿场效应晶体管及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种垂直隧穿场效应晶体管及其制备方法。
背景技术
隧穿场效应晶体管(TFET)本质上为一个有栅控的反偏PIN二极管，其源区和漏区的掺杂类型不同。对于N型隧穿场效应晶体管(TFET)来说，其中，N型掺杂为漏区，工作时加正向偏置。P型掺杂为源端，工作时加负向偏置。与金属氧化物半导体场效应晶体管(MOSFET)相比，隧穿场效应晶体管(TFET)可以获得更小的亚阈值摆幅(SS)，因此隧穿场效应晶体管(TFET)很适合用于低功耗应用。
在隧穿场效应晶体管(TFET)中，输出电流随着漏端电压增大而增大的过程是通过漏端电压降在源端隧穿结处，非常有效的改变隧穿结隧穿宽度从而使输出隧穿电流增大实现。但是与传统的MOSFET相比较，隧穿电流小，因此改善隧穿场效应晶体管(TFET)的隧穿电流是一个非常重要的问题。
目前隧穿场效应晶体管(TFET)一般采用垂直隧穿，源区区域和沟道区域在栅区的作用下发生垂直隧穿，尽管这种方法可以增加隧穿几率，但现有技术中，由于源区与栅区之间的重叠区域有限，使得隧穿面积较小，因而隧穿电流较小。
发明内容
本发明提供一种垂直隧穿场效应晶体管及其制备方法，能够增加隧穿面积，有效提高隧穿电流。
一方面，提供了一种垂直隧穿场效应晶体管，所述垂直隧穿场效应晶体 管包括源区、第一外延层、栅介质层、栅区及两个漏区；所述第一外延层、所述栅介质层及所述栅区依次叠加于所述源区上；
所述源区上朝向所述第一外延层的表面设有第一沟槽；所述第一外延层上设有第二沟槽，所述第二沟槽形成于所述第一沟槽中，所述第二沟槽与所述第一沟槽的开口朝向相同；所述第一外延层形成所述栅区与所述源区之间的隧穿沟道；
所述栅介质层及栅区均设置于所述第二沟槽中；所述栅介质层设置于所述第一外延层上，所述栅介质层将所述栅区与所述第一外延层隔离；
两个所述漏区分别设置在所述第二沟槽外的两相对侧处，所述漏区与所述栅区相隔离；所述第一外延层延伸至所述漏区与所述源区之间，并形成所述漏区与所述源区之间的沟道。
在第一种可能的实现方式中，所述栅区延伸至所述第二沟槽外，并朝向所述漏区延伸形成有扩展部，所述扩展部与所述第一外延层之间设置有所述栅介质层。
在第二种可能的实现方式中，所述栅区的扩展部与所述漏区之间设有间隙；或者，
所述栅介质层延伸至所述栅区的扩展部与所述漏区之间，所述漏区与所述栅区通过绝缘材质相隔离。
在第三种可能的实现方式中，在所述源区与所述第一外延层的叠加方向上，所述第一沟槽与所述第二沟槽的截面形状相同。
结合第三种可能的实现方式，在第四种可能的实现方式中，所述第一沟槽的截面与所述第二沟槽的截面均为矩形。
在第五种可能的实现方式中，所述栅区上设有第三沟槽，所述第三沟槽与所述第一沟槽的开口朝向相同。
在第六种可能的实现方式中，所述漏区与所述第一外延层之间还设有沟道层。
在第七种可能的实现方式中，所述源区与所述第一外延层之间还设有第二外延层，所述第二外延层的掺杂类型与所述源区的掺杂类型相同，所述第二外延层的掺杂浓度大于所述源区的掺杂浓度。
另一方面，提供了一种垂直隧穿场效应晶体管的制备方法，所述垂直隧 穿场效应晶体管的制备方法包括以下步骤：
提供衬底；
在所述衬底上覆盖源区材料；
在所述源区材料上形成一第一沟槽，以制备成源区；
在所述源区上覆盖第一外延层材料，并在位于所述第一沟槽中的第一外延层材料上形成一第二沟槽，所述第二沟槽与所述第一沟槽的开口朝向相同，以制备成第一外延层；以及
在所述第一外延层上形成栅介质层、栅区及两个漏区；
所述步骤“在所述第一外延层上形成栅区及两个漏区”中包括不分先后的两个步骤：在所述第一外延层的第二沟槽上依次形成栅介质层及栅区，所述栅介质层将所述栅区与所述第一外延层隔离；以及，
在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区，所述漏区与所述栅区相隔离。
在第二种可能的实现方式中，当所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”在所述步骤“在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区”之前时，所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”包括以下步骤：
在所述第一外延层整体上表面覆盖栅介质材料，并在位于所述第二沟槽中的栅介质材料上形成一凹槽；
在所述栅区介质层整体上表面覆盖栅区材料，并使栅区材料将所述凹槽填充；
去除全部或部分位于所述第一外延层的第二沟槽的两个相对侧上的栅区介质层及栅区。
在第三种可能的实现方式中，当所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”在所述步骤“在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区”之后时，所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”包括以下步骤：
在所述第一外延层及两漏区的整体上表面覆盖栅介质材料，覆盖的所述栅介质材料两侧呈对称的阶梯状，并形成一凹槽及一容置槽；所述凹槽形成于所述第二沟槽的栅介质材料中，所述容置槽形成于两个所述漏区之间栅介 质材料中，所述凹槽位于容置槽的槽底；
在所述栅介质材料的整体上表面上覆盖栅区材料，所述栅区材料填充所述凹槽及所述容置槽；
移除位于所述漏区上的栅介质材料及栅区材料。
在第四种可能的实现方式中，在所述步骤“在所述第一外延层上形成栅区及两个漏区”中还包括步骤：在所述栅区上形成一第三沟槽，所述第三沟槽与所述第一沟槽开口朝向相同；
所述步骤“在所述栅区上形成一第三沟槽，所述第三沟槽与所述第一沟槽开口朝向相同”在所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”之后。
在第五种可能的实现方式中，在所述步骤“在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区”中包括以下步骤：
在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一沟道层；
在所述沟道层上形成所述漏区。
在第六种可能的实现方式中，在所述步骤“在所述源区材料上形成一第一沟槽，以制备成源区”与所述步骤“在所述源区上覆盖第一外延层材料，并在位于所述第一沟槽中的第一外延层材料上形成一第二沟槽，以制备成第一外延层”之间，所述垂直隧穿场效应晶体管的制备方法还包括步骤：在所述源区上形成一第二外延层，所述第二外延层的掺杂类型与所述源区的掺杂类型相同，所述第二外延层的掺杂浓度大于所述源区的掺杂浓度。
根据本发明的垂直隧穿场效应晶体管及其制备方法，源区的第一沟槽与栅区有重叠的区域内的载流电子都会都到栅区电场的作用，源区的第一沟槽内各个面上的载流电子均可以发生隧穿，即利用第一沟槽增加了源区与栅区之间的重叠面积，从而增加隧穿面积；第一外延层可以形成栅区与源区之间的沟道，隧穿类型属于线性隧穿，栅区电场方向和源区的电子隧穿方向处于一条线上，隧穿几率大，从而提高了隧穿电流。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用 的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施方式提供的垂直隧穿场效应晶体管的剖面示意图；
图2是图1的垂直隧穿场效应晶体管的分解剖面示意图；
图3是图1中垂直隧穿场效应晶体管的制备方法的流程图；
图4是图3中垂直隧穿场效应晶体管的制备方法的步骤S11对应的剖面图；
图5是图3中垂直隧穿场效应晶体管的制备方法的步骤S12对应的剖面图；
图6是图3中垂直隧穿场效应晶体管的制备方法的步骤S13的流程图；
图7是图6中垂直隧穿场效应晶体管的制备方法的步骤S131对应的剖面图；
图8是图6中垂直隧穿场效应晶体管的制备方法的步骤S133对应的剖面图；
图9是图3中垂直隧穿场效应晶体管的制备方法的步骤S14对应的剖面图；
图10是图3中垂直隧穿场效应晶体管的制备方法的步骤S15的流程图；
图11是图10中垂直隧穿场效应晶体管的制备方法的步骤S1511对应的剖面图；
图12是图10中垂直隧穿场效应晶体管的制备方法的步骤S1512对应的剖面图；
图13是图10中垂直隧穿场效应晶体管的制备方法的步骤S1514对应的剖面图；
图14及图15是图10中垂直隧穿场效应晶体管的制备方法的步骤S152对应的剖面图；
图16是图3中垂直隧穿场效应晶体管的制备方法的步骤S16对应的剖面图；
图17是本发明第二实施方式提供的垂直隧穿场效应晶体管的剖面示意 图；
图18是本发明第三实施方式提供的垂直隧穿场效应晶体管的剖面示意图；
图19是图18中垂直隧穿场效应晶体管的制备方法的步骤S25的流程图；
图20是图19中垂直隧穿场效应晶体管的制备方法的步骤S2511对应的剖面图；
图21是图19中垂直隧穿场效应晶体管的制备方法的步骤S2513对应的剖面图；
图22是图19中垂直隧穿场效应晶体管的制备方法的步骤S2515对应的剖面图；
图23是图19中垂直隧穿场效应晶体管的制备方法的步骤S2521对应的剖面图；
图24是图19中垂直隧穿场效应晶体管的制备方法的步骤S2522对应的剖面图；
图25是图19中垂直隧穿场效应晶体管的制备方法的步骤S2524对应的剖面图；
图26是本发明第四实施方式提供的垂直隧穿场效应晶体管的剖面示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1及图2，为本发明第一较佳实施方式提供的垂直隧穿场效应晶体管的剖面结构示意图。垂直隧穿场效应晶体管包括源区1、第一外延层2、栅介质层3、栅区4及两个漏区5；第一外延层2、栅介质层3及栅区4依次叠加于源区1上。
源区1上朝向第一外延层2的表面设有第一沟槽11；第一外延层2延伸 至第一沟槽中并形成有第二沟槽21，第二沟槽21形成于第一沟槽11中，且二者的开口朝向相同；第一外延层2形成栅区4与源区1之间的沟道。栅介质层3及栅区4均设置于第二沟槽21中。栅介质层3设置于第一外延层2上，栅介质层3将栅区4与第一外延层2隔离。两个漏区5分别设置在第二沟槽外的两相对侧处，漏区5与栅区4相隔离；第一外延层2延伸至漏区5与源区1之间，并形成漏区5与源区1之间的沟道。
栅区4位于第二沟槽21中，且第二沟槽21形成于第一沟槽11中，可以使得栅区4处于第一沟槽11中，源区1的第一沟槽11与栅区4有重叠的区域内的载流电子都会都到栅区4电场的作用，源区1的第一沟槽内各个面上的载流电子均可以发生隧穿，即利用第一沟槽11增加了源区1与栅区4之间的重叠面积，从而增加隧穿面积；第一外延层2可以形成栅区4与源区1之间的沟道，隧穿类型属于线性隧穿，栅区4电场方向和源区1的电子隧穿方向处于一条线上，隧穿几率大，从而提高了隧穿电流。同时，利用第一外延层2作为漏区5与源区1之间的沟道，可以不再制备沟道，减少工艺步骤。
源区1为原位掺杂的P+型(P型重掺杂)半导体层，其材料可以硅材料，也可以是锗、锗硅材料、III-V族材料、或III-V族化合材料等中的任意一种。P+型半导体层可以沉积形成、或者通过离子注入工艺注入P+型离子形成。P+型杂质一般包括先不限于硼离子、氟化硼离子等等。
第一外延层2为本证掺杂的N+型(N型重掺杂)半导体层，其材料可以是硅、锗、锗硅、III-V族材料等，掺杂浓度可以是未掺杂或轻掺杂。N型杂质一般包括但不限于砷离子、磷离子等等。第一外延层2可以与源区1形成一个p-n隧穿结。
栅介质层3可以是高K电介质材料、硅氧化物、HfSiON或者其他氧化物材料等，其可以起到绝缘作用，以将栅区4与第一外延层2隔离。栅区4的材料可以是金属或者多晶硅等。
本实施例中，在源区1与第一外延层2的叠加方向上，第一沟槽11的截面为矩形，第二沟槽21的截面为矩形，从而利于对源区1及第一外延层2的蚀刻以形成第一沟槽11及第二沟槽21，方便制备。第一沟槽11与第二沟槽21的截面相同，可以利于隧穿。当然，在其他的实施方式中，第一沟槽 11、第二沟槽21的截面也可以是三角形、U形、梯形等形状中的任一种。
栅区4上设有第三沟槽40，第三沟槽40形成于栅区4上远离源区1的表面，第三沟槽40与第一沟槽11开口朝向相同，通过第三沟槽40可以减少栅区4耗材，减轻垂直隧穿场效应晶体管的重量。此处，在其他的实施方式中，栅区4上也可以不设置第三沟槽40。
本实施例中，栅介质层3与栅区4整体位于第一外延层2的第二沟槽21中，栅介质层3与栅区4二者与第二沟槽21的开口处几乎平齐。漏区5位于第二沟槽21外，其边缘与第二沟槽21的开口边缘对齐，漏区5的横向宽度与第一外延层2两侧部位的横向宽度一致，从而可以充分利用第一外延层2的上表面空间，利于漏区5的制备。漏区5设置在第二沟槽21外，而栅区4设置在第二沟槽21中，可以使得漏区5与栅区4相隔离。
进一步，垂直隧穿场效应晶体管还包括衬底9及电极接触结构，衬底9设置在源区1上远离第一外延层2的表面处。通过衬底9可对整个垂直隧穿场效应晶体管起到支撑作用，且方便源区1的加工制备。源区、栅区及漏区上均分别对应连接有电极接触结构，以分别形成源极、栅极及漏极。从而实现垂直隧穿场效应晶体管与其他元器件的电连接。如图1所示，各漏区5上分别形成有一漏极8，漏极8包括金属柱82及边墙81，金属柱82连接至漏区5，边墙81为绝缘材质制成且包围在金属柱82周围。电极接触结构8可以与现有技术中垂直隧穿场效应晶体管的电极接触结构相同，本发明实施方式中不再进一步详细描述。
请参阅图3，为本发明提供的第一实施方式的垂直隧穿场效应晶体管的制备方法的流程图。垂直隧穿场效应晶体管的制备方法包括但不限于如下步骤。
步骤S11，提供一衬底9。本实施例中，所述衬底的材质为硅。如图4所示，衬底可为矩形衬底。在其他实施方式中，衬底也可以为锗(Ge)或硅锗、镓砷等II-IV族、或III-V族、或IV-IV族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator,SOI)、或者绝缘衬底上的锗(Germanium on Insulator,GeOI)中的任意一种。此处的P型杂质一般包括先不限于硼离子、氟化硼离子等等。
步骤S12，在衬底9上覆盖源区材料10，如图5所示，本实施方式中， 在衬底上沉积原位掺杂的P+型半导体层，其材料可以硅材料，也可以是锗、锗硅材料、III-V族材料、或III-V族化合材料等中的任意一种。当然，在其他实施方式中，也可以通过离子注入工艺注入P+型离子形成所述源区，同时，需要通过退火工艺来激活掺杂的离子。
步骤S13，在源区材料10上形成一第一沟槽11，以制备成源区1。如图6所示，在所述步骤S13中，包括但不仅限于以下子步骤。
步骤S131，如图7所示，在源区材料10上沉积一层第一掩膜层101，并刻蚀该第一掩膜层的中部，以露出源区的中心区域。第一掩膜层用于保护第一掩膜层覆盖的源区表面，防止刻蚀时，刻蚀液体对第一掩膜层下方的源区产生影响。所述第一掩膜层21的材料可以为但不局限于氧化硅材料、氮化硅、或氮氧化硅等。
步骤S132，以第一掩膜层为掩膜，刻蚀露出的源区的中心区域，从而形成第一沟槽。
步骤S133，去除余下的第一掩膜层，从而制备成源区，如图8所示。
步骤S14，在所述源区上覆盖第一外延层材料，并在位于所述第一沟槽中的第一外延层材料上形成一第二沟槽21，第二沟槽21与第一沟槽11的开口朝向相同，以制备成第一外延层2，如图9所示。具体地，第一外延层为本证掺杂的半导体层，以作为隧穿沟道及第一外延层(pocket区域)，其材料可以是硅、锗、锗硅、III-V族材料等，掺杂类型为n型，掺杂浓度可以是未掺杂或轻掺杂。第一外延层可用外延的方式形成，比如化学气相沉积(Chemical Vapor Deposition，CVD)技术，分子束外延(Molecular beam epitaxy，MBE)技术。
在步骤S14中，首先，形成覆盖在源区上的本证掺杂的半导体层，本证掺杂的半导体层覆盖于源区的整体上表面，并将第一沟槽填充；然后将填充于第一沟槽中的半导体层进行刻蚀形成第二沟槽，从而将半导体层加工成第一外延层。该第二沟槽的具体刻蚀方式可以与第一沟槽的刻蚀方式相同，此处不再赘述。
步骤S15，在所述第一外延层上形成栅介质层、栅区及两个漏区。如图10所示，为步骤S15的流程图，在该步骤中，包括但不仅限于以下子步骤。
步骤S151，在所述第一外延层的第二沟槽上依次形成栅介质层及栅区， 所述栅介质层将所述栅区与所述第一外延层隔离。该步骤进一步包括以下步骤。
步骤S1511，如图11所示，在所述第一外延层整体上表面覆盖栅介质材料30，并在位于所述第二沟槽中的栅介质材料上形成一凹槽31。
在本步骤中，首先，将栅介质材料覆盖于第一外延层的整体上表面，并将第二沟槽填充；然后将填充于第二沟槽中的栅介质材料进行刻蚀形成凹槽。该凹槽的具体刻蚀方式可以与第一沟槽的刻蚀方式相同。
步骤S1512，如图12所示，在所述栅区介质层整体上表面覆盖栅区材料40，并使栅区材料40将所述凹槽填充。
步骤S1513，去除全部位于所述第一外延层2的第二沟槽的两个相对侧上的栅区介质层材料30及栅区材料40，并露出位于第二沟槽的两个相对侧处的第一外延层，仅保留位于第二沟槽21内的栅区介质层材料及栅区材料，如图13所示，从而制备成栅区介质层及栅区。本步骤中可以通过设置掩膜层及刻蚀的方式进行去除作业。
步骤S1514，如图13所示，在栅区上设置第三沟槽，第三沟槽形成于栅区上远离源区的表面，第三沟槽与第一沟槽开口朝向相同。此处，亦可以通过设置掩膜层及刻蚀的方式形成第三沟槽。
步骤S152，在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区，漏区与所述栅区相隔离。首先，在第一外延层2、栅介质层3及栅区4的整体上表面覆盖第二掩膜层，并将第二掩膜层位于第二沟槽相对的两侧处的部分移除，露出相应部分的第一外延层，如图14形成的第二掩膜层50。然后，再在第二掩膜层50的两侧分别形成一位于第一外延层2上的漏区5，最后在移除第二掩膜层50，从而形成如图15所示结构。此处，可以在第一外延层2上进行离子注入形成漏区5；或者，也可以是，提供原位掺杂N+型硅材料覆盖在第一外延层2、栅介质层3及栅区4的整体上表面，然后提供第二掩膜层覆盖N+型硅材料上，刻蚀第二掩膜层中间区域，然后再刻蚀N+硅材料中间区域，留下两侧的区域为漏区。
步骤S16，分别在漏区、源区、栅区上形成电极接触结构，以对应形成漏极、源极及栅极，得到完整的垂直隧穿场效应晶体管。利用漏极、源极及栅极，可以便于使垂直隧穿场效应晶体管与其他元件实现电连接。
如图16所示，为在漏区5上形成漏极8的结构示意图。本步骤中，首先在各漏区5上分别沉积边墙材料，边墙材料可以是硅氧化物、氮化硅、高K电介质或者其他绝缘材料。然后进行氩离子束刻蚀，在边墙的中心位置刻蚀出通孔，以露出漏区；再在露出的漏区上进行钴(Co)和氮化钛(TiN)离子束沉淀，接着进行快速退火工艺，然后去除氮化钛和钴，最后进行沉积钝化层，开接触孔以及金属化等等，形成完整的垂直隧穿场效应晶体管。本步骤中的电极接触结构的制备方法与现有技术中类似，本发明实施方式中不再进行具体描述。
在本实施方式垂直隧穿场效应晶体管的制备方法中，步骤S1514可以省略，即栅区上可以不设置第三沟槽。此外，在其他的实施方式中，步骤S1514只要位于步骤S1512之后即可，与步骤S1512之后的其他步骤之间可以不分先后次序。
在本实施方式垂直隧穿场效应晶体管的制备方法中，沉积工艺可以通过低压化学气相沉积(LPCVD)或者物理气相沉积(PVD)等实现。
请参阅图17，为本发明第二实施方式提供的垂直隧穿场效应晶体管。本实施方式中，栅区4a延伸至所述第二沟槽外，并朝向漏区5a延伸形成有扩展部40a，扩展部与第一外延层2之间设置有栅介质层3a。通过扩展部可以进一步增加隧穿面积，从而进一步提高隧穿电流。
由于栅区4a及栅介质层3a延伸至第一外延层2a上第二沟槽的两侧区域，两漏区5a的横向宽度相应缩小，为了避免漏区5a与栅区4a接触，漏区5a与栅区4a之间设有间隙，从而使二者相隔离。本实施方式中的垂直隧穿场效应晶体管其他部分与第一实施方式相同，在此不再赘述。
第二实施方式中的垂直隧穿场效应晶体管的制备方法与第一实施方式中的垂直隧穿场效应晶体管的制备方法的区别仅在于步骤S1513及步骤S152，其他步骤的实施方式与第一实施方式相同，在此不再赘述。
在步骤S1513中，去除部分位于第一外延层2a的第二沟槽的两个相对侧上的栅区介质层材料及栅区材料，保留位于第二沟槽边缘处的栅区介质层材料及栅区材料，即可形成栅区的扩展部40a，并使得扩展部40a与第一外延层2之间保留有栅介质层3a。
在步骤S152中，在第一外延层2a、栅介质层3a及栅区4a的整体上表 面覆盖掩膜层，并将掩膜层位于第二沟槽相对的两侧处的部分移除，露出相应部分的第一外延层，且在栅介质层3a与栅区4a的两侧分别保留部分掩膜层，以便形成栅介质层3a与漏区5a之间的间隙。
请参阅图18，为本发明第三实施方式提供的垂直隧穿场效应晶体管。本实施方式与第二实施方式的区别仅在于，漏区5b与栅区4a之间的间隙中设置有绝缘材质，二者通过绝缘材质相隔离，具体地，漏区5b与栅区4a之间设有栅介质层3a及边墙，其中边墙为氮化硅等绝缘材料制备，利用边墙以使得栅区4a与漏区5a相隔离，整个栅介质层3a可以一次制备成型，从而便于整个垂直隧穿场效应晶体管的制备。此处，作为另外的实施方式，漏区5b与栅区4a之间亦可填充其他绝缘材质已将二者隔离。
如图19所示，为第三实施方式提供的垂直隧穿场效应晶体管的制备方法流程图，该制备方法包括但不限于如下步骤。
步骤S21，提供一衬底9b。
步骤S22，在衬底上覆盖源区材料。
步骤S23，在源区材料上形成一第一沟槽，以制备成源区1b。
步骤S24，在所述源区上覆盖第一外延层材料，并在位于所述第一沟槽中的第一外延层材料上形成一第二沟槽，以制备成第一外延层2b。
步骤S21至步骤S24的具体实施方式可以与垂直隧穿场效应晶体管的第一实施方式中步骤S11至步骤S14相同，在此不再赘述。
步骤S25，在所述第一外延层上形成栅介质层3b、栅区4b及两个漏区5b。如图19所示本步骤的流程示意图。在该步骤中，包括但不仅限于以下子步骤。
步骤S251，在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区5b。该步骤进一步包括以下步骤。
步骤S2511，在第一外延层2b的整体上表面覆盖漏区材料50b，如图20所示。
步骤S2512，在漏区材料50b的整体上表面设置掩膜层52b。
步骤S2513，移除位于横向中心区域的部分掩膜层，露出部分漏区材料；露出的漏区材料横向宽度大于第二沟槽的横向宽度，如图21所示。
步骤S2514，刻蚀所述露出的漏区材料，以露出部分第一外延层。
步骤S2515，移除其余的掩膜层52b，未被刻蚀的漏区材料部分形成漏区5b，如图22所示。
由于位于横向中心区域的部分掩膜层被移除，刻蚀时仅漏区材料的两侧处存在掩膜层，使得漏区材料横向的中间部位被刻蚀，从而在横向的两侧处分别形成一漏区，位于第一外延层上的两个漏区制备完成。
步骤S252，在所述第一外延层2b的第二沟槽上依次形成栅介质层及栅区。该步骤进一步包括以下步骤。
步骤S2521，在所述第一外延层2b及两漏区的整体上表面覆盖栅介质材料30b，覆盖的栅介质材料两侧呈对称的阶梯状，并形成一凹槽301及一容置槽302。凹槽301形成于第二沟槽的栅介质材料中，容置槽302形成于两个漏区5b之间栅介质材料中，凹槽301位于容置槽302的槽底。
步骤S2522，在栅介质材料30b的整体上表面上覆盖栅区材料40b，栅区材料40b填充凹槽301及容置槽302，如图24所示，可以使得栅介质材料将栅区材料与漏区隔离。
步骤S2523，移除位于漏区上的栅介质材料及栅区材料。
步骤S2524，移除部分位于容置槽302及凹槽301中的栅区材料，以在栅区材料上形成第三沟槽41b，从而制备形成成型的栅区4b及栅区介质层3b，如图25所示。此处，在其他的实施方式中，该步骤S2524亦可以省去。
步骤S26，分别在漏区、源区、栅区上形成电极接触结构，以对应形成漏极、源极及栅极，得到完整的垂直隧穿场效应晶体管。利用漏极、源极及栅极，可以便于使垂直隧穿场效应晶体管与其他元件实现电连接。在制备漏极时，将漏区靠近栅极的一侧处进行刻蚀，使漏区与栅介质层之间形成间隙，并在该间隙中制备边墙，以使得漏区与栅区相隔离。
该步骤与第一实施方式中的步骤S26相同，此处不再赘述。
请参阅图26，为本发明第四实施方式提供的垂直隧穿场效应晶体管。本实施方式中，第一外延层2c与漏区5c之间还设置有沟道层6c，利用该沟道层6c可以形成源区1c与漏区5c之间的隧穿沟道。栅区4c的扩展部40c与沟道层6之间形成有栅介质层，以将栅区4c及沟道层6c隔离，沟道层6c的上表面高于栅区4c的扩展部40c上表面，从而可以使得栅区4与漏区5相隔离，同时利于漏区5c的加工制备。本实施方式的垂直隧穿场效应晶体 管其他部分与第二实施方式相同，在此不再赘述。该垂直隧穿场效应晶体管制备过程中，需在制备漏区5c之前，先在第一外延层2c上制备形成沟道层6c，再在沟道层6c上制备漏区，从而便可在第一外延层2c与漏区5c之间增加沟道层6c。
此处，在第一实施方式或第二实施方式的垂直隧穿场效应晶体管中，第一外延层与漏区之间亦可增加一沟道层。如在第一实施方式垂直隧穿场效应晶体管中，第一外延层与漏区之间亦可增加一沟道层，则步骤S152中，具体包括以下步骤：在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一沟道层；在所述沟道层上形成所述漏区。
在上述四种实施方式的垂直隧穿场效应晶体管中，源区与所述第一外延层之间还设有第二外延层，所述第二外延层的掺杂类型与所述源区的掺杂类型相同，所述第二外延层的掺杂浓度大于所述源区的掺杂浓度。这样可以源区上形成一个非常陡峭的浓度梯度，即源区与第一外延层之间形成一个陡峭的隧穿结，进而可以增大隧穿几率，提高隧穿电流。该垂直隧穿场效应晶体管在制备过程中，在制备第一外延层之前，首先在源区上制备成型第二外延层，再制备形成第一外延层即可。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (15)

  1. 一种垂直隧穿场效应晶体管，其特征在于，所述垂直隧穿场效应晶体管包括源区、第一外延层、栅介质层、栅区及两个漏区；所述第一外延层、所述栅介质层及所述栅区依次叠加于所述源区上；
    所述源区上朝向所述第一外延层的表面设有第一沟槽；所述第一外延层上设有第二沟槽，所述第二沟槽形成于所述第一沟槽中，所述第二沟槽与所述第一沟槽的开口朝向相同；所述第一外延层形成所述栅区与所述源区之间的沟道；
    所述栅介质层及栅区均设置于所述第二沟槽中；所述栅介质层设置于所述第一外延层上，所述栅介质层将所述栅区与所述第一外延层隔离；
    两个所述漏区分别设置在所述第二沟槽外的两相对侧处，所述漏区与所述栅区相隔离；所述第一外延层延伸至所述漏区与所述源区之间，并形成所述漏区与所述源区之间的沟道。
  2. 如权利要求1所述的垂直隧穿场效应晶体管，其特征在于，所述栅区延伸至所述第二沟槽外，并朝向所述漏区延伸形成有扩展部，所述扩展部与所述第一外延层之间设置有所述栅介质层。
  3. 如权利要求1所述的垂直隧穿场效应晶体管，其特征在于，所述栅区的扩展部与所述漏区之间设有间隙；或者，
    所述栅介质层延伸至所述栅区的扩展部与所述漏区之间，所述漏区与所述栅区通过绝缘材质相隔离。
  4. 如权利要求1所述的垂直隧穿场效应晶体管，其特征在于，在所述源区与所述第一外延层的叠加方向上，所述第一沟槽与所述第二沟槽的截面形状相同。
  5. 如权利要求4所述的垂直隧穿场效应晶体管，其特征在于，所述第一沟槽的截面与所述第二沟槽的截面均为矩形。
  6. 如权利要求1所述的垂直隧穿场效应晶体管，其特征在于，所述栅区上设有第三沟槽，所述第三沟槽与所述第一沟槽的开口朝向相同。
  7. 如权利要求1所述的垂直隧穿场效应晶体管，其特征在于，所述漏区与所述第一外延层之间还设有沟道层。
  8. 如权利要求1所述的垂直隧穿场效应晶体管，其特征在于，所述源区 与所述第一外延层之间还设有第二外延层，所述第二外延层的掺杂类型与所述源区的掺杂类型相同，所述第二外延层的掺杂浓度大于所述源区的掺杂浓度。
  9. 一种垂直隧穿场效应晶体管的制备方法，其特征在于，包括以下步骤：
    提供衬底；
    在所述衬底上覆盖源区材料；
    在所述源区材料上形成一第一沟槽，以制备成源区；
    在所述源区上覆盖第一外延层材料，并在位于所述第一沟槽中的第一外延层材料上形成一第二沟槽，所述第二沟槽与所述第一沟槽的开口朝向相同，以制备成第一外延层；以及
    在所述第一外延层上形成栅介质层、栅区及两个漏区；
    所述步骤“在所述第一外延层上形成栅区及两个漏区”中包括不分先后的两个步骤：在所述第一外延层的第二沟槽上依次形成栅介质层及栅区，所述栅介质层将所述栅区与所述第一外延层隔离；以及，
    在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区，所述漏区与所述栅区相隔离。
  10. 根据权利要求9所述的垂直隧穿场效应晶体管的制备方法，其特征在于，所述步骤“在所述源区材料上形成一第一沟槽，以制备成源区”中包括以下步骤：
    在源区材料上沉积一层第一掩膜层，并刻蚀该第一掩膜层的中部，以露出源区的中心区域；
    以第一掩膜层为掩膜，刻蚀露出的源区的中心区域，从而形成第一沟槽；
    去除余下的第一掩膜层，从而制备成源区。
  11. 根据权利要求9所述的垂直隧穿场效应晶体管的制备方法，其特征在于，当所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”在所述步骤“在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区”之前时，所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”包括以下步骤：
    在所述第一外延层整体上表面覆盖栅介质材料，并在位于所述第二沟槽中的栅介质材料上形成一凹槽；
    在所述栅区介质层整体上表面覆盖栅区材料，并使栅区材料将所述凹槽填充；
    去除全部或部分位于所述第一外延层的第二沟槽的两个相对侧上的栅区介质层及栅区。
  12. 根据权利要求9所述的垂直隧穿场效应晶体管的制备方法，其特征在于，当所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”在所述步骤“在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区”之后时，所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”包括以下步骤：
    在所述第一外延层及两漏区的整体上表面覆盖栅介质材料，覆盖的所述栅介质材料两侧呈对称的阶梯状，并形成一凹槽及一容置槽；所述凹槽形成于所述第二沟槽的栅介质材料中，所述容置槽形成于两个所述漏区之间栅介质材料中，所述凹槽位于容置槽的槽底；
    在所述栅介质材料的整体上表面上覆盖栅区材料，所述栅区材料填充所述凹槽及所述容置槽；
    移除位于所述漏区上的栅介质材料及栅区材料。
  13. 根据权利要求9所述的垂直隧穿场效应晶体管的制备方法，其特征在于，在所述步骤“在所述第一外延层上形成栅区及两个漏区”中还包括步骤：在所述栅区上形成一第三沟槽，所述第三沟槽与所述第一沟槽开口朝向相同；
    所述步骤“在所述栅区上形成一第三沟槽，所述第三沟槽与所述第一沟槽开口朝向相同”在所述步骤“在所述第一外延层的第二沟槽上依次形成栅介质层及栅区”之后。
  14. 根据权利要求9所述的垂直隧穿场效应晶体管的制备方法，其特征在于，在所述步骤“在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一漏区”中包括以下步骤：
    在所述第一外延层上位于所述第二沟槽外的两个相对侧处分别形成一沟道层；
    在所述沟道层上形成所述漏区。
  15. 根据权利要求9所述的垂直隧穿场效应晶体管的制备方法，其特征 在于，在所述步骤“在所述源区材料上形成一第一沟槽，以制备成源区”与所述步骤“在所述源区上覆盖第一外延层材料，并在位于所述第一沟槽中的第一外延层材料上形成一第二沟槽，以制备成第一外延层”之间，所述垂直隧穿场效应晶体管的制备方法还包括步骤：在所述源区上形成一第二外延层，所述第二外延层的掺杂类型与所述源区的掺杂类型相同，所述第二外延层的掺杂浓度大于所述源区的掺杂浓度。
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