CN113053994A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN113053994A
CN113053994A CN202010798546.1A CN202010798546A CN113053994A CN 113053994 A CN113053994 A CN 113053994A CN 202010798546 A CN202010798546 A CN 202010798546A CN 113053994 A CN113053994 A CN 113053994A
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Prior art keywords
insulating film
electrode
semiconductor
section
layer
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CN202010798546.1A
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Inventor
岸本裕幸
加藤浩朗
西口俊史
下村纱矢
富田幸太
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication of CN113053994A publication Critical patent/CN113053994A/zh
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Abstract

实施方式涉及半导体装置及其制造方法。半导体装置具备：半导体部、设置于半导体部的背面上的第一电极、设置于半导体部的表面上的第二电极、以及控制电极，在半导体部与第二电极之间配置于设置于半导体部的沟槽的内部，通过第一绝缘膜与半导体部电绝缘，通过第二绝缘膜与第二电极电绝缘。控制电极包括设置于从第一绝缘膜以及第二绝缘膜分离的位置的第三绝缘膜。半导体部包括第一导电型的第一半导体层、第二导电型的第二半导体层、以及第一导电型的第三半导体层。第一层在第一电极与第二电极之间延伸。第二层设置于第一层与第二电极之间。第三层选择性地设置于第二层与第二电极之间。

Description

半导体装置及其制造方法
关联申请
本申请享受以日本专利申请2019-238876号(申请日：2019年12月27日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
实施方式涉及半导体装置及其制造方法。
背景技术
在沟槽栅极型MOS晶体管中，有时设置于栅极沟槽内的栅极电极包含孔隙，使晶体管特性劣化。
发明内容
实施方式提供一种能够抑制由栅极电极中的空隙引起的晶体管特性的劣化的半导体装置及其制造方法。
实施方式的半导体装置具备：半导体部、设置于所述半导体部的背面上的第一电极、设置于所述半导体部的表面上的第二电极、以及控制电极，在所述半导体部与所述第二电极之间配置于设置于所述半导体部的沟槽的内部，通过第一绝缘膜与所述半导体部电绝缘，通过第二绝缘膜与所述第二电极电绝缘。所述半导体部包括第一导电型的第一半导体层、第二导电型的第二半导体层、以及所述第一导电型的第三半导体层。所述控制电极位于所述第一半导体层与所述第二电极之间。所述第二半导体层设置于所述第一半导体层与所述第二电极之间，隔着所述第一绝缘膜与所述控制电极相对。所述第三半导体层选择性地设置于所述第二半导体层与所述第二电极之间，配置于与所述第一绝缘膜接触的位置，与所述第二电极电连接。所述控制电极包括设置于从所述第一绝缘膜以及所述第二绝缘膜分离的位置的第三绝缘膜。
附图说明
图1是表示第一实施方式的半导体装置的示意剖视图。
图2的(a)～图7的(b)是表示第一实施方式的半导体装置的制造过程的示意剖视图。
图8的(a)～(c)是表示第一实施方式的变形例的制造过程的示意剖视图。
图9的(a)及(b)是表示第一实施方式的变形例的半导体装置的示意剖视图。
图10是表示第二实施方式的半导体装置的示意剖视图。
图11的(a)～图12的(c)是表示第二实施方式的制造过程的示意剖视图。
图13的(a)及(b)是表示第二实施方式的变形例的半导体装置的示意剖视图。
具体实施方式
以下，参照附图对实施方式进行说明。对附图中的相同部分标注相同附图标记并适当省略其详细说明，对不同的部分进行说明。另外，附图是示意性或概念性的，各部分的厚度与宽度的关系、部分间的大小的比率等不一定与现实相同。另外，即使在表示相同的部分的情况下，也存在根据附图而相互的尺寸、比率不同地表示的情况。
并且，使用各图中所示的X轴、Y轴以及Z轴对各部分的配置以及构成进行说明。X轴、Y轴、Z轴相互正交，分别表示X方向、Y方向、Z方向。另外，有时将Z方向作为上方、将其相反方向作为下方进行说明。
(第一实施方式)
图1是表示第一实施方式的半导体装置1的示意剖视图。半导体装置1例如是沟槽栅极型MOS晶体管。
如图1所示，半导体装置1具备半导体部10、第一电极(以下，为漏极电极20)、第二电极(以下，为源极电极30)、栅极电极40以及场板电极(以下，为FP电极50)。
半导体部10例如是硅。漏极电极20设置于半导体部10的背面上。源极电极30设置于半导体部10的表面侧。栅极电极40及FP电极50位于半导体部10与源极电极30之间，配置于设置于半导体部10的栅极沟槽GT的内部。
FP电极50配置于比栅极电极40更靠近漏极电极20的位置。即，FP电极50设置于比漏极电极20与栅极电极40之间的距离更靠近漏极电极20的位置。
在该例中，FP电极50位于漏极电极20与栅极电极40之间。FP电极50例如在未图示的部分与源极电极30电连接。
栅极电极40通过栅极绝缘膜43与半导体部10电绝缘。此外，栅极电极40通过层间绝缘膜45与源极电极30电绝缘。
FP电极50通过绝缘膜53与半导体部10电绝缘。另外，FP电极50通过绝缘膜55及绝缘膜57与栅极电极40电绝缘。
栅极电极40例如位于层间绝缘膜45与绝缘膜53之间、以及层间绝缘膜45与绝缘膜55之间。
半导体部10包括第一半导体层(以下，为n型漂移层11)、第二半导体层(以下，为p型扩散层13)、第三半导体层(以下，为n型源极层15)、p型接触层17以及n型漏极层19。
n型漂移层11在漏极电极20与源极电极30之间延伸。栅极电极40位于n型漂移层11与源极电极30之间。另外，FP电极50位于n型漂移层11的内部。
p型扩散层13设置于n型漂移层11与源极电极30之间。p型扩散层13以隔着栅极绝缘膜43与栅极电极40相对的方式配置。
n型源极层15选择性地设置于p型扩散层13与源极电极30之间。n型源极层15配置于与栅极绝缘膜43接触的位置。n型源极层15包含浓度比n型漂移层11的n型杂质的浓度高的n型杂质。n型源极层15与源极电极30电连接。
p型接触层17选择性地设置于p型扩散层13与源极电极30之间。p型接触层17包含浓度比p型扩散层13的p型杂质的浓度高的p型杂质。p型接触层17与源极电极30电连接。
在该例中，源极电极30具有到达p型接触层17的延伸部30c。延伸部30c与n型源极层15及p型接触层17接触且电连接。源极电极30经由p型接触层17与p型扩散层13电连接。
n型漏极层19设置于n型漂移层11与漏极电极20之间。漏极电极20例如与n型漂移层11接触且电连接。n型漏极层19包含浓度与n型漂移层11的n型杂质的浓度相比高浓度的n型杂质。
如图1所示，栅极电极40例如包括空隙、所谓的孔隙VG。孔隙VG的内表面被绝缘膜47覆盖。另外，绝缘膜47也可以以填充孔隙VG的内部的空间的方式设置。绝缘膜47设置于与栅极绝缘膜43、层间绝缘膜45、绝缘膜53以及绝缘膜55分离的位置。例如，孔隙VG位于层间绝缘膜45与绝缘膜55之间。
接着，参照图2的(a)～图7的(b)，说明半导体装置1的制造方法。图2的(a)～图7的(b)是依次表示半导体装置1的制造过程的示意剖视图。
如图2的(a)所示，在半导体晶片100的表面侧形成栅极沟槽GT。栅极沟槽GT例如使用各向异性RIE(Reactive Ion Etching，反应性离子蚀刻)而形成。半导体晶片100例如是n型硅晶片。半导体晶片100包括与n型漂移层11的n型杂质相同浓度的n型杂质。
如图2的(b)所示，以覆盖栅极沟槽GT的内部的方式形成绝缘膜53。绝缘膜53以在栅极沟槽GT的内部残留空间SP1的方式形成。绝缘膜53例如是对半导体晶片100进行热氧化而成的硅氧化膜。
如图2的(c)所示，在半导体晶片100的表面侧形成导电膜103。导电膜103形成为填埋栅极沟槽GT内的空间SP1。导电膜103例如是具有导电性的多晶硅膜，使用CVD(ChemicalVapor Deposition，化学气相沉积)形成。导电膜103例如包含作为n型杂质的磷(P)。
如图3的(a)所示，将填埋到栅极沟槽GT的底部的部分保留地、选择性地去除导电膜103。由此，在栅极沟槽GT的底部形成FP电极50。在栅极沟槽GT的内部形成有空间SP2。
如图3的(b)所示，在FP电极50的上端形成绝缘膜57。绝缘膜57例如为硅氧化膜，通过隔着空间SP2对FP电极50进行热氧化而形成。
如图3的(c)所示，在半导体晶片100的表面侧形成绝缘膜55。绝缘膜55形成为将栅极沟槽GT内的空间SP2填埋。绝缘膜55例如是包含硼(B)以及磷(P)的硅酸盐玻璃膜、所谓BPSG膜，使用CVD形成。
如图4的(a)所示，保留将栅极沟槽GT的内部填埋的部分，选择性地去除绝缘膜55及绝缘膜53。绝缘膜53以在Z方向上在比FP电极50的上端高的位置具有其上端的方式被去除。绝缘膜55的一部分在FP电极50的上方残留在绝缘膜57之上。例如，通过湿法蚀刻去除绝缘膜53和绝缘膜55。在栅极沟槽GT的上部形成空间SP3。
如图4的(b)所示，以将半导体晶片100的露出部覆盖的方式形成栅极绝缘膜43。栅极绝缘膜43例如为硅氧化膜，通过对半导体晶片100进行热氧化而形成。栅极绝缘膜43形成为在栅极沟槽GT的上部残留空间SP3。
如图4的(c)所示，在半导体晶片100的表面侧形成导电膜105。导电膜105形成为将栅极沟槽GT内的空间SP3填埋。导电膜105例如是包括作为n型杂质的磷(P)的多晶硅膜，使用CVD形成。栅极绝缘膜43位于半导体晶片100与导电膜105之间。
导电膜105以在其内部包括孔隙VG的方式形成。导电膜105例如在使空间SP3的开口处的沉积速度比在空间SP3的底部的沉积速度快的条件下形成。孔隙VG形成于从栅极绝缘膜43、绝缘膜53以及绝缘膜55分离的位置、例如空间SP3的中央。孔隙VG例如具有Z方向的长度比X方向的宽度长的剖面形状。
如图5的(a)所示，通过对导电膜105进行热氧化，形成绝缘膜107。绝缘膜107例如是硅氧化膜。绝缘膜107形成为覆盖导电膜105的露出面。在该过程中，孔隙VG的内表面也被氧化，形成绝缘膜47。绝缘膜47例如是硅氧化膜。
例如，作为氧化剂的氧沿着多晶硅膜的晶界渗透至内部。当氧到达孔隙VG时，将暴露于孔隙VG内表面的硅原子氧化，形成绝缘膜47。
如图5的(b)所示，去除绝缘膜107，使导电膜105的表面露出。绝缘膜107例如通过湿法蚀刻而被去除。
如图5的(c)所示，保留填埋空间SP3的(参照图4的(b))的部分，选择性地去除导电膜105。导电膜105例如使用干法蚀刻或湿法蚀刻而被去除。由此，在栅极沟槽GT的内部形成栅极电极40。
如图6的(a)所示，在半导体晶片100的表面侧形成p型扩散层13及n型源极层15。
p型扩散层13通过在半导体晶片100的表面侧离子注入例如作为p型杂质的硼(B)后，通过热处理使其活化及扩散而形成。此时，控制热处理时间，使得n型漂移层11与p型扩散层13的界面在Z方向上位于与栅极电极40的下表面相同的水平或比栅极电极40的下表面靠上的水平。
n型源极层15例如通过在半导体晶片100的表面侧离子注入作为n型杂质的磷(P)后，通过热处理使其活化而形成。
如图6的(b)所示，在半导体晶片100的表面侧形成层间绝缘膜45。层间绝缘膜45以覆盖栅极电极40以及栅极绝缘膜43的方式形成。层间绝缘膜45例如是硅氧化膜，使用CVD形成。
此外，通过选择性地去除栅极绝缘膜43和层间绝缘膜45来形成接触槽45c。接触槽45c与n型源极层15连通，并沿着栅极电极40例如在Y方向上延伸。
如图6的(c)所示，经由接触槽45c，选择性地去除n型源极层15，使p型扩散层13在接触槽45c的底面露出。之后，经由接触槽45c离子注入作为p型杂质的硼，并实施热处理，由此形成p型接触层17。
如图7的(a)所示，在半导体晶片100的表面侧形成源极电极30。源极电极30形成为，覆盖层间绝缘膜45，并具有在接触槽45c的内部延伸的延伸部30c。源极电极30例如是使用溅射法形成的金属层，包括铝(Al)。
如图7的(b)所示，在半导体晶片100的背面侧形成n型漏极层19及漏极电极20，完成半导体装置1。
n型漏极层19是通过对半导体晶片100的背面侧进行磨削或蚀刻而将半导体晶片100薄层化成规定的厚度后，将作为n型杂质的磷(P)离子注入到背面侧并进行热处理而形成的。半导体晶片100的位于p型扩散层13与n型漏极层19之间的部分成为n型漂移层11。
漏极电极20例如是包括钛(Ti)的金属层，使用溅射法形成于n型漏极层19的背面上。
在实施方式的制造方法中，通过对导电膜105进行热氧化，形成将孔隙VG的内表面覆盖的绝缘膜47的(参照图5的(a))。由此，对于图5的(a)所示的工序以后的制造过程中的热处理，能够使孔隙VG稳定化。另外，绝缘膜47也可以形成为使孔隙VG闭塞。即，在形成绝缘膜47之后在孔隙VG的内部不残留空间的情况也存在。
例如，在未形成绝缘膜47的情况下，在孔隙VG的内表面露出的硅原子通过热处理而脱离，并重新附着于孔隙VG的内部。通过重复该动作，有时在栅极电极40的内部孔隙VG移动，例如位于栅绝缘膜43的附近。其结果，孔隙VG使栅极阈值电压、沟道电阻等变化，使晶体管特性劣化。
与此相对，在半导体装置1中，形成绝缘膜47，由此抑制孔隙VG的内表面处的硅原子的脱离。由此，能够防止孔隙VG的移动。即，在半导体装置1中，孔隙VG被保持在远离栅极绝缘膜43的位置，不会对晶体管特性造成影响。
接着，参照图8的(a)～(c)，说明第一实施方式的变形例的半导体装置1的制造方法。图8的(a)～(c)是表示接着图4的(b)的制造过程的示意剖视图。
如图8的(a)所示，在半导体晶片100的表面侧形成不掺杂杂质的多晶硅层115。多晶硅层115形成为将栅极沟槽GT的上部的空间SP3填埋。多晶硅层115在填埋空间SP3的部分包括孔隙VG。
如图8的(b)所示，通过对多晶硅层115进行热氧化，形成绝缘膜107，覆盖多晶硅层115的表面。在该过程中，以覆盖孔隙VG的内表面的方式形成绝缘膜47。
如图8的(c)所示，在去除绝缘膜107之后，向多晶硅层115扩散作为n型杂质的磷(P)。例如，通过在包括膦(PH3)的N2等惰性气体的气氛中进行热处理，使磷(P)扩散到多晶硅中。另外，也可以在多晶硅中离子注入磷(P)，并通过热处理使其扩散。或者，也可以在非掺杂多晶硅上形成含有磷(P)的多晶硅层，并通过热处理使磷(P)扩散到非掺杂多晶硅中。由此，多晶硅层115具有导电性。
接着，保留填埋空间SP3的部分，去除多晶硅层115(参照图5的(c))。之后，通过图6的(a)～图7的(b)所示的制造过程，完成半导体装置1。
在该例子中，通过用绝缘膜47覆盖孔隙VG的内表面，提高对热处理的耐性。例如，在使n型杂质向多晶硅层115扩散的过程中，能够抑制孔隙VG的移动。
图9的(a)及(b)是表示第一实施方式的变形例的半导体装置2及3的示意剖视图。
图9的(a)所示的半导体装置2具备栅极电极40a(第一控制部)以及栅极电极40b(第二控制部)。栅极电极40a及40b与FP电极50一起配置于栅极沟槽GT的内部。
栅极电极40a及40b分别隔着栅极绝缘膜43以与p型扩散层13相对的方式配置。FP电极50包括隔着绝缘膜53与n型漂移层11相对的主部和在栅极电极40a与栅极电极40b之间延伸的延伸部50ex。延伸部50ex通过绝缘膜59与栅极电极40a及40b电绝缘。绝缘膜59设置于栅极电极40a与栅极电极40b之间。
栅极电极40a及40b通过层间绝缘膜45与源极电极30电绝缘。栅极电极40a及40b分别位于层间绝缘膜45和绝缘膜53之间。另外，栅极电极40a及40b分别位于栅极绝缘膜43与绝缘膜59之间。
源极电极30具有包括接合层33和接触层35的层叠构造。接合层33例如是包含铝(Al)的金属层。接触层35位于结合层33与层间绝缘膜45之间。接触层35例如是包含钛(Ti)的金属层。
接触层35具有到达p型接触层17的延伸部35c。源极电极30经由延伸部35c与n型源极层15及p型接触层17电连接。
在该例中，栅极电极40a及40b也分别具有孔隙VG，孔隙VG的内表面被绝缘膜47覆盖。在栅极电极40a及40b的每一个中，孔隙VG设置于从栅极绝缘膜43、层间绝缘膜45、绝缘膜53和绝缘膜59分离的位置。孔隙VG位于栅极绝缘膜43与绝缘膜59之间以及层间绝缘膜45与绝缘膜53之间。绝缘膜47抑制因热处理导致的孔隙VG的移动，防止晶体管特性的劣化。
图9的(b)所示的半导体装置3具有栅极沟槽GT以及场沟槽FT。栅极电极40配置于栅沟槽GT的内部。栅极电极40通过栅极绝缘膜43与半导体部10电绝缘。另外，栅极电极40通过层间绝缘膜45与源极电极30电绝缘。
FP电极50配置于场沟槽FT的内部，通过绝缘膜53与半导体部10电绝缘。栅极电极40例如设置于在沿着半导体部10的表面的方向上相邻的FP电极50之间。FP电极50例如在未图示的部分与源极电极30电连接。
在该例子中，栅极电极40也包括孔隙VG。孔隙VG的内表面被绝缘膜47覆盖。孔隙VG设置于从栅极绝缘膜43和层间绝缘膜45分离的位置。孔隙VG，通过绝缘膜47而相对于热处理被稳定化，被保持在不影响晶体管特性的位置。
(第二实施方式)
图10是表示第二实施方式的半导体装置4的示意剖视图。半导体装置4具备在栅极沟槽GT的内部设置的FP电极50及栅极电极60。FP电极50设置于比漏极电极20与栅极电极60之间的距离更靠近漏极电极20的位置。
在该例中，FP电极50配置于漏极电极20与栅极电极60之间。FP电极50通过绝缘膜53与半导体部10电绝缘。FP电极50通过绝缘膜55和57与栅极电极60电绝缘。
栅极电极60位于源极电极30与FP电极50之间，通过层间绝缘膜45与源极电极30电绝缘。另外，栅极电极60通过栅极绝缘膜63与半导体部10电绝缘。
如图10所示，半导体装置4还具备位于层间绝缘膜45与栅极电极60之间的绝缘膜65。绝缘膜65包括向栅极电极60的内部突出的突起部67。
突起部67例如位于层间绝缘膜45与绝缘膜55之间，朝向绝缘膜55延伸。突起部67的Z方向的长度例如比从突起部67的前端到栅极电极60的下端的距离短。绝缘膜65例如也可以包含与层间绝缘膜45相同的材料，并与层间绝缘膜45一体地设置。
接着，参照图11的(a)～图12的(c)，说明半导体装置4的制造方法。图11的(a)～图12的(c)是表示接着图4的(b)的制造过程的示意剖视图。
如图11的(a)所示，在半导体晶片100的表面侧形成导电膜123。导电膜123覆盖栅极沟槽GT的上部的空间SP1的内表面。导电膜123例如是包括作为n型杂质的磷(P)的多晶硅膜。导电膜123例如使用CVD形成。
如图11的(b)所示，随着导电膜123形成得较厚，空间SP3变窄。
如图11的(c)所示，导电膜123以空间SP3被闭塞的方式形成得较厚。作为结果，导电膜123形成为在其内部具有接缝SM。接缝SM通过例如在空间SP3的两侧的内壁上沉积的导电膜123的一部分相互接触而形成。
在该例子中，导电膜123不包括图4的(c)所示的孔隙VG，并且具有接缝SM。这样的差异例如取决于空间SP3的形状或尺寸。例如，在空间SP3的开口宽度WGT比底部的宽度WBT宽的情况下，不形成孔隙VG，导电膜123包括接缝SM。
如图12的(a)所示，保留填埋空间SP3的部分，去除导电膜123。导电膜123的填埋空间SP3的部分成为栅极电极60。
如图12的(b)所示，通过将栅极电极60热氧化来形成绝缘膜65。绝缘膜65例如是硅氧化膜，以覆盖栅极电极60的上表面的方式形成。绝缘膜65具有延伸到栅极电极60中的突起部67。
绝缘膜65的突起部67沿着接缝SM形成。突起部67例如通过由作为氧化剂的氧将位于接缝SM的硅原子氧化而形成。
如图12的(c)所示，在半导体晶片100的表面侧离子注入p型杂质及n型杂质并进行热处理，由此形成p型扩散层13及n型源极层15。接着，通过图6的(a)～图7的(b)所示的制造过程，完成半导体装置4。
在该例子中，通过在栅极电极60的内部形成的绝缘膜65的突起部67，栅极电极60的X方向的宽度变宽。因此，应力施加于位于X方向上相邻的栅极电极60之间的p型扩散层13及n型源极层15，在构成p型扩散层13及n型源极层15的半导体结晶中产生应变。其结果，例如，p型扩散层13中的电子的迁移率变大。由此，能够降低相对于经由在p型扩散层13与栅极绝缘膜63的界面处所感应的反型沟道而流动的导通电流的电阻。
图13的(a)及(b)是表示第二实施方式的变形例的半导体装置5及6的示意剖视图。
图13的(a)所示的半导体装置5具备栅极电极60a及60b。栅极电极60a和60b与FP电极50一起配置于栅沟槽GT的内部。
栅极电极60a及60b分别配置为隔着栅极绝缘膜63与p型扩散层13相对。FP电极50包括在栅极电极60a和栅极电极60b之间延伸的延伸部50ex。延伸部50ex通过绝缘膜59与栅极电极60a及60b电绝缘。
栅极电极60a和60b通过层间绝缘膜45与源极电极30电绝缘。源极电极30具有包括接合层33和接触层35的层叠构造。接触层35具有到达p型接触层17的延伸部35c。源极电极30经由延伸部35c与n型源极层15及p型接触层17电连接。
在该例子中也是，在层间绝缘膜45与栅极电极60a及60b之间分别设置绝缘膜65。绝缘膜65包括延伸到栅极电极60a和60b的每一个中的突起部67。
突起部67位于层间绝缘膜45与绝缘膜53之间，并朝向绝缘膜53延伸。突起部67的沿着延伸方向的长度例如比从突起部67的前端到栅极电极60a以及60b各自的下端的距离短。通过突起部67，例如对p型扩散层13及n型源极层15施加应力，能够降低在p型扩散层13与栅极绝缘膜63的界面感应的反型沟道中的电阻。
图13的(b)所示的半导体装置6具有栅极沟槽GT以及场沟槽FT。栅极电极60配置于栅沟槽GT的内部，通过栅绝缘膜63与半导体部10电绝缘。另外，栅极电极60配置于半导体部10与源极电极30之间，通过层间绝缘膜45与源极电极30电绝缘。
FP电极50配置于场沟槽FT的内部，通过绝缘膜53与半导体部10电绝缘。FP电极50例如在未图示的部分与源极电极30电连接。
在该例子中也是，在层间绝缘膜45与栅极电极60之间设置绝缘膜65。绝缘膜65包括延伸到栅极电极60中的突起部67。突起部67的Z方向的长度例如比从突起部67的前端到栅极电极60的下端的距离短。由此，对p型扩散层13及n型源极层15施加应力，能够降低在p型扩散层13与栅极绝缘膜63的界面感应的反型沟道中的电阻。
另外，上述的实施方式对于不设置FP电极50的构造也是有效的。例如，在半导体装置3以及6中，也可以是不设置场沟槽FT而不配置FP电极50的构造。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提示的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。这些实施方式及其变形包括在发明的范围及主旨中，并且包括在权利要求书所记载的发明及其等同的范围内。

Claims (17)

1.一种半导体装置，具备：
半导体部；
第一电极，设置于所述半导体部的背面上；
第二电极，设置于所述半导体部的表面上；以及
控制电极，在所述半导体部与所述第二电极之间配置于设置于所述半导体部的沟槽的内部，通过第一绝缘膜与所述半导体部电绝缘，通过第二绝缘膜与所述第二电极电绝缘，包含被设置于与所述第一绝缘膜以及所述第二绝缘膜分离的位置的第三绝缘膜，
所述半导体部包括第一导电型的第一半导体层、第二导电型的第二半导体层、以及所述第一导电型的第三半导体层，
所述第一半导体层在所述第一电极与所述第二电极之间延伸，所述控制电极位于所述第一半导体层与所述第二电极之间，
所述第二半导体层设置于所述第一半导体层与所述第二电极之间，隔着所述第一绝缘膜与所述控制电极相对，
所述第三半导体层选择性地设置于所述第二半导体层与所述第二电极之间，配置于与所述第一绝缘膜接触的位置，与所述第二电极电连接。
2.根据权利要求1所述的半导体装置，其中，
还具备；
第三电极，在所述沟槽的内部，设置于与从所述控制电极到所述第一电极的距离相比更靠近所述第一电极的位置，通过第四绝缘膜与所述半导体部电绝缘，并通过第五绝缘膜与所述控制电极电绝缘，
所述第三绝缘膜设置于与所述第四绝缘膜和所述第五绝缘膜分离的位置。
3.根据权利要求1或2所述的半导体装置，其中，
所述控制电极在与所述第一绝缘膜以及所述第二绝缘膜分离的位置包括空隙，
所述第三绝缘膜覆盖所述空隙的内表面。
4.根据权利要求2所述的半导体装置，其中，
所述第三电极设置于所述第一电极与所述控制电极之间，隔着所述第四绝缘膜与所述半导体部的所述第一半导体层相对，
所述控制电极位于所述第二绝缘膜与所述第四绝缘膜之间、以及所述第二绝缘膜与所述第五绝缘膜之间。
5.根据权利要求4所述的半导体装置，其中，
所述第三绝缘膜位于所述第二绝缘膜与所述第五绝缘膜之间。
6.根据权利要求4所述的半导体装置，其中，
所述第三绝缘膜在从所述第一电极朝向所述第二电极的方向上的长度，比在从所述半导体部的所述第二半导体层朝向所述控制电极的方向上的宽度长。
7.根据权利要求2所述的半导体装置，其中，
所述控制电极包括在从所述半导体部的所述第二半导体层朝向所述控制电极的方向上排列的第一控制部和第二控制部，
所述第三电极具有：隔着所述第四绝缘膜与所述半导体部的所述第一半导体层相对的第一部分、以及在所述第一控制部与所述第二控制部之间延伸的第二部分，
所述第三电极的所述第二部分通过设置于所述第一控制部与所述第二控制部之间的第五绝缘膜而与所述控制电极电绝缘，
所述第一控制部以及所述第二控制部分别位于所述第二绝缘膜与所述第四绝缘膜之间。
8.根据权利要求7所述的半导体装置，其中，
所述第三绝缘膜位于所述第一绝缘膜与所述第五绝缘膜之间、以及所述第二绝缘膜与所述第四绝缘膜之间。
9.根据权利要求1所述的半导体装置，其中，
所述控制电极包括多晶硅，
所述第三绝缘膜是硅氧化膜。
10.一种半导体装置，具备：
半导体部；
第一电极，设置于所述半导体部的背面上；
第二电极，设置于所述半导体部的表面上；
控制电极，在所述半导体部与所述第二电极之间配置于设置于所述半导体部的沟槽的内部；
第一绝缘膜，将所述控制电极与所述半导体部电绝缘；以及
第二绝缘膜，将所述控制电极与所述第二电极电绝缘，包括延伸到所述控制电极中的突起部，
所述半导体部包括第一导电型的第一半导体层、第二导电型的第二半导体层、以及所述第一导电型的第三半导体层，
所述第一半导体层在所述第一电极与所述第二电极之间延伸，所述控制电极位于所述第一半导体层与所述第二电极之间，
所述第二半导体层设置于所述第一半导体层与所述第二电极之间，隔着所述第一绝缘膜与所述控制电极相对，
所述第三半导体层选择性地设置于所述第二半导体层与所述第二电极之间，配置于与所述第一绝缘膜接触的位置，与所述第二电极电连接。
11.根据权利要求10所述的半导体装置，其中，
所述第二绝缘膜的沿着所述突起部的延伸方向的长度，比从所述突起部的前端到所述控制电极的下端的距离短。
12.根据权利要求10所述的半导体装置，其中，
还具备：
第三电极，在所述沟槽的内部设置于所述控制电极与所述第一电极之间，通过第四绝缘膜与所述半导体部的所述第一半导体层电绝缘，通过第五绝缘膜与所述控制电极电绝缘，
所述第二绝缘膜的所述突起部位于所述第二绝缘膜与所述第五绝缘膜之间，并朝向所述第五绝缘膜延伸。
13.根据权利要求10所述的半导体装置，其中，
还具备：
第三电极，与所述控制电极一起设置于所述沟槽的内部，
所述控制电极包括在从所述半导体部的所述第二半导体层朝向所述控制电极的方向上排列的第一控制部和第二控制部，
所述第三电极具有：隔着所述第四绝缘膜与所述半导体部的所述第一半导体层相对的主部、以及在所述第一控制部与所述第二控制部之间延伸的部分，
所述第三电极的所述延伸部分，通过设置于所述第一控制部与所述第二控制部之间的第五绝缘膜而与所述控制电极电绝缘，
所述第一控制部以及所述第二控制部，分别位于所述第二绝缘膜与所述第四绝缘膜之间，
所述第二绝缘膜的所述突起部，位于所述第一绝缘膜与所述第五绝缘膜之间，并朝向所述第四绝缘膜延伸。
14.一种半导体装置的制造方法，具备：
在半导体晶片上形成沟槽的工序；
在所述沟槽的内部保留空间地形成覆盖所述沟槽的内表面的第一绝缘膜的工序；
形成将所述沟槽的所述空间填埋的导电层的工序；以及
通过对所述导电层进行热氧化，在所述导电层的表面形成第二绝缘膜，并且在所述导电层的内部形成第三绝缘膜的工序。
15.根据权利要求14所述的半导体装置的制造方法，其中，
所述第三绝缘膜形成于与所述第一绝缘膜以及所述第二绝缘膜分离的位置。
16.根据权利要求14所述的半导体装置的制造方法，其中，
所述第三绝缘膜形成为从所述第二绝缘膜延伸到所述导电层中。
17.根据权利要求14所述的半导体装置的制造方法，其中，
所述半导体装置包括：
设置于所述沟槽的内部的控制电极；
电极层，设置于所述半导体晶片上，隔着与所述第一绝缘膜～第三绝缘膜不同的第四绝缘膜覆盖所述控制电极；
第一导电型的第一半导体层，设置于所述半导体晶片中；以及
第二导电型的第二半导体层，设置于所述第一半导体层与所述电极层之间，与所述电极层电连接，
所述导电层的至少一部分成为所述控制电极，
所述沟槽在所述第一半导体层中延伸，
所述第二半导体层设置为隔着所述第一绝缘膜与所述控制电极相对。
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