CN1129358A - 迁移率提高了的mosfet器件及其制造方法 - Google Patents

迁移率提高了的mosfet器件及其制造方法 Download PDF

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CN1129358A
CN1129358A CN95117359A CN95117359A CN1129358A CN 1129358 A CN1129358 A CN 1129358A CN 95117359 A CN95117359 A CN 95117359A CN 95117359 A CN95117359 A CN 95117359A CN 1129358 A CN1129358 A CN 1129358A
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乔恩J·坎迪拉里亚
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Abstract

一种迁移率提高了的MOSFET器件(10)，它包含一个形成在单晶硅层(11)上的沟道层(12)。沟道层(12)包含硅和第二种材料的合金，其中，第二种材料替位地出现在硅的晶格位置上，其原子百分比使沟道层(12)处于张应力之下。

Description

迁移率提高了的MOSFET器件及其制造方法
本发明一般涉及到半导体器件、更确切地说是涉及到具有提高了的载流子迁移率的半导体器件。
金属氧化物半导体场效应晶体管(MOSFET)已为人们熟知并广泛地应用于电子工业。MOSFET器件的载流子迁移率由于直接影响到输出电流和开关性能而成为一个重要参数。在标准的MOSFET技术中，为改善电流驱动和开关性能而减小沟道长度和栅极介质厚度。但由于栅极介质厚度的减小相应增加了本征栅电容而会损害器件性能。
在硅MOSFET器件中已表明，上下以硅区为界、由硅锗(Si1－xGex)合金构成的处于压应力下的埋置沟道区可以提高沟道区中的空穴载流子迁移率。这是由于空穴被该周围硅区和Si1－xGex沟道区之间的势能偏移限制于沟道区中。在授予Murakami等人的美国专利5019882和授予Solomon等人的美国专利5241197中示出了这种应变(strained)器件。
埋置Si1－xGex沟道的器件有一些缺点，包括增加了的沟道区合金散射使电子迁移率下降、不希望有的导带偏移使电子迁移率提高很少、得不到比硅更高的载流子速度，以及为了产生应力并提高迁移率而需要高的Ge浓度。高的Ge浓度引起层厚度和工艺温度大大降低。降低了的工艺温度对杂质激活和栅氧化工艺有不利影响。
带有处于张应力下的沟道区的硅器件是可取的，这是由于张应力引起空穴和电子迁移率都提高且比起硅来可提高载流子速度。已报道的一种方法采用了一种在硅沟道区下方带有一个Si0.7Ge0.3合金弛豫层并在Si0.7Ge0.3合金层下方带有一个Si1－xGex(X＝5－30％)缓冲层的应变硅表面沟道区。此法的优点是消除了沟道区中的合金散射。但此法有一个缺点，即应变沟道区处于表面从而对会使迁移率降低的表面散射效应很敏感。对热载流子退化和噪声问题也很敏感。此外，此法需要合金弛豫层和缓冲层，使工艺复杂性和成本增加。
另一种已报导的方法采用一种形成在Si1－yGey(其中y＞x)弛豫层上的应变Si1－xGex沟道层，在该应变Si1－xGex沟道层上方带有一个硅层并在Si1－yGey弛豫层下方带有一个硅层。这种结构有一些缺点，包括：载流子会迁移出应变Si1－xGex沟道层而进入Si1－yGey合金弛豫层从而降低提高的迁移率效应，由于沟道层中存在锗而出现较大的合金散射效应，以及因多层SiGe而增加工艺复杂性。
显而易见，需要有一种电子和空穴迁移率得提高到的、对合金散射效应不那么敏感的、对表面散射效应也不那么敏感的且不需要合金弛豫层和缓冲层的MOSFET器件。
简要地说，迁移率提高了的MOSFET器件包含一个形成在第一导电类型单晶硅层上的载流子输运区。载流子输运区包含一个硅与第二材料的合金，其中第二材料在载流子输运区中的原子百分比要使载流子输运区处于张力状态。第二导电类型的源区和漏区延伸到载流子输运区中。载流子输运区的一部分将源区和漏区分隔开来。控制电极与载流子输运区电隔离并排列在源区和漏区之间。
制作此处所述迁移率提高了的MOSFET的方法包括在第一导电类型单晶硅层上制作一个载流子输运区。此载流子输运区包含一个硅与第二材料的合金。第二材料在载流子输运区中的原子百分比使载流子输运区处于张应力之下。栅介质层制作在部分载流子输运区上。控制电极制作在栅介质层上。第二导电类型的源区和漏区制作成至少延伸到载流子输运区中，这部分载流子输运区位于源和漏区之间。
图1是本发明一个实施例的放大剖面图；
图2是图1实施例在零栅偏压下的能带图；
图3是本发明另一实施例的放大剖面图；
图4是本发明又一实施例的放大剖面图；
图5是本发明又一实施例的放大剖面图。
图1示出了根据本发明的具有提高了的载流子迁移率的MOSFET器件10的一个实施例。载流子输运区即沟道层12制作在单晶硅层11上。沟道层12为硅和第二材料的合金。p沟道器件的单晶硅层11为n型导电类型而n沟道器件的单晶硅层11为p型导电类型。第二材料以替位形式出现在沟道层12的晶格位置中，其原子百分比要使沟道层相比于单晶硅层11或含硅晶体来说处于张应力之下。沟道层12最好不要用受主或施主杂质掺杂。
MOSFET器件10还包含形成在沟道层12上的外延半导体即外延层13。外延层13最好含有硅，且厚度为50埃数量级。源区14和漏区16延伸通过外延层13且至少伸入沟道层12。源区14和漏区16最好延伸通过沟道层12进入单晶硅层11之中。一部分沟道层12位于源区14和漏区16之间。控制电极即栅电极18和外延层13电隔离。栅电极18最好用栅介质层17和外延层13电隔离。栅介质层17最好由氧化物构成且其厚度在30—125埃范围内。在部分源区14上制作源电极19并在部分漏区16上制作漏电极21。
图2是图1实施例在零栅偏压下的能带图，示出了应变引入的能带分裂对沟道层12的作用。图2示出了外延层13中、沟道层12中和单晶硅层11中价带22与导带23之间的相对关系。当沟道层12处于张应力下时，沟道层12中的价带边即交界面24分裂，并实际上能级向上移向导带23。此外，导带边即界面26分裂并实际上能级向下移向价带22。这就产生了一个比单晶硅层带隙28和外延层带隙29窄的沟道层带隙27。沟道层带隙27的偏移或变窄实际上产生一个在沟道层12中捕获空穴和电子的势阱。而且，上述效应还使沟道12具有被有效载流子质量降低了的空穴和电子优先占据的能级。当栅电极18加有恰当栅偏压时，这又反过来提高了沟道层12中的自由载流子迁移率。
张应力下的沟道层比压应力下的沟道层更好，这是由于张应力能提供更大的导带分裂。此外，比之压应力下的薄膜，张应力下的薄膜预计有较低的有效载流子质量。于是，张应力下的沟道层可提高电子和空穴载流子的迁移率并保证了迁移率提高了的互补p沟道和n沟道器件的制造。
如授予J.Cande laria和Motorola公司的美国专利5360986(此处作为参考文献)所示，掺碳硅是一种适用于沟道层12的合金材料。在最佳实施例中，沟道层12包含一个掺碳的硅而Si1－xCx合金，其中碳是第二材料，碳位于替位硅晶格位置上，x最好≤0.02。x最好在约0.005—0.016的范围内。
当x为0.02—0.005数量级时，沟道层12的厚度最好分别为100—200埃数量级。根据碳存在的原子百分比来调整沟道层12的厚度。当沟道层12包含Si1－xCx合金时，外延层13最好包含硅且厚度在50—100埃范围内。
由于掺碳沟道层的合金/载流子散射效应较低，故掺碳硅沟道层优于掺Ge硅沟道层。这是由于碳与锗原子间的相对尺寸差使得有可能利用比锗量低很多的碳量(11～1的数量级)来获得相似的应变幅度(尽管符号相反)。由于掺碳硅沟道层的合金/载流子散射效应比有类似应变的掺Ge硅沟道层低，故载流子迁移率，特别是电子迁移率得到了额外的提高。而且，由于MOSFET器件10中的沟道层12是埋置的，亦即以外延层13和单晶硅层11为界，故MOSFET10对表面散射、热载流子退化和噪声效应更不敏感。
当沟道层12含有Si1－xCx合金时，采用外延生长即化学气相淀积技术来制作沟道层12。例如采用乙炔、乙稀、丙烷或甲烷碳源。或者为美国专利5360986所示，制作一个硅层，将碳离子注入到硅层中，并加热掺碳的硅层以诱导掺碳硅层的固相外延再生长以形成沟道层12。或者用分子束外延、金属有机化学气相淀积(MOCVD)或超高真空化学气相淀积(UHVCVD)来制作沟道层12。
在制作带有p沟道结构和掺碳的沟道层的MOSFET10的最佳实施例中，n型导电性单晶硅层11被选择性地形成在p型衬底上或p型衬底中。然后在不掺杂的硅层上形成含有掺碳硅的沟道层12。接着在沟道层12上形成含有n型掺杂硅或不掺杂硅且厚度为50—100埃数量级的外延层13。不掺杂硅层、沟道层12以及外延层13最好在同一个外延生长步骤中形成。
然后在外延层13上沉积或生长一个厚度在60—80埃范围内的氧化硅层。接着在氧化硅层上形成一个原位掺杂的n型多晶硅层。接下来对此n型多晶硅层和氧化硅层进行选择性图形化以分别形成栅电极18和栅介质层17。再将p型杂质选择性地引入外延层13。然后将该结构加热以激活p型杂质而形成源区14和漏区16。再用标准的MOSFET工艺来完成MOSFET器件10。为制作n沟道结构形式的MOSFET器件10，杂质的导电类型正好相反。
图3—5示出了根据本发明的迁移率提高了的MOSFET器件的其它实施例。图3所示MOSFET30除不带有外延层13之外均与MOSFET器件10相似。MOSFET30具有如前所述的提高了的迁移率，但由于沟道层12和栅介质层17之间的界面而对表面散射效应更为敏感。然而，比之结构相似的无应力硅沟道MOSFET器件来说，MOSFET30的载流子迁移率仍然提高了。
图4所示的MOSFET器件40相似于MOSFET器件10，另外还带有形成在单晶硅层11中的调制掺杂层或调制层41。单晶硅层11的43部分将调制层41和沟道层12分隔开来。43部分和厚度最好为50—100埃数量级。调制层41的导电类型与源区14和漏区16相同，其杂质浓度高于单晶硅层11，而且导电类型相反。调制层41的厚度最好在100—200埃的范围内。
调制层41采用外延生长即化学气相淀积(CVD)制作在单晶硅层11的42部位。然后用外延生长或CVD技术在调制层41上制作单晶硅层11的43部分。可用离子注入或扩散技术向单晶硅层11的43部分掺入n型或p型杂质，具体根据MOSFET器件10是p沟道抑或是n沟道器件来决定。调制层41和单晶硅层11的43部分最好在同一个原位工序中相继制作。
图5所示的MOSFET50和MOSFET10相似，另还带有隔离层即区51以形成一个绝缘体上半导体(SOI)器件。隔离层51最好包含氧化硅并用离子注入氧或其它技术来制作。隔离层51最好在形成沟道层12和外延层13之前制作。作为变通，隔离层51可制作在支撑用的衬底(未绘出)上，然后将单晶硅衬底固定到隔离层51上，并将单晶硅衬底减薄至所需的厚度以形成单晶硅层11。隔离层51最好与沟道层12隔开一个500—600埃的距离52。
当隔离层51同MOSFET器件3一起使用时(图3)，它最好位于沟道层12下方1000埃数量级处。当隔离层51同MOSFET40一起使用时(图4)，它最好位于调制层41下方100—200埃数量级处。
至此应认为已提供了一种迁移率提高了的MOSFET器件。借助于在单晶硅层上制作一个载流子输运区(其中的载流子输运区包含一个硅和第二材料的合金，且第二材料在载流子输运区中的原子百分比使载流子输运区处于张应力之下)，获得了提高了的载流子迁移率。
而且，借助于使载流子输运区处于张应力之下，获得了比之载流子输运区处于压应力下更大的导带分裂，从而为电子和空穴载流子都提供了更高的迁移率。这保证了迁移率提高了的互补n沟和p沟器件的制造。
此外，借助于在载流子输运区上增加一个外延层，提供了一个对表面散射、热载流子退化和噪声效应较不敏感的埋置结构。
而且，当载流子输运区包含掺碳硅时，获得了比包含掺锗硅的有类似应变的载流子区更低的合金散射。同时，当载流子输运区包含掺碳硅时，无需采用弛豫合金层就获得了张应力下的载流子输运区。这就降低了工艺的复杂性和成本。

Claims (10)

1.一种迁移率提高了的MOSFET器件，其特征是：
一个第一导电类型的单晶硅层(11)；
一个形成在单晶硅层(11)上的载流子输运区(22)，其中的载流子输运区(12)由硅与第二半导体材料的合金组成，且其中的第二半导体材料替位地出现在载流子输运区(12)的晶格位置，其原子百分比要使载流子输运区处于张应力之下；
一个延伸到载流子输运区(12)中的第二导电类型的源区(14)；
一个延伸到载流子输运区(12)中的第二导电类型的漏区(16)，其中载流子输运区(12)的一部分位于源区(14)和漏区(16)之间；以及
一个与载流子输运区(12)电隔离的控制电极(18)，其中的控制电极(18)排列在源区(14)和漏区(16)之间。
2.如权利要求1的器件，其进一步特征是：
一个排列在载流子输运区(12)和控制电极(18)之间的第一半导体材料的外延层(13)，其中的源区(14)和漏区(16)延伸通过外延层(13)至少进入载流子输运区(12)。
3.如权利要求1的器件，其中的载流于输运区(12)包含Si1－xCx合金。
4.如权利要求3的器件，其中的x≤0.02。
5.一种带有埋置的掺碳的硅沟道区的MOSFET结构，其特征是：
一个沟道层(12)，它包含形成在第一导电类型单晶硅层(11)上的Si1－xCx合金，其中的碳出现在沟道层(12)中替位晶格位置上，使沟道(12)处于张应力之下；
一个形成在沟道层上的硅外延层(13)；
一个延伸通过硅外延层(13)且至少进入沟道层(12)的第二导电类型的源区(14)；
一个延伸通过硅外延层(13)且至少进入沟道层(12)的第二导电类型的漏区(16)，其中的部分沟道层(12)将源区(14)与漏区(16)分隔开来；
一个形成在硅外延层(13)上至少位于源区(14)和漏区(16)之间的栅介质层(17)；以及
一个形成在栅介质层(17)上的栅电极(18)。
6.如权利要求5的结构，其中的x≤0.02，且其中的单晶硅层(11)的厚度为1000埃的数量级，沟道层(12)的厚度为100埃的数量级，而硅外延层(13)的厚度为50埃数量级。
7.如权利要求5的结构，其进一步特征是：一个排列在单晶硅层(11)下方的隔离区(51)。
8.如权利要求5的结构，其中的单晶硅层(11)包括一个排列在单晶硅层(11)中的调制层(41)，其中单晶硅层(11)的一部分将调制层(41)与沟道层(21)分隔开来，且其中的调制层(41)是第二导电类型的，调制层(41)的杂质浓度高于单晶硅层(11)的杂质浓度。
9.一种迁移率提高了的MOSFET器件的制造方法，其特征在于下列步骤：
在第一导电类型的单晶硅层(11)上形成一个载流子输运区(12)，其中，载流子输运区(12)包含硅和第二半导体材料的合金，且其中的第二半导体材料替位地出现在载流子输运区(12)的晶格位置，其原子百分比使载流子输运区(12)比之第一导电类型的单晶硅层(11)来说处于张应力之下；
在载流子输运区(12)上形成一个外延半导体层(13)；
在一部分载流子输运层(12)上的外延半导体层(13)上形成一个栅介质层(17)；
在栅介质层(17)上形成一个控制电极(18)；
形成一个延伸通过外延半导体层(13)至少进入载流子输运区(12)的第二导电类型的源区(14)；以及
形成一个延伸通过外延半导体层(13)至少进入载流子输运区(12)的第二导电类型的漏区(16)，其中部分载流子输运区位于源区(14)和漏区(16)之间。
10.如权利要求9的方法，其中，形成载流子输运区(12)的步骤包括形成一个以Si1－xCx合金为特征的载流子输运区(12)，其中的x≤0.02。
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