CN1319152C - 利用特定晶体管取向的cmos制造方法 - Google Patents

利用特定晶体管取向的cmos制造方法 Download PDF

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CN1319152C
CN1319152C CNB018197612A CN01819761A CN1319152C CN 1319152 C CN1319152 C CN 1319152C CN B018197612 A CNB018197612 A CN B018197612A CN 01819761 A CN01819761 A CN 01819761A CN 1319152 C CN1319152 C CN 1319152C
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semiconductor wafer
described semiconductor
pmos
nmos
stressor
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马克·阿姆斯特朗
格哈德·施罗姆
克林·J·库恩
保罗·A·帕茨卡恩
苏尼特·D·佳格
斯科特·E·汤普森
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Abstract

互补金属氧化物半导体晶体管形成在硅基片上。基片具有{100}结晶取向。形成在基片上的晶体管的取向，是使电流在晶体管沟道内的流动方向平行于<100>方向。此外，在沟道上还施加纵向拉应力。

Description

利用特定晶体管取向的CMOS制造方法
本发明的技术领域
本发明涉及半导体晶体管，特别是涉及半导体晶体管结构取向，其取向使电流方向平行于特定的结晶方向。
本发明的背景技术
互补金属氧化物半导体(CMOS)集成电路既包括N型器件(NMOS)，也包括P型器件(PMOS)，前者利用电子作为载流子，而后者利用空穴作为载流子。CMOS技术被应用于目前所制造的大部分集成电路中。
CMOS集成电路的一个重要性能指标，是空穴和电子的迁移率。要提高PMOS和NMOS两者的性能，这两种载流子的迁移率都应当尽可能地高。CMOS电路的总体性能同样取决于NMOS和PMOS的性能，从而，取决于空穴和电子的迁移率。
公知的是，在半导体材料上施加应力，例如在半导体材料硅上施加应力，会改变电子和空穴的迁移率，从而，会改变半导体材料上所形成的NMOS和PMOS的性能。迁移率的提高会导致性能的提高。但人们还发现，电子和空穴的迁移率，并不总是对应力做出相同的反应，从而，使加工工艺复杂化。此外，迁移率与应力之间的关系，还取决于结晶半导体材料的表面取向和应力及电流的方向。例如，就沿着{100}平面上的<110>方向的电流而言，纵向拉应力往往会提高电子的迁移率而降低空穴的迁移率。相反，就沿着{100}平面上的<100>方向的电流而言，纵向拉应力往往会提高电子和空穴两者的迁移率。
目前，半导体器件被取向，以使电流沿着{100}硅上的<110>方向来流动。这一点可参看图2，图2为一个半导体晶片201的俯视图。半导体晶片201通常用“{100}硅”来表示，硅晶片是目前所使用的主要半导体晶片。在现有技术中，相对于半导体晶片201来说，NMOS和PMOS晶体管203被这样取向，以使源极与漏极之间的电流方向与<110>方向一致。因此，晶体管203的取向，是如图2中所示的那样。
就这种取向而言，电子和空穴的迁移率，对纵向应力所做出的反应是相反的。也就是说，当沿着电流方向给硅基片施加应力时，或是电子的迁移率提高而空穴的迁移率下降，或是空穴的迁移率提高而电子的迁移率下降。因此，就这种排列而言，CMOS电路的总体性能并没有提高。
为此，要在不降低一种类型器件的载流子的迁移率的情况下，提高另一种类型器件的载流子的迁移率，就必须利用硅材料的选择性加应力技术。从而，可在晶体管203a而不是在晶体管203b的位置上，给晶片201施加应力，反之亦然。这需要昂贵的加工步骤，可能包括形成掩模、淀积或刻蚀。
附图说明
图1为示意图，表示硅的三种结晶取向；
图2为示意图，表示现有技术的半导体晶片上CMOS器件的取向；
图3为示意图，表示本发明的半导体晶片上CMOS器件的取向；
图4A为曲线图，表示P型{100}硅基片的压力电阻系数与电流方向之间的函数关系；
图4B为曲线图，表示N型{100}硅基片的压力电阻系数与电流方向之间的函数关系；
图5表示一个承受纵向拉应力的晶体管；
图6表示一个承受横向拉应力的晶体管。
详细说明
硅(Si)是目前电子工业最重要的半导体材料。用来制造硅晶片的大多数硅，都是利用单晶硅来制成的。这类硅晶片作为基片，在上面形成CMOS器件。这类硅晶片也被称之为半导体基片或半导体晶片。
在结晶硅中，组成这种固体材料的原子，是周期性地排列。如果这种周期性排列贯穿在整个固体材料中，这种材料就被定义为是由单晶硅所构成。如果这种固体材料是由无数个单晶区域所构成，这种固体材料则被称之为多晶材料。
硅，在用于集成电路中时，可以是下述三种形式之一：(1)单晶硅；(2)多结晶硅(多晶硅)；以及(3)非晶硅。正如前面所描述过的那样，硅晶片是被制造成单晶形式。
在晶体中，原子的周期性排列被称之为晶格。晶格也有体积，这个体积代表整个晶格，并被称之为在整个晶体内有规则地重复的晶胞。
硅具有金刚石立方体晶格结构，能够表示为两个贯通的面心立方体晶格。从而，对立方体晶格的简单形象化分析，能够扩展到说明硅晶体的特征。在本说明书的描述中，提到了硅晶体中的各个平面，特别是提到了{100}、{110}和{111}平面。
这些平面说明了硅原子平面相对于主晶轴线的取向。标号{xyz}称之为密勒(Miller)指向，是由硅晶面与主晶轴线交汇(intersects)的点的倒数(reciprocals)来确定。从而，图1示出了硅晶面的3种取向。在图1A中，硅晶面与x轴相交在位置1，而且永远不会与y轴或z轴相交。因此，这种结晶硅的取向是{100}。同样，图1B示出了{110}结晶硅，而图1C示出了{111}结晶硅。{111}和{100}取向是商业上所用的两种主要晶片取向。
需要指出的是，对于立方体晶体的任何一个指定平面，都有5个其他等效平面。因此，构成晶体基本晶胞的立方体六个面，全部被认为是{100}平面。标号{xyz}表示所有六个等效平面。
在本说明书中，还提到了晶体方向，特别是提到了<100>、<110>和<111>方向。这些方向被定义为是垂直于各个平面的法线方向。因此，<100>方向是垂直于{100}平面的方向。标号<xyz>表示所有六个等效方向。
正如前面所描述过的那样，在现有技术中，制造在{100}硅上的大部分MOS晶体管，其栅极的取向使电流方向平行于<110>方向。这一点可参看图2。
根据本发明，如图3所示，MOS晶体管被取向，以使电流实质上沿着<100>方向来流动。图3为利用{100}硅所制成的半导体晶片301的俯视图。形成在半导体晶片301上的晶体管器件表现为晶体管303a和晶体管303b。晶体管303a和晶体管303b的取向，是使晶体管源极与漏极之间的电流实质上沿着半导体晶片301上的<100>方向来流动的取向。显然，晶体管303a和晶体管303b并不是按照比例绘出的，而仅仅是示意性的。
因此，根据本发明的一个实施例，形成在硅晶片上的器件具有一种特定的器件取向，而且采用了一种可在器件沟道区域引起纵向拉应力的生产工艺。这种作用在沟道上的纵向拉应力，将在不降低空穴迁移率的情况下，提高电子的迁移率。
在现有技术中，器件被取向，以使电流实质上沿着{100}硅上的<110>方向来流动。就这种取向而言，电子和空穴的迁移率，对纵向应力所做出的反应是相反的。从而，CMOS电路的总体性能并不会提高。为此，采用了硅材料的选择性加应力技术，以在不降低一种类型器件的载流子的迁移率的情况下，提高另一种类型器件的载流子的迁移率。
通过器件的取向使器件电流沿着<100>方向来流动，能够减轻或逆转由于应力所造成的这种情况：对应于一种类型器件的载流子的迁移率的一定量的提高，另一种类型器件的载流子的迁移率会出现相对下降。这就不需要利用选择性加应力技术来实现令人满意的总体性能增益。本发明的取向使应力能够作为一种工具来提高CMOS电路性能。
硅的压力电阻系数，相对于电流方向而言，是各向异性的。图4A示出了半导体基片p型区域的压力电阻系数与{100}平面上的电流方向之间的函数关系，而图4B示出了半导体基片n型区域的压力电阻系数与{100}平面上的电流方向之间的函数关系。由于公知的是，NMOS晶体管和n型区域不仅性能相似而且压力电阻系数也相似，而且对PMOS晶体管和p型区域来说，也是如此。从而，图4A和图4B适用于NMOS和PMOS晶体管。
在施加应力时，压力电阻系数的变化，与不同方向上电阻的变化有关。正值表示对应于应力，电阻提高。电阻的变化是与迁移率的变化成反比，而迁移率又是与晶体管的速度成正比。因此，电阻较高会导致晶体管较慢。
纵向拉应力的定义是：在与电流方向相同的方向上，“拉伸”沟道。例如，图5中所示了一个晶体管601，它有一个栅极603、一个源极605和一个漏极607。当给栅极603施加一个适当电压时，源极605与漏极607之间的电流，沿着箭头609的方向来流动。纵向拉应力，应当是要沿着方向610拉开源极605和漏极607的应力。此外，纵向压应力，应当是要沿着方向612来拉近源极605和漏极607的应力。
横向拉应力的定义是：在垂直于电流的方向上，“拉伸”沟道。例如，图6中示出了一个晶体管701，它有一个栅极703、一个源极705和一个漏极707。当给栅极703施加一个适当电压时，源极705与漏极707之间的电流，沿着箭头709的方向流动。横向拉应力，应当是在垂直于电流方向709的方向711上的应力。
如图4B所示，当将一个纵向拉应力(用实线401表示)施加于一个半导体晶片的n型区域时，压力电阻系数在<100>方向上为最小(约为-100单位)。如图4A所示，当将一个相同的纵向拉应力(用实线403表示)施加于一个半导体晶片的p型区域时，压力电阻系数仅仅比中性条件(0单位)稍高。
因此，根据本发明的一个实施例，晶体管的取向应当使电流在<100>方向上流动，并且在<100>方向上施加纵向拉应力。这将会提高NMOS晶体管的速度，而不会影响PMOS晶体管。这种取向优于现有技术的<110>取向，在现有技术的取向中，在施加这种应力时，PMOS晶体管的性能会下降，从而，要获得总体增益，需要一种麻烦的选择性加应力工艺。
根据本发明的另一个实施例，在施加横向应力(用虚线405和407表示)时，晶体管器件的取向能够使电流在<110>方向上流动。对于PMOS晶体管来说，这给出了一个大约-70的数值，而对于NMOS晶体管来说，这给出一个大约-25的数值。但实际上，这难以实现，原因是晶体管的宽度通常是长度的许多倍。因此，施加在沟道侧面上的力，会在沟道的中部被大大减弱。
在本技术领域，给基片施加纵向拉应力的具体技术是公知的，因此，在本说明书中，不再对此进行详细说明。举例来说，在一个实施例中，使用一种高拉伸的氮化物(nitride)电介质。这种高拉伸的氮化物电介质，在此也被称之为用来施加拉应力的“应力器”结构。此外，在另一个实施例中，“应力器”结构也可以是一种拉伸的浅沟槽隔离(STI)填充物。虽然这两种“应力器”是作为实例给出，但本说明书中所使用的名词“应力器”，是代表任何一种能够引起拉应力的结构。此外，形成电流在<100>方向上流动的取向晶体管，也是较为简单的。例如，相对于现有技术的取向技术(就{100}硅晶片而言)，或是将基底半导体晶片转动45°，或是将制造掩模转动45°，即能够做到这一点。
虽然本说明书展示和说明了本发明的具体实施例及应用，但应当知道，本发明并不仅仅局限于在此所公开的具体结构和部件。对于本领域的普通技术人员来说，在不偏离本发明精神和范围的情况下，对本发明所公开的方法和系统的布置、运用及具体细节进行各种改进、变化和变动，是显而易见的。
由于根据上述详细说明能够进行各种改进。因此，不应当把在附属权利要求中所使用的名词，认作为是将本发明局限于在说明书和权利要求中所描述的具体实施例。相反，本发明的范围完全根据权利要求的解释原则由附属权利要求来确定。

Claims (22)

1.一种集成电路，包括：
NMOS器件，形成在半导体基片上；
PMOS器件，形成在所述半导体基片上，其中，所述NMOS器件和所述PMOS器件被取向，以使电流沿着所述半导体基片上的<100>方向流动，其中所述半导体基片的至少一部分处在由高拉伸的氮化物电介质所引起的拉应力下。
2.根据权利要求1所述的集成电路，其中，所述半导体基片是用{100}硅制成的。
3.根据权利要求1所述的集成电路，其中，所述拉应力为纵向拉应力。
4.根据权利要求1所述的集成电路，其中，所述NMOS器件和PMOS器件为晶体管。
5.一种装置，包括：
用{100}硅所制成的半导体基片；
PMOS晶体管，形成在所述半导体基片上，所述PMOS晶体管有用来输送电流的PMOS沟道，而且所述PMOS晶体管被取向以使电流在<100>方向上流动；
NMOS晶体管，形成在所述半导体基片上，所述NMOS晶体管有用来输送电流的NMOS沟道，而且所述NMOS晶体管被取向以使电流在<100>方向上流动；以及
应力器，它在所述NMOS沟道或所述PMOS沟道上引起纵向拉应力。
6.根据权利要求5所述的集成电路，其中，所述应力器为高拉伸的氮化物电介质或拉伸的浅沟槽隔离填充物。
7.一种方法，包括：
在半导体晶片上形成NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<100>方向流动；以及
将纵向拉应力引入到所述半导体晶片的至少一部分中。
8.如权利要求7所述的方法，其中所述在所述半导体晶片上形成所述NMOS器件和PMOS器件的步骤包括将所述半导体晶片自所述半导体晶片的<110>方向转动45度。
9.如权利要求7所述的方法，其中所述在所述半导体晶片上形成所述NMOS器件和PMOS器件的步骤包括将所述制造掩模自所述半导体晶片的<110>方向转动45度。
10.如权利要求7所述的方法，其中所述将所述纵向拉应力引入到所述半导体晶片中的步骤包括沿着所述半导体晶片的所述<100>方向施加高拉伸的氮化物电介质。
11.如权利要求7所述的方法，其中所述将所述纵向拉应力引入到所述半导体晶片中的步骤包括沿着所述半导体晶片的所述<100>方向施加拉伸的浅沟槽隔离填充物。
12.一种方法，包括：
在半导体晶片上形成NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<110>方向流动；以及
将横向拉应力引入到所述半导体晶片的至少一部分中。
13.如权利要求12所述的方法，其中所述将所述横向拉应力引入所述半导体晶片的步骤包括在垂直于所述半导体晶片的所述<110>方向的方向上将所述横向拉应力引入到所述半导体晶片中。
14.如权利要求12所述的方法，其中所述将横向拉应力引入所述半导体晶片的步骤包括在垂直于所述电流将流动的方向的方向上将所述横向拉应力引入到所述半导体晶片中。
15.一种装置，包括：
在半导体晶片上形成的NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<100>方向流动；以及
应力器，所述应力器被施加到所述半导体晶片的至少一部分上，以将纵向拉应力引入所述半导体晶片中。
16.如权利要求15所述的装置，其中所述应力器包括高拉伸的氮化物电介质。
17.如权利要求15所述的装置，其中所述应力器包括拉伸的浅沟槽隔离填充物。
18.如权利要求15所述的装置，其中所述NMOS器件或者所述PMOS器件中的至少一个包括沟道区域，并且其中所述应力器被施加在所述沟道区域中。
19.一种装置，包括：
在半导体晶片上形成的NMOS器件和PMOS器件，所述NMOS器件和所述PMOS器件所具有的取向将使得电流沿着所述半导体晶片的<110>方向流动；以及
应力器，所述应力器被施加到所述半导体晶片的至少一部分上，以将横向拉应力引入所述半导体晶片中。
20.如权利要求19所述的装置，其中所述应力器包括高拉伸的氮化物电介质。
21.如权利要求19所述的装置，其中所述应力器包括拉伸的浅沟槽隔离填充物。
22.如权利要求19所述的装置，其中所述NMOS器件或者所述PMOS器件中的至少一个包括沟道区域，并且其中所述应力器被施加在所述沟道区域中。
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