CN1794433A - 异质结构沟道绝缘栅极场效应晶体管的制造方法及晶体管 - Google Patents
异质结构沟道绝缘栅极场效应晶体管的制造方法及晶体管 Download PDFInfo
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Abstract
本发明涉及一种绝缘栅极场效应晶体管(T)，其包括窄的异质结构应变半导体沟道(4，5)，该沟道在栅极(6)和隐埋在基片(SB)中的介电块(91)之间延伸。
Description
技术领域
本发明涉及集成电路，更具体地说，涉及集成电路中的异质结构沟道晶体管的制造。
背景技术
直接在较大基片中制作的硅/硅锗异质结构半导体沟道晶体管是已知的。
然而，这种晶体管存在SCE(短沟道效应)和DIBL(漏极感应势垒降低效应)的缺点。更准确地说，当晶体管栅极的长度下降时，由于源极和漏极间的势垒降低，沟道中心的电势变化很大因而晶体管的阈值电压也会改变。这就是SCE效应。在此基础上又加上漏极电势的作用，就会进一步降低势垒，这就是DIBL效应。
发明内容
本发明旨在提供上述问题的解决方案。
本发明的目的是提供一种晶体管，在克服SCE和DIBL效应的同时改善沟道中载流子迁移率，尽管载流子采用隐埋传导。
本发明的另一目的是提高nMOS器件中穿过拉伸应变硅层的电子的传导性。
本发明的再一目的是提高pMOS器件中穿过压缩应变硅和硅锗层的空穴的传导性。
因此，本发明提供一种制备绝缘栅极场效应晶体管的方法，其包括：
a)在基片的活性区上沉积一层相对于构成活性区的材料能选择性地除去的材料；
b)在能选择性地除去的材料层上形成窄的异质结构的应变半导体沟道；
c)在该沟道上形成绝缘栅极；
d)有选择地除去能选择性地除去的材料层，以便在该沟道下形成空腔；
e)在所述空腔内沉积介电材料以便形成介电块；以及
f)从基片的活性区起形成源极区和漏极区，与沟道相接触并分别在其一边延伸，于是介电块被隐埋在沟道下。
通过把窄的异质结构应变半导体沟道与隐埋在所述沟道下的介电块结合起来并界定后者，使沟道中的载流子获得更好的迁移率，同时克服了现有技术中晶体管的问题，即短沟道和DIBL效应。
本领域的技术人员知道怎么选择沟道厚度以便得到薄的沟道。这里提示一下，这种沟道的厚度最好小于10纳米。
按照实施本发明的一种方法，基片的活性区包含硅锗合金，其锗含量与硅含量的比率随着与基片表面的接近而增长，而由能选择性地除去的材料形成的层是一种从基片的活性区上表面外延生长得到的应变硅层。
例如，沟道可以这样形成：在应变硅层上外延生长第一硅锗合金层以便得到压缩的硅锗合金层，以及在所述第一层上外延生长第二硅层以便得到拉伸的应变硅层。
按照实施本发明的一种实施方法，通过含有硅的材料的外延生长形成源极和漏极区。
本发明还提供一种绝缘栅极场效应晶体管，其包含窄的、厚度为1到10纳米之间的异质结构半导体沟道，该沟道包含位于基片活性区之上的栅极和介电块之间的硅锗合金层和应变硅层。
按照一个实施例，该应变硅层的厚度范围在1到5纳米之间。
附图说明
为了进一步理解本发明的其它优点和特征，下面结合附图对本发明的实施方式和实施例进行详细说明。但本分明并不限于此。
附图中：
图1到7示意性地图示了按照本发明一个实施例的方法的主要步骤；以及
图8示意性地显示了集成电路中按照本发明的绝缘栅极场效应晶体管。
具体实施方式
现在更详细地说明按照本发明一个实施例的方法的主要步骤。
图1中，在例如由硅制成的基片SB上，通过外延形成硅锗合金层1，该合金中锗含量与硅含量的比率随着与基片SB表面的接近而增长。组成该合金的硅和锗对应于分子式Si1-xGex，其中x随着与基片SB表面的接近而变化，例如从0变到0.2。
活性区AZ形成于层1中两个隔离区2之间，所述隔离区可以是隔离沟。比如，这些隔离沟可以是DTI(深沟隔离)类型的深沟或者STI(浅沟隔离)类型的浅沟。
硅层3通过在活性区AZ上选择性的外延生长形成(图2)，由于层3中硅的晶格和活性区AZ中硅锗合金的晶格之间的晶格失配，所述硅处于应变状态。提示一下，层3的厚度可以是15纳米，但更一般地是在10纳米到40纳米之间。
以类似的方法，压缩的应变硅锗合金层4通过在层3上选择性的外延生长形成。在这点上，选择层4中锗的百分含量比活性区AZ中锗的百分含量大。例如，层4的厚度可以是3纳米，但更一般地是在1纳米到5纳米之间。
然后拉伸状态的应变硅层5在层4上通过选择性的外延生长形成。例如，层5的厚度可以是3纳米，但更一般地是在1纳米到5纳米之间。
接着，通过已知的方法形成栅极区6，该栅极区6可以用多晶硅制成。该栅极区6由间隔层7环绕(图3)，并通过硅氧化物(栅极氧化物)层71与拉伸状态的硅层5分隔开。
图4中，通过已知手段，例如通过非等向性蚀刻，蚀刻分别为压缩状态的硅锗合金层4和拉伸状态的应变硅层5，使用栅极区6和间隔层7作为掩模。附加的间隔层8分别形成在间隔层7和层4、层5的一边——所述间隔层随后用作掩模。
然后，除去应变硅层3(图5)，这样在压缩状态的硅锗合金层4与活性区AZ表面之间留下空腔9。该除去操作可以通过已知手段实施，比如通过用CF4，CH2F2，N2，O2类型的等离子进行选择性的各向同性等离子蚀刻。压力和温度条件可以由本领域的技术人员调节以便得到所需的蚀刻速率。比如，蚀刻可以在25℃和大气压下进行。
接着，介电(比如SiO2)层90沉积在活性区AZ表面上和空腔9中(图6)。
使用间隔层8作掩模，通过已知手段蚀刻所述介电层90(图7)，比如通过非等向性蚀刻。
半导体区10和11通过选择性外延生长分别形成于晶体管的一边(图8)，从活性区AZ开始直到与拉伸状态应变硅层5的表面处于同水平高度处。然后在半导体区10和11中注入掺杂剂以便形成源极和漏极区。
现隐埋在基片中的介电块91，具有与原来应变硅层3相同的厚度，也就是说典型的是15纳米，但更一般地可以在10纳米到40纳米之间。
图8显示包含本发明的绝缘栅极场效应晶体管T的集成电路IC。
该集成电路包含基片SB，该基片SB上有硅锗合金层1，其锗含量与硅含量的比率随着与基片SB表面的接近而增长。
晶体管T在所述层1的活性区AZ上形成并位于两隔离区2之间。所述晶体管包括窄的异质结构应变半导体沟道，该沟道包含压缩的硅锗合金层4和拉伸的硅层5，并在栅极6和隐埋在基片SB中的介电块91之间延伸。
Claims (7)
1.一种制备绝缘栅极场效应晶体管(T)的方法，包括：
a)在基片(SB)的活性区(AZ)上沉积一层(3)相对于构成活性区(AZ)的材料能选择性地除去的材料；
b)在能选择性地除去的材料层(3)上形成窄的异质结构应变半导体沟道(4，5)；
c)在该沟道(4，5)上形成绝缘栅极(6)；
d)有选择地除去能选择性地除去的材料层(3)，以便在该沟道(4，5)下形成空腔(9)；
e)在所述空腔(9)内沉积介电材料以便形成介电块(91)；以及
f)从基片(SB)的活性区(AZ)形成源极区(10)和漏极区(11)，与沟道(4，5)相接并分别在其一侧延伸，于是介电块(91)被隐埋在沟道(4，5)下。
2.根据权利要求1所述的方法，其中，所述沟道(4，5)的厚度小于10纳米。
3.根据权利要求1或者2所述的方法，其中，所述基片(SB)的活性区(AZ)包含硅锗合金，其锗含量与硅含量的比率随着与基片(SB)表面的接近而增长，并且，由能选择性地除去的材料形成的层(3)是一种从基片(SB)的活性区(AZ)上表面外延生长而得到的应变硅层。
4.根据权利要求3所述的方法，其中，所述沟道(4，5)的是这样形成的：在应变硅层(3)上外延生长第一硅锗合金层以便得到压缩的硅锗合金层(4)，以及在所述第一层上外延生长第二硅层(5)以便得到拉伸的应变硅层。
5.根据权利要求1至4任一项所述的方法，其中，所述源极(10)和漏极(11)区由含有硅的材料外延生长而成。
6.一种集成电路，包含一种绝缘栅极场效应晶体管(T)，该晶体管包含窄的异质结构半导体沟道(4，5)，该沟道厚度在1到10纳米之间，该沟道包含硅锗合金层(4)和应变硅层(5)，它们位于基片(SB)活性区(AZ)上的栅极(6)和介电块(91)之间。
7.根据权利要求6所述的集成电路，其中，应变硅层的厚度在1到5纳米之间。
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| CN102437127A (zh) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | 基于硅-锗硅异质结的单晶体管dram单元及其制备方法 |
| CN102437126A (zh) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | 基于源体异质结的单晶体管dram单元及其制备方法 |
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| DE102006042617B4 (de) * | 2006-09-05 | 2010-04-08 | Q-Cells Se | Verfahren zur Erzeugung von lokalen Kontakten |
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| US9093530B2 (en) * | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
| EP2930752A3 (en) * | 2014-04-08 | 2016-01-20 | IMEC vzw | Method for manufacturing a transistor device |
| RU2621370C2 (ru) * | 2015-09-18 | 2017-06-02 | федеральное государственное бюджетное образовательное учреждение высшего образования Кабардино-Балкарский государственный университет им. Х.М. Бербекова | Способ изготовления полупроводникового прибора |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100332108B1 (ko) * | 1999-06-29 | 2002-04-10 | 박종섭 | 반도체 소자의 트랜지스터 및 그 제조 방법 |
| WO2001093338A1 (en) * | 2000-05-26 | 2001-12-06 | Amberwave Systems Corporation | Buried channel strained silicon fet using an ion implanted doped layer |
| FR2838237B1 (fr) * | 2002-04-03 | 2005-02-25 | St Microelectronics Sa | Procede de fabrication d'un transistor a effet de champ a grille isolee a canal contraint et circuit integre comprenant un tel transistor |
| WO2003105204A2 (en) * | 2002-06-07 | 2003-12-18 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
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2005
- 2005-09-14 EP EP05291905A patent/EP1638149B1/fr not_active Expired - Fee Related
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188201B (zh) * | 2006-11-24 | 2010-11-10 | 日产自动车株式会社 | 制造半导体器件的方法 |
| CN102437127A (zh) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | 基于硅-锗硅异质结的单晶体管dram单元及其制备方法 |
| CN102437126A (zh) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | 基于源体异质结的单晶体管dram单元及其制备方法 |
| CN103515441A (zh) * | 2012-06-25 | 2014-01-15 | 三星电子株式会社 | 具有嵌入式应变感应图案的半导体器件 |
| CN103515441B (zh) * | 2012-06-25 | 2018-04-27 | 三星电子株式会社 | 具有嵌入式应变感应图案的半导体器件 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1638149A3 (fr) | 2008-11-05 |
| EP1638149A2 (fr) | 2006-03-22 |
| US20060081876A1 (en) | 2006-04-20 |
| US7436005B2 (en) | 2008-10-14 |
| EP1638149B1 (fr) | 2011-11-23 |
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