CN101764062B - 具有高掺杂源/漏极和应变增强器的n型场效应晶体管 - Google Patents
具有高掺杂源/漏极和应变增强器的n型场效应晶体管 Download PDFInfo
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Abstract
一种具有高掺杂源/漏极和应变增强器(booster)的N-FET结构和制造方法，该方法提供具有锗沟道区的衬底，在所述锗沟道区上方形成栅极电介质，并且在所述栅极电介质上方形成栅电极。牺牲栅电极间隔物设置在所述栅极电介质和所述栅电极的侧壁上，在所述衬底上蚀刻空腔，并且空腔在牺牲栅电极间隔物下方延伸。在形成过程中原位掺杂Si1-xGex源/漏极区，其中x＜0.85。
Description
技术领域
本发明通常涉及一种半导体器件制造方法，尤其涉及一种具有高掺杂源/漏极和应变增强器(booster)的NFET的结构及其制造方法。
背景技术
半导体工业的一个重要目标是，在增加半导体性能的同时减少半导体器件的尺寸。平面型晶体管，例如金属氧化半导体场效应晶体管(MOSFET)可很好地适用于高密度的集成电路。
利用应变装置技术，能够形成更高速的MOSFET晶体管。一种制造方法涉及位于弛豫(relaxed)锗化硅底层上方的硅的外延生长。当硅层的晶格被伸展以与底层锗化硅的较大的晶格常数近似时，在硅中引起拉伸应变。相反地，利用具有较小晶格常数的固溶物，例如碳化硅，能够导致压缩应变。
一种应变装置技术的方法是将一层锗化硅(SiGe)沉积在体硅晶片上。锗化硅的晶体结构为金刚石形，与硅的晶体结构相同。但是，锗化硅中的晶格常数大于硅中的晶格常数。因此，当将薄的硅层(薄于临界厚度)沉积到锗化硅层的上方时，硅的晶格可以发生应变，从而将硅原子与锗化硅层中的原子对齐。应变硅中的电子经受更少的阻抗，并且相比未应变的硅流动的更快，因此增加了晶体管的性能。
又一种建立高速MOSFET晶体管的方法包括锗(Ge)MOSFET晶体管。锗MOSFET晶体管具有较高的本征载流子迁移率，这改善了器件的速度。但是，源极/漏极区的掺杂激活可能是当前锗MOSFET晶体管存在的问题，尤其是N型场效应晶体管(N-FET)。锗N-FET晶体管的外部电阻可以大于传统N-FET晶体管的外部电阻。外部电阻包括与欧姆接触(金属到半导体以及半导体到金属)有关的电阻、源极/漏极区本身内部的电阻、沟道区与源极/漏极区之间区域(例如源极/漏极伸展区)的电阻以及由于在最初的衬底-外延层界面位置的杂质(碳、氮、氧)污染造成的界面电阻的总和。上述外部电阻会降低晶体管的性能。
例如，如果N-FET的外部电阻较高，则可能负面地影响N-FET的驱动电流。驱动电流为一个金属氧化半导体(MOS)晶体管的漏极电流，其中该MOS晶体管具有连接到电源电压的栅电极和漏极，以及接地的源极和体区(bulk)。驱动电流是一个重要的器件性能参数。
另外，在具有高外部电阻的N-FET结构中，不能够获得用于漏极感应势垒下降(DIBL)的希望较低值。DIBL是弱反型(weakinversion)体系中的晶体管测量。在源极和沟道区之间存在势垒，势垒的高度是源极与沟道区之间的漂移电流和扩散电流之间平衡的结果。如果施加高漏极电压，则可以减少势垒高度，进而导致漏电流的增加。因此，漏电流不仅由栅电极电压控制，还由漏极电压控制。通过取决于漏极电压的阈值电压减少，能够解决这种寄生效应。
由于需要高沟道掺杂将寄生的串联源/漏电阻(Rsd)减少到可接受的数值，因此，在使用浅源/漏结深度的同时，缩微平面的体块型互补金属氧化半导体(COMS)方面就存在挑战。接着，需要的是一种具有减少源/漏电阻(Rsd)的浅的高掺杂源/漏极，以提供有利的晶体管应变。
发明内容
通过一种具有高掺杂源/漏极和应变增强器的N型场效应晶体管(N-FET)结构及方法，本发明通常可以解决或避免上述及其他问题，并通常获得技术优点。
根据本发明的实施例，提供了一种制造N型场效应晶体管(N-FET)的方法。该方法提供具有锗沟道区的衬底，在所述锗沟道区上方形成栅极电介质，并且在所述栅极电介质上方形成栅电极。牺牲栅电极间隔物设置在所述栅极电介质和所述栅电极的侧壁上，在所述衬底上蚀刻空腔，并且空腔在牺牲栅电极间隔物下方延伸。在形成过程中原位掺杂Sil-xGex源/漏极区，其中x＜0.85。
本发明优选实施例的优点包括：提供一种具有减小寄生串连源/漏电阻(Rsd)和浅源/漏极结深度的高速金属氧化半导体场效应晶体管(MOSFET)。
本发明的又一个优点是在N-FET沟道区上提供拉伸应变，从而增加载流子迁移率，由此增加驱动电流。
为了更好地理解下文中对本发明的详细描述，上文广泛地概述了本发明的示例实施例的特征及技术优点。本发明实施例的附加特征和优点将在下面的描述中给出，这些特征和优点形成本发明保护范围要求的目标。本领域的普通技术人员应当了解，文中公开的概念与特定实施例可以容易地作为修改或设计其他结构或步骤的基础，以实现本发明相同的目的。本领域的普通技术人员应当了解，这样的等同结构不脱离如所附权利要求限定的示例实施例的精神和范围。
附图说明
为了更全面地理解本发明的示例实施例及其优点，现在将结合附图给出下面的详细说明，其中：
图1a为用于注入磷的磷浓度-深度图表，图1b为多层Ge/Si结构中的磷浓度图表，图1c为SiGe层中的磷浓度图表；
图2为SiGeN-FET源/漏极区中的磷浓度图表；
图3-9为形成本发明实施例的具有Ge沟道区N-FET的选择工艺步骤的剖视图；
图10为本发明另一实施例的具有Si1-xGex沟道区的N-FET剖视图。
除非另有说明，不同附图中对应的数字及符号通常用于指示相应的元件。绘制的附图是为了清楚阐明发明优选实施例的相关方面，不必须按照比例绘制。
具体实施方式
下面，将对本发明的优选实施例的实现及使用做出讨论。但是，应当了解本发明提供许多可应用的发明概念，这些发明概念可以体现在各种特定环境下。文中讨论的特定实施例仅阐述了本发明的实现及使用的特定方式，并不用来限制本发明的保护范围。
本发明将结合特定环境的示例实施例，即具有高掺杂源/漏极和应变增强器的锗(Ge)N型场效应晶体管(N-FET)给出说明。但是，本发明也可以应用于其他半导体器件。
现在参考图1a，该图显示了用于注入磷的磷浓度-深度图表。图1b为多层Ge/Si结构中的磷浓度图表，图1c为SiGe层中的磷浓度图表。
首先参考图1a，y轴表示每立方厘米(cm3)的磷浓度，x轴表示用于磷注入的Ge衬底的测量深度，单位为纳米(nm)。曲线1到5表示不同注入剂量的注入浓度(全部以千电子伏(keV)注入)。曲线1对应3E+13的注入剂量，曲线2对应1E+14的注入剂量，曲线3对应3E+14的注入剂量，曲线4对应1E+15的注入剂量，以及曲线5对应5E+15的注入剂量。曲线1显示了磷浓度从20nm的深度在1E+19的范围内减少到大约40nm深度的1E+18的范围。此外，曲线2、3和4为显示在磷浓度-注入剂量中预期增加的类似曲线。但是，曲线5显示了不规则部6，该不规则部6表示在大约18nm深度的注入衬底中大于2E+20的范围内的磷浓度出现促降。对于高性能可靠的半导体器件来说，这种在理想磷浓度范围内出现的非均匀性是不理性的，因此必须采用非注入的其他方法来掺杂N+源极/漏极区。
下面转向参考图1b，其中y轴表示每立方厘米的浓度，x轴表示单位为的测量深度。划分表格的线102表示位于左侧的Ge层与位于右侧的Si层之间的分界面。Ge浓度曲线104表示位于Ge层中的期望高浓度和位于Si层中的低浓度，Si曲线103表示位于Ge层中的低浓度Si和位于Si层中的高浓度Si。浓度曲线105显示了Ge层和Si层中的磷浓度，位于1E+16到1E+17之间的磷浓度贯穿整个Ge层。在表面深度(见区域106)存在峰值磷浓度，并且在Ge层与Si层之间的分界处(见区域108)存在峰值磷浓度。对于用作本发明实施例的源/漏极结构，磷浓度水平是不希望的低和不均匀。因此，清楚地可知纯Ge或纯Si都不是用于高掺杂源/漏极区的最佳选择。
但是，相反参考图1c，可以在SiGe层中观察到不均匀的掺杂区。沿着单位为原子/cm3的y轴显示了SiGe层的磷(P)浓度。注意位于SiGe层两侧的Si盖层与Si体层的标记。SiGe层的测量深度如单位为μm的x轴所示。从图表显然可知，图示区域110对应的SiGe层的磷浓度大体上是均匀的。区域110中的磷浓度大约为1E+18。因此，SiGe层显示了理想的均匀掺杂轮廓，以用于实现n沟道MOSFET的SiGe源/漏极结构。
现在参考图2，该图显示了SiGe层中百分比Ge的磷浓度图表。图2所示的三个曲线表示三个类似的数据系列。这里将曲线150作为三个曲线的代表进行讨论。曲线150表示SiGe层中百分比Ge的平均磷浓度。y轴显示了单位为原子/cm3的磷浓度，x轴表示SiGe层中Ge的百分比。从SiGe层中提取的所有的数据点是通过利用原位(in-situ)磷处理工艺产生。
具有表示Ge百分比低于15％的数据的曲线150显示磷浓度低于大约5E+19原子/cm3。具有表示Ge百分比高于85％数据的曲线150显示磷浓度低于大约3E+19原子/cm3。但是，具有表示Ge百分比在大约15％和85％之间数据的曲线150显示磷浓度为大约1E+20原子/cm3，该浓度是可接受的高度并且是均匀的。因此，SiGe层中理想的Ge百分比范围为大约15％到大约85％，或者更好的是大约50％到85％。通过减少晶体的不合适缺陷，更高的Ge含量可以改善缺陷密度。
图3-9显示了制造本发明实施例的Ge沟道区N-FET的选择处理步骤剖视图。现在参考图3，该图显示了一个选择处理步骤的N-FET剖视图。衬底202可以包括体块(bulk)Ge、位于Si或者绝缘层上锗(GOI)上的Ge层。在图3-9所示的实施例中，衬底202为体块锗。
栅极电介质204可以包括氧化硅、氧化锗、氮化锗、氮氧化锗、(Si，Ge)Ox、高介电常数(k)材料或者它们的组合。高k材料可以具有大约大于4并且最好大约大于7的介电常数，高k材料可以包括金属氧化物，例如HfO2，HfSiOx，HfZrOx，HfZrSiOx，HfSiON，Al2O3，LaAlO3，ZrO2，硅酸锆(Zrsilicate)等。栅电极206可以包括掺杂或者非掺杂多晶硅，或者其他导电材料例如金属或者硅化物。硬质掩模208可以是在栅电极光刻工艺过程中用于定义栅电极的氧化物或者氮化物。衬垫层(linerlayer)210可以包括氧化物、其他绝缘层或者类似物。间隔层(spacerlayer)212可以包括氮化物、其他绝缘层或者类似物。
图4-9显示了如图3类似的N-FET，并具有与图3重复和编号的相同层。因此，这些层不再结合图3-9给出详细描述。在图4中，在源/漏极蚀刻工艺准备过程中将部分衬垫层210和部分间隔层212从源/漏极区除去，衬垫层210和间隔层212可以利用现有技术公知的标准图案化蚀刻(图中未显示图案)、湿蚀刻或者干蚀刻被蚀刻。
图5显示了轻掺杂源/漏极(LDD)以及/或者环状注入(haloimplanted)区214。根据特定设计限制以及所需的电学效果，掺杂物浓度可以是每立方厘米1E+15到1E+19。但是，注入可以一个斜角度或者多个斜角度执行，从而将LDD或者环状注入区塞入栅极电介质的下方。
现在参考图6，该图显示了在源/漏极区216蚀刻之后的N-FET剖视图。蚀刻工艺可以是湿或干的等容积蚀刻，并且可以使用氢氧化钾(KOH)蚀刻剂。注意，该蚀刻对衬垫层212下方的衬底进行底切，仅部分原先的注入LDD及/或环状注入区214保留。此外，注意直接位于栅极电介质下方的衬底区域保持为完好的，从而形成沟道区224。
图7显示了本发明实施例的填充有原位(in-situ)磷掺杂的Si1-xGex(x＜0.85)的源/漏极区216。源/漏极区216在沟道区224上产生拉伸应变。沟道区224上的拉伸应变能够使得电荷载流子(这里是电子)以更大的速度穿过沟道区224。此外，如图1c表格的数据显示，源/漏极区216为原位掺杂。此外，磷原位掺杂可以更均匀，并且相比现有技术，更多的掺杂物可以被活化。在另一个实施例中，其他n型掺杂物可以用来替换磷，例如包括砷(As)和锑(Sb)。
使用例如用于Ge源极的GeH4或者Ge2H6的气体，以及用于Si源极的SiH4，SiH2Cl2，Si2H6和CH3SiH3气体，可以在外延生长炉中形成原位掺杂源/漏极区216。形成的薄膜中Ge的百分比位于大约15％到大约85％之间，为了更好的工艺控制，最好位于50％到85％之间。利用具有大约0.005Pa到大约0.5Pa之间局部压力的PH3气体，可以将掺杂物引入薄膜中。也可以使用例如He、N2以及H2的运载气体。该工艺可以在低压环境中执行，例如低于大约100托的环境，或者大气压环境。该工艺的温度可以位于大约350℃到大约650℃之间。产生的磷掺杂浓度可以位于5E+19到2.5E+20原子/cm3之间。源/漏极区可以与衬底202(本实施例中为Ge体块)的表面同平面，或者源/漏极区可以高于衬底202。
现在参考图8，该图显示了形成侧壁间隔物220之后的N-FET剖视图。在除去衬垫层210之后，可以新形成栅电极衬垫218，或者栅电极衬垫218可以通过衬垫层210蚀刻而形成。栅电极衬垫218为隔离层，该层为包括氧化物、氮化物或其他类似物的电介质。侧壁间隔物220可以包括例如氮化物、氧化物或者其他的电介质，并且利用公知的现有技术形成。
图9显示了本发明第一实施例的在浅SiGe源/漏极区具有高掺杂浓度的N-FET。衬底为Ge体硅或者硅上Ge层。沟道区224为经历拉伸应变的Ge。源/漏极区216为磷原位掺杂Si1-xGex，其中x＜0.85，或者更好的是0.50＜x＜0.85。第一实施例200显示了在栅极电介质下方稍微延伸的环状注入区214。此外，第一实施例200显示了位于栅极电介质206上方和源/漏极区216上方的硅化物222。硅化物222可以包括NiGe、CoGe、TiGe、WGe、包括Si的材料或其他类似材料。
图10显示了本发明第二实施例的N-FET剖视图，衬底302可以包括位于Si上的Si1-yGey，并且源/漏极可以包括Si1-xGex，其中y小于1且小于x。浅沟槽隔离(STI)区与晶体管相邻。栅极电介质304可以包括氧化锗、氮氧化锗、高k材料或者它们的组合。高k材料可以具有大约大于4的介电常数，最好是大约大于7。高k材料可以包括金属氧化物，例如HfO2，HfSiOx，HfZrOx，HfZrSiOx，HfSiON，Al2O3，LaAlO3，ZrO2，硅酸锆(Zrsilicate)等。栅电极306可以包括掺杂或者非掺杂多晶硅，或者其他导电材料例如金属或者硅化物。
栅电极衬垫318可以是隔离层，例如是包括氧化物、氮化物或者类似物的电介质。侧壁分隔物320可以包括例如氮化物、氧化物或者类似物的电介质，并且利用现有的公知技术形成。
使用例如用于Ge源极的GeH4或者Ge2H6的气体，以及用于Si源极的SiH4，SiH2Cl2，Si2H6和CH3SiH3气体，可以在外延生长炉中形成原位掺杂源/漏极区316。形成的薄膜中Ge的百分比最好位于大约15％到大约85％之间。利用具有大约0.005Pa到大约0.5Pa之间局部压力的PH3气体，可以将掺杂物引入薄膜中。也可以使用例如He、N2以及H2的运载气体。该工艺可以在低压环境中执行，例如低于大约100托的环境，或者大气压环境。该工艺的温度可以位于大约350℃到大约650℃之间。产生的磷掺杂浓度可以位于5E+19到2.5E+20原子/cm3之间。源/漏极区可以与衬底302(本实施例中为SiGe层)的表面同平面，或者源/漏极区可以高于衬底302。
第二实施例300显示了在栅极电介质下方稍微延伸的环状注入区314，并且沟道区324从源/漏极区316下方经受拉伸应变。此外，第二实施例300显示了位于栅电极306上方和位于源/漏极区316上方的硅化物322。硅化物322可以包括NiGe、CoGe、TiGe、WGe、包括Si的材料或其他类似材料。
为了减少串联电阻并且提供良好的接触界面，可以在上述实施例中选择使用额外的深源/漏极注入。深源/漏极注入的最佳设计意味着它们不会显著影响N-FET晶体管沟道区中的器件性能。
此外，在其他实施例中，源/漏极区可以具有梯度的Ge分布，其中靠近衬底表面的Ge含量最低，并且随着源/漏极区的深入而增加。在其他实施例中，源/漏极区可以包含碳，例如Si1-xGexC，其中x＜1。
本发明实施例的优点包括提供一种能够最大程度减小浅源/漏极区串联电阻的方法和结构。此外，浅源/漏极区在N-FET沟道撒谎那个提供拉伸应变。其他优点包括改善的驱动电流和漏极感应势垒下降(DIBL)器件参数。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (15)
1.一种制造N型场效应晶体管的方法，所述方法包括：
提供具有锗沟道区的衬底；
在所述锗沟道区上方形成栅极电介质；
在所述栅极电介质上方形成栅电极；
在所述栅电极和所述栅极电介质上沉积牺牲栅电极间隔物；
在所述衬底上蚀刻空腔，其中所述空腔在牺牲栅电极间隔物下方延伸；
在所述空腔中形成原位掺杂的Si1-xGex源/漏极区，其中0.50<x<0.85；以及
在所述原位掺杂的Si1-xGex源/漏极区之上形成锗的硅化物。
2.如权利要求1所述的方法，其中所述衬底包括体块锗、绝缘层上锗或者硅上锗。
3.如权利要求1所述的方法，还包括在形成所述原位掺杂的Si1-xGex源/漏极区过程中减少x的步骤，以形成具有梯度锗的源/漏极区；或者x在形成所述原位掺杂的Si1-xGex源/漏极区的整个过程中基本一致。
4.如权利要求1所述的方法，其中所述空腔被蚀刻到低于120纳米的深度。
5.如权利要求4所述的方法，其中所述空腔被蚀刻到在10纳米到100纳米之间的深度。
6.如权利要求1所述的方法，其中所述原位掺杂的Si1-xGex源/漏极区还包括碳，所述原位掺杂的Si1-xGex源/漏极区被掺杂有磷、砷、锑或者它们的组合，其中所述原位掺杂的Si1-xGex源/漏极区具有的N型浓度大于1E+20原子/cm3。
7.如权利要求1所述的方法，还包括在所述栅电极之上形成锗的硅化物。
8.如权利要求1所述的方法，其中形成所述栅极电介质包括沉积氧化锗、氮氧化锗、高k材料或者它们的组合。
9.如权利要求1所述的方法，其中在形成所述原位掺杂的Si1-xGex源/漏极区中使用第一气体，所述第一气体包括GeH4或者Ge2H6并具有0.05Pa到3Pa之间的局部气压；或者在形成所述原位掺杂的Si1-xGex源/漏极区中使用第二气体，所述第二气体包括PH3并具有0.005Pa到0.5Pa之间的局部气压。
10.一种N型场效应晶体管，包括：
具有锗沟道区的衬底；
位于所述锗沟道区上方的栅极电介质；
位于所述栅极电介质上方的栅电极；
包括Si1-xGex的源/漏极区，设置在邻近所述沟道区的所述衬底的蚀刻空腔内的Si1-xGex具有大于1E+20原子/cm3的N型浓度，其中0.50<x<0.85；以及
在所述Si1-xGex的源/漏极区之上形成的锗的硅化物。
11.如权利要求10所述的N型场效应晶体管，其中所述衬底包括体块锗、绝缘层上锗或者硅上锗，所述源/漏极区还包括碳。
12.如权利要求10所述的N型场效应晶体管，其中所述源/漏极区具有10纳米到120纳米之间的深度。
13.如权利要求10所述的N型场效应晶体管，其中从所述源/漏极区表面到所述源/漏极区底面，x具有从小到大的梯度。
14.一种半导体器件，包括：
具有锗沟道区的衬底；
位于所述衬底上方的栅极电介质；
形成在所述栅极电介质上方的栅电极；
包括设置在所述衬底上的蚀刻区域内的Si1-xGex的n掺杂源/漏极区，其中0.50<x<0.85；以及
在所述Si1-xGex的n掺杂源/漏极区之上形成的锗的硅化物。
15.如权利要求14所述的半导体器件，其中所述n掺杂源/漏极区为原位掺杂，并具有大于1E+20原子/cm3的磷浓度。
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