CN1905211A - 应变沟道晶体管及其制造方法 - Google Patents

应变沟道晶体管及其制造方法 Download PDF

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CN1905211A
CN1905211A CNA2006100995072A CN200610099507A CN1905211A CN 1905211 A CN1905211 A CN 1905211A CN A2006100995072 A CNA2006100995072 A CN A2006100995072A CN 200610099507 A CN200610099507 A CN 200610099507A CN 1905211 A CN1905211 A CN 1905211A
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丁明镇
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DB HiTek Co Ltd
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Abstract

根据本发明的应变沟道晶体管包括：半导体基片；半导体层，具有大于所述半导体基片的晶格常数的晶格常数，并且形成在所述半导体基片上；应变沟道层，形成在所述半导体层上；以及一对外延层，形成在所述应变沟道层的两侧上以改变所述应变沟道层的晶格结构。由于沟槽区形成在所述应变沟道层中并且所述外延层形成在所述沟槽区中，所述应变沟道层的晶格距离通过来自所述外延层的应力而变宽，并最终提高通过沟道的电荷的迁移率。

Description

应变沟道晶体管及其制造方法
此申请要求了于2005年7月26日提交的韩国申请No.10-2005-0067885的优先权，其通过引用整体结合于此。
技术领域
本发明涉及一种半导体器件及其制造方法，并且更具体地，涉及一种应变沟道晶体管及其制造方法，其中电荷的迁移率得以提高。
背景技术
为了满足晶体管的低功率消耗和高工作速度的趋势，已开发了应变(strained)沟道晶体管，其沟道形成为具有大的晶格参数，从而提高通过沟道的电荷的迁移率。
通常，具有第二晶格常数的锗层形成在具有第一晶格常数的硅基片上，并且硅层另外形成在锗层上，使具有大于第一晶格常数的晶格常数的硅层可以形成在硅基片的顶上。因此，硅层可以形成为具有大于硅基片的晶格常数的晶格常数的晶体管的应变沟道层。
图1是传统应变沟道晶体管的横截面视图。参见图1，具有应变沟道的传统晶体管包括：锗层12，形成在具有第一晶格常数的硅基片10上；以及硅层14，形成在锗层12上。这里，锗层12具有大于硅基片10的第一晶格常数的第二晶格常数。
因为硅层14外延地生长在具有大于典型硅材料的晶格常数的晶格常数的锗层12上，硅层14的晶格常数变大，从而形成应变层。隔离层16形成在包括硅基片10、锗层12和应变硅层14的基片上，限定有源区域。另外，栅图案18、源区20s和漏区20d形成在有源区域的硅层14中。因为晶体管的沟道形成在作为硅基片的顶层的应变硅层14中，通过该沟道的电荷的迁移率高于通过普通硅层的电荷的迁移率。
但是，随着晶体管的沟道长度的减小，存在缺点：在由空穴通过沟道的运动来传送信号的PMOS(P沟道金属氧化物半导体)晶体管中，通过沟道的电荷(特别是空穴)的迁移率恶化，即使沟道形成在应变硅层中。
发明内容
因此，本发明的一个目的是提供一种其中通过沟道的电荷的迁移率可得以提高的应变沟道晶体管及其制造方法。
为了实现上述目的，根据本发明的应变沟道晶体管包括：半导体基片；半导体层，具有大于半导体基片的晶格常数的晶格常数，并且形成在半导体基片上；应变沟道层，形成在半导体层上；一对外延层，形成在应变沟道层的两侧上以改变应变沟道层的晶格结构；栅图案，形成在应变沟道层上；以及源和漏区，形成在外延层上。
根据本发明的应变沟道晶体管包括：锗层，形成在硅基片上；以及应变沟道，形成在锗层上的硅层中。由于外延层形成在应变沟道层的两侧中，沟道层的晶格距离由来自外延层的应力而变宽，并最终提高了通过沟道的电荷的迁移率。
根据本发明的应变沟道晶体管的制造方法特征在于包括步骤：形成具有大于半导体基片的晶格常数的晶格常数的半导体层；在半导体层上形成应变半导体层；以及在通过蚀刻应变半导体层而形成的沟槽区中形成外延层。
沟槽区限定沟道区，并且应变半导体层的晶格距离由形成在沟槽区中的外延层的应力而变宽。栅图案可以形成在沟道区上，且源/漏区可以形成在栅图案的两侧上的外延层中。
根据本发明，晶体管的沟道形成在与外延层构成异质结的应变半导体层中，并且结果可以形成其晶格距离由从外延层施加的应力而变宽的应变沟道。因为根据本发明的应变沟道的晶格距离变宽，通过沟道的电荷的迁移率可得以提高，并且由具有低迁移率的空穴来传送信号的PMOS(P沟道金属氧化物半导体)晶体管的工作速度可得以提高。并且，可以通过将根据本发明的应变沟道应用到具有低于65nm的晶体管的沟道的半导体器件而制造消耗低功率和以高速度工作的半导体器件。
附图说明
图1是传统应变沟道晶体管的横截面视图。
图2是根据本发明的应变沟道晶体管的一实施例的横截面视图。
图3到5是图示了用于根据本发明的一实施例制造应变沟道晶体管的方法的横截面视图。
具体实施方式
下文中，将参照附图详细描述本发明的一优选实施例。
图2是根据本发明的应变沟道晶体管的一实施例的横截面视图。如图2中所示，应变沟道晶体管包括：形成在半导体基片50上的半导体层52；形成在半导体层52上的应变沟道层54；以及形成在应变沟道层54的两侧上的外延层64。栅图案70形成在应变沟道层54上，且源/漏区形成在外延层64上。
半导体基片50包括具有第一晶格常数的材料例如硅基片，且半导体层52可以由具有大于硅的晶格常数的第二晶格常数的锗层来形成。应变沟道层54可以从硅层来形成，在该硅层中，晶格距离通过使硅的密度在半导体层52上逐渐增大而变宽。
根据本发明的一实施例，应变沟道层54和外延层64形成由隔离层56限定的有源区。此外，栅图案79在有源区的顶部上而形成。即应变沟道层54可以形成在栅图案之下。这里，由于外延层64由与应变沟道层54接触的材料制成，因此施加应力到应变沟道层54，应变沟道层54可以变形。因而，应变沟道层54的晶格距离可变大，同时与具有相对大的晶格参数的外延层64接触。从而，其晶格距离变大的应变沟道层54可以改善诸如空穴的电荷的迁移率。
图3到5是图示了用于根据本发明的一实施例制造应变沟道晶体管的方法的横截面视图。
如图3中所示，具有第二晶格常数的半导体层52形成在具有第一晶格常数的半导体基片50上。第二晶格常数大于第一晶格常数。例如，如果半导体基片50是硅基片，则半导体层52可以由具有大于硅的晶格常数的晶格常数的材料来形成，该材料是从锗、硅-锗(SiGe)、碳化硅、InP、CdSe、ZnTe和MgSe等构成的组中选择的，并且根据本发明的一实施例，半导体层52优选地由锗形成。
接着，应变半导体层54通过在半导体层52上以体状态(bulk state)外延地生长如具有第一晶格常数的硅材料的半导体材料而形成。特别地，因为锗层通常具有大于典型硅材料的晶格参数，生长在包括锗的半导体层52上的应变半导体层54中的硅的晶格距离可以扩大，因此导致具有大于体硅(bulky silicon)的晶格常数的晶格常数的应变半导体层54。
如图3中所示，在半导体层52上形成应变半导体层54之后，通过在包括应变半导体层54的基片上形成多个隔离层56来限定有源区。
如图4中所示，在形成隔离层56之后，掩模层60形成在半导体基片上。掩模层60覆盖将形成晶体管的沟道的区，并具有通过其暴露有源区的开口。使用掩模层60作为蚀刻掩模，通过开口而被暴露的应变半导体层54的部分被蚀刻以形成沟槽区62。在此蚀刻过程中，应变半导体层54的被暴露部分可以被完全移除以暴露半导体层52，应变半导体层54的一部分可以保留在半导体层52上。
如图5中所示，在形成沟槽区62之后，使用掩模层60作为生长阻挡层，外延层64生长在沟槽区62中。因为应变层54由外延层64的生长施加应力，应变半导体层54的晶格结构可以由具有外延层64的异质结变形。因此，当应变半导体层54与具有较大晶格常数的外延层64接触时，应变半导体层54的晶格距离可以变得更加扩大。
因此，外延层64优选地由具有比应变半导体层54大的晶格常数的材料制成。例如，在应变半导体层54由硅制成的情形中，外延层64可以包括由具有比硅大的晶格常数的锗、硅-锗(SiGe)、碳化硅、InP、CdSe、ZnTe和MgSe构成的组中的任何一个。根据本发明的一实施例，更优选地是外延层64由锗制成。
连续地，根据用于制造晶体管的典型过程，栅图案70形成在应变半导体层54上，如图2中所示。另外，源/漏区可以形成在栅图案70旁边的外延层64中，如图5中所示。
尽管已经特别示出并且参照其优选实施例描述了本发明，本领域技术人员应该理解，可以在不脱离由所附的权利要求所限定的本发明的精神和范围的情况下进行形式和细节的各种修改。

Claims (8)

1.一种应变沟道晶体管，包括：
半导体基片；
半导体层，具有大于所述半导体基片的晶格常数的晶格常数，并且形成在所述半导体基片上；
应变沟道层，形成在所述半导体层上；
一对外延层，形成在所述应变沟道层的两侧上以改变所述应变沟道层的晶格结构；
栅图案，形成在所述应变沟道层上；以及
源和漏区，形成在所述外延层上。
2.如权利要求1的应变沟道晶体管，其中所述应变沟道层的材料具有第一晶格常数，所述半导体层或所述外延层的材料具有第二晶格常数，以及
所述第二晶格常数大于所述第一晶格常数。
3.如权利要求1或2的应变沟道晶体管，其中在所述半导体基片是硅基片的情形中，所述半导体层包括从由锗、硅-锗(SiGe)、碳化硅、InP、CdSe、ZnTe和MgSe构成的组中选择的任何一个。
4.如权利要求1或2的应变沟道晶体管，其中在所述应变沟道层包括硅材料的情形中，所述外延层包括从由锗、硅-锗(SiGe)、碳化硅、InP、CdSe、ZnTe和MgSe构成的组中选择的任何一个。
5.如权利要求1或2的应变沟道晶体管，其中在所述半导体基片是硅基片的情形中，所述应变沟道层包括硅，并且所述应变沟道层的晶格距离通过所述外延层而变形。
6.一种用于制造应变沟道晶体管的方法，包括步骤：
在半导体基片上形成半导体层，所述半导体层具有大于所述半导体基片的晶格常数的晶格常数；
在所述半导体层上形成应变半导体层；
通过图案化所述应变半导体层而形成多个沟槽，所述多个沟槽限定沟道区；
使用外延生长过程在所述沟槽中形成外延层，所述外延层与所述沟道区接触；
在所述沟道区上形成栅图案；以及
在所述外延层中形成源区和漏区。
7.如权利要求6的方法，其中形成所述多个沟槽包括步骤：
形成掩模层以覆盖所述应变半导体层上的所述沟道区；以及
蚀刻所述应变半导体层以形成所述多个沟槽；以及
其中形成所述外延层包括步骤：
通过使用所述掩模层作为生长阻挡层而在所述沟槽中形成所述外延层。
8.如权利要求6或7的方法，其中在所述应变半导体层包括硅的情形中，所述外延层包括从由锗、硅-锗(SiGe)、碳化硅、InP、CdSe、ZnTe和MgSe构成的组中选择的任何一个。
CNB2006100995072A 2005-07-26 2006-07-26 应变沟道晶体管的制造方法 Expired - Fee Related CN100552973C (zh)

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KR1020050067885A KR100639032B1 (ko) 2005-07-26 2005-07-26 스트레인드 채널 트랜지스터 및 그 제조방법
KR1020050067885 2005-07-26

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CN103367430A (zh) * 2012-03-29 2013-10-23 中芯国际集成电路制造(上海)有限公司 晶体管以及形成方法
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CN101378080B (zh) * 2007-08-29 2010-12-08 东部高科股份有限公司 半导体器件及其制造方法
CN102956497A (zh) * 2011-08-30 2013-03-06 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN102956497B (zh) * 2011-08-30 2015-04-29 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
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