CN101378080B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN101378080B
CN101378080B CN2008102139066A CN200810213906A CN101378080B CN 101378080 B CN101378080 B CN 101378080B CN 2008102139066 A CN2008102139066 A CN 2008102139066A CN 200810213906 A CN200810213906 A CN 200810213906A CN 101378080 B CN101378080 B CN 101378080B
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赵勇洙
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Abstract

本发明披露了一种半导体器件及其制造方法，通过该半导体器件及其制造方法提高了沟道的迁移率并且可以使闪烁噪声的影响最小化。本发明实施例涉及一种制造半导体器件的方法，该方法包括：在衬底上方形成第一外延层，在第一外延层上方形成第二外延层，在第二外延层上方形成栅电极，在栅电极的两侧上方形成隔离件，蚀刻与隔离件的两侧相邻的区域至衬底的深度，在隔离件下方的区域中形成LDD区，以及在与隔离件的两侧相邻的蚀刻区域上方形成用于源区/漏区的第三外延层。

Description

半导体器件及其制造方法
本申请基于35U.S.C119要求第10-2007-0087002号(于2007年8月29日递交)韩国专利申请的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及一种半导体器件技术，更具体地，涉及一种半导体器件及其制造方法。
背景技术
通常，由于半导体器件变的更加高度集成，所以实施制造工艺变的更加困难。例如，在MOS晶体管中，由于栅电极/源电极/漏电极在尺寸上降低，所以沟道长度也降低。由于沟道长度降低，栅极绝缘层的厚度也降低，降低了电子的迁移率。
此外，由于沟道杂质的浓度上升，闪烁噪声(flicker noise)增加到影响模拟信号特性。因此，在制造用于SoC(片上系统)技术的半导体器件的过程中，难于确保操作的可靠性。闪烁噪声是一种在有源器件中固有的噪声。由于闪烁噪声与频率成反比，所以可以将闪烁噪声称做“1/f噪声”。闪烁噪声在低频带上迅速地增加。闪烁噪声与电子迁移率、沟道杂质及其类似物相关。在用于稳定的射频信号的SoC中，闪烁噪声可能引起严重的问题。
发明内容
本发明实施例涉及一种半导体器件技术，更具体地，涉及一种半导体器件及其制造方法。本发明实施例涉及一种半导体器件及其制造方法，通过该半导体器件及其制造方法提高了沟道的迁移率并且可以使得闪烁噪声的影响最小化。
一种根据本发明实施例的半导体器件包括：在衬底上方的第一外延层(epi-layer)，在第一外延层上方的第二外延层，在第二外延层上方的栅电极，在栅电极的两侧上方的隔离件，以及形成在隔离件下方并达到第一外延层深度的LDD区。第一外延层可以包括掺杂有沟道杂质的外延层而第二外延层可以包括不含有沟道杂质的未掺杂外延层。该半导体可以进一步包括用来形成源区/漏区的第三外延层，该第三外延层邻近隔离体的两侧并位于包括第一和第二外延层的衬底的被蚀刻部分的上方。
本发明实施例涉及一种制造半导体器件的方法，该方法包括：在衬底上方形成第一外延层，在第一外延层上方形成第二外延层，在第二外延层上方形成栅电极，在栅电极的两侧上方形成隔离件，蚀刻与隔离件的两侧相邻的区域至衬底的深度，在隔离件下方的区域中形成LDD区，以及在邻近隔离件两侧的蚀刻区域上方形成用于源区/漏区的第三外延层。
隔离件形成步骤可以包括：在与栅电极两侧相邻的第二外延层上方形成氧化层，在栅电极上方形成第一氮化层，该氮化层具有的宽度大于栅电极的宽度，并在氧化层的顶部上方延伸，以及使用第一氮化层作为掩模去除氧化层的一部分。在形成隔离件后，第一氮化层可以进一步在部分蚀刻第一氮化层至衬底的深度的过程中被用作掩模。
在蚀刻与隔离件两侧相邻的区域至衬底的深度之后，该方法可以进一步包括在垂直方向上施加应力(stress)给通过蚀刻步骤暴露的衬底。在垂直方向上施加应力给衬底可以包括在包含栅电极和隔离件的衬底上方形成第二氮化层。
应力可以在垂直方向上施加给所暴露的衬底以使应力能够存储在栅电极的沟道区中。
附图说明
实例图1是在已经形成第二外延层之后根据本发明实施例的半导体器件的截面图。
实例图2是在已经形成栅电极之后根据本发明实施例的半导体器件的截面图。
实例图3是在已经形成氧化层之后根据本发明实施例的半导体器件的截面图。
实例图4是在已经形成氮化层和光刻胶层之后根据本发明实施例的半导体器件的截面图。
实例图5是在已经去除氧化层和部分衬底之后根据本发明实施例的半导体器件的截面图。
实例图6是在已经形成第二氮化层之后根据本发明实施例的半导体器件的截面图。
实例图7是在已经去除第二氮化层之后根据本发明实施例的半导体器件的截面图。
实例图8是在已经形成LDD区之后根据本发明实施例的半导体器件的截面图。
实例图9是根据本发明实施例的完成的半导体器件的截面图。
具体实施方式
实例图1是在已经形成第二外延层130之后根据本发明实施例的半导体器件的截面图。参照实例图1，大量掺杂有沟道杂质的第一外延层120生长在半导体衬底110，例如，单晶硅衬底的上方。第一外延层120可以包含在大约2×1013离子/cm2到2×1016离子/cm2之间的沟道杂质量级(level)。例如，在NMOS晶体管中，沟道杂质可以包括硼(B)或其类似。例如，在PMOS晶体管中，沟道杂质可以包括砷、磷或其类似。
在第一外延层120已经长成并掺杂沟道杂质之后，第二外延层130可以生长在第一外延层120上方。第二外延层130不掺杂杂质。每个外延层120和130可以具有相同的厚度，该厚度可以为大约10nm到30nm。在已经形成分别对应于掺杂沟道杂质的外延层和不掺杂沟道杂质的外延层的第一外延层和第二外延层之后，可以形成在以下描述中说明的栅电极140。
实例图2是在已经形成栅电极之后根据本发明实施例的半导体器件的截面图。参照实例图2，为了形成栅电极140，可以在第二外延层130上方生长栅极氧化物(gate oxide)。然后，可以用多晶硅涂覆该栅极氧化物。可以轮流使用光刻胶和干蚀刻工艺来形成栅电极140。通过干蚀刻工艺蚀刻的栅极氧化物成为栅极绝缘层141，而被蚀刻的多晶硅成为电极142。在以下的描述中，术语栅电极140将指的是栅极绝缘层141和电极142两者。栅电极140可以为大约130nm到170nm高。
实例图3是在已经形成氧化层152之后根据本发明实施例的半导体器件的截面图。参照实例图3，可以通过沉积和平坦化在栅电极140两侧上方形成氧化层152。具体地，在已经形成栅电极140之后，可以在包括栅电极140的第二外延层130上方沉积氧化物。该氧化物可以通过CVD(化学气相沉积)来沉积。可以通过诸如CMP(化学机械抛光)的平坦化(planarization)来抛光该氧化物直到暴露栅电极140的顶部表面。
实例图4是在已经形成氮化层154和光刻胶层156之后根据本发明实施例的半导体器件的截面图。参照实例图4，完成在氧化物上方实施的平坦化(planarization)以在栅电极140两侧的上方形成氧化层152之后，可以在包括栅电极140的氧化层152上方形成第一氮化层154。可以形成光刻胶层156以覆盖栅电极140和位于栅电极140两侧上方的部分第一氮化层154。光刻胶层156可以被形成具有的宽度大于栅电极140的宽度。更具体地，光刻胶层156可以被形成从栅电极140的两侧延伸大约45nm到55nm。
可以使用光刻胶层156作为掩模来蚀刻第一氮化层154。可以通过使用光刻胶层156蚀刻形成第一氮化层154a。第一氮化层154a(在图5中示出)可以被形成具有的宽度大于栅电极140的宽度以在氧化层152上方延伸。可以使用第一氮化层154a作为蚀刻掩模来形成虚拟隔离件(dummy spacer)。
实例图5是在已经去除氧化层和部分衬底之后根据本发明实施例的半导体器件的截面图。参照实例图5，在已经通过使用光刻胶层156作为掩模蚀刻形成第一氮化层154a之后，可以去除光刻胶层156。可以使用第一氮化层154a作为掩模通过第一干蚀刻工艺去除部分氧化层152。在栅电极140两侧上方残留的部分氧化层成为虚拟隔离件152a。
在已经去除部分氧化层152之后，可以实施使用第一氮化层154a作为掩模的第二干蚀刻工艺。在第二干蚀刻工艺中，衬底110可以被蚀刻至距离衬底110的表面大约95nm到105nm的深度。因此，可以去除包括没有被隔离件152a两侧覆盖的第一外延层120和第二外延层130的部分衬底110。可以去除氮化层154a，该氮化层154a在形成虚拟隔离件152a和去除包括第一外延层120和第二外延层130的部分衬底110的过程中用作蚀刻掩模。
实例图6是在已经形成第二氮化层160之后根据本发明实施例的半导体器件的截面图，而实例图7是在已经去除第二氮化层160之后根据本发明实施例的半导体器件的截面图。在已经去除第一氮化层154a之后，可以在包括栅电极140和隔离件152a的被部分蚀刻的衬底110a上方形成第二氮化层160，以施加垂直的应力给通过蚀刻暴露的衬底110a。应力可以通过高温退火(high-temperatureannealing)来相对于栅电极140下方的沟道区垂直地集中。应力可以存储在栅电极140的沟道区中。第二氮化层160可以由SIN基材料(SIN based material)形成。在完成应力的沟道存储过程之后，可以去除第二氮化层160。通过在沟道区中存储应力，栅电极140的沟道区被活化(activated)，并且在沟道区中提高了电子迁移率。
实例图8是在已经形成LDD区170之后根据本发明实施例的半导体器件的截面图。在已经去除第二氮化层160之后，可以通过离子注入来形成LDD区170。例如，在形成p-型LDD区的过程中，可以使用具有5KeV到50KeV能量和1×1014离子/cm2到5×1015离子/cm2剂量的BF2离子来实施离子注入。在形成n-型LDD区的过程中，可以使用具有10KeV到70KeV能量和1×1014离子/cm2到5×1015离子/cm2剂量的砷离子来实施离子注入。通过上述的LDD结构，降低了在沟道区和源极/漏极结(junction)周围的漏极-栅极电压并且减少了相当大的电位波动(potential fluctuation)。因此，该LDD结构有助于抑制热载流子的产生。
通过控制离子注入的能量，可以制成第一外延层120和衬底110以限制LDD区170。换句话说，可以根据与衬底110一起蚀刻的第一外延层120a的结构来限定LDD区170。因此，LDD区170可以形成在隔离件152a下方并且达到通过第二干蚀刻工艺蚀刻的第一外延层120a的深度。
实例图9是在制造完成之后根据本发明实施例的半导体器件的截面图。在已经形成LDD区170之后，可以形成第三外延层180以覆盖通过第二干蚀刻工艺蚀刻的部分衬底。第三外延层180可以被形成具有与隔离件152a的底部相同的高度。具体地，可以在与隔离件152a两侧相邻的被蚀刻的衬底区域上方形成第三外延层180。每个衬底区域起到源区/漏区的作用。更具体地，可以在邻近隔离件152a两侧的通过第二干蚀刻工艺蚀刻的部分衬底110上方形成第三外延层180，该蚀刻的部分衬底110包括第一外延层120和第二外延层130。第三外延层180成为源区和漏区。
随后，可以通过自对准多晶硅化(salicidation)在源区和漏区的第三外延层180和栅电极140上方形成硅化物层。然后，可以实施一系列的后续工艺，例如，用于接触件、金属导线及其类似物的工艺。由于缺乏与本发明实施例的关联性，将省略后续工艺的细节。
因此，本发明实施例提供了以下的作用和/或优点。本发明实施例使用氮化层集中地施加应力给使用了沟道存储的沟道区，从而提高了电子迁移率。本发明实施例在沟道区中形成多层的外延层结构，从而降低了沟道杂质的剂量并同样因此提高了电子迁移率。因此，即使在几十纳米或更低的级别上集成半导体器件，本发明实施例也可使器件的可靠性最大化。本发明实施例使由闪烁噪声引起的影响最小化，从而增强了器件的模拟特性。在将SoC技术应用到半导体器件的过程中，本发明实施例使相邻器件之间的干扰信号的影响最小化。
在所披露的本发明实施例中可以作各种修改及变形，这对于本领域的技术人员而言是显而易见且明显的。因此，本发明意在涵盖在所附权利要求及其等同替换的范围内的对披露的本发明实施例的显而易见且明显的修改和变形。

Claims (15)

1.一种制造半导体器件的方法，包括：
在衬底上方形成第一外延层；
在所述第一外延层上方形成第二外延层；
在所述第二外延层上方形成栅电极；
在所述栅电极的两侧的侧壁上形成隔离件；
蚀刻与所述隔离件的两侧相邻的区域至衬底的深度；
在所述隔离件下方的区域中形成LDD区；以及
在与所述隔离件的两侧相邻的蚀刻区域上方形成用于源区/漏区的第三外延层；
其中，在所述栅电极的两侧的侧壁上形成隔离件包括：
在与所述栅电极的两侧相邻的所述第二外延层上方形成氧化层；
在所述栅电极上方形成第一氮化层，所述氮化层具有的宽度大于所述栅电极的宽度，并且在所述氧化层的顶部上方延伸；以及
使用所述第一氮化层作为掩模去除所述氧化层的一部分。
2.根据权利要求1所述的方法，其中，所述第一外延层掺杂有沟道杂质。
3.根据权利要求1所述的方法，其中，所述第二外延层不包含沟道杂质。
4.根据权利要求1所述的方法，其中，所述第一外延层和第二外延层具有相同的厚度。
5.根据权利要求1所述的方法，其中，在形成所述隔离件之后，所述第一氮化层进一步在部分蚀刻所述衬底至距离所述衬底的表面一个深度的过程中被用作掩模。
6.根据权利要求5所述的方法，其中，所述第一氮化层在所述衬底已经被部分蚀刻至距离所述衬底的表面一个深度之后被去除。
7.根据权利要求1所述的方法，其中，在蚀刻与所述隔离件两侧相邻的区域至所述衬底的深度之后，所述方法包括施加垂直的应力给通过所述蚀刻暴露的所述衬底。
8.根据权利要求7所述的方法，其中，在垂直方向上施加所述应力给所述衬底的步骤包括，在包括所述栅电极和所述隔离件的所述衬底上方形成第二氮化层的步骤。
9.根据权利要求8所述的方法，其中，所述第二氮化层由SiN形成。
10.根据权利要求8所述的方法，包括去除所述第二氮化层。
11.根据权利要求7所述的方法，其中，所述应力存储在所述栅电极的沟道区中。
12.根据权利要求4所述的方法，其中，每个所述第一外延层和第二外延层的厚度在10nm到30nm之间。
13.根据权利要求7所述的方法，其中，所述栅电极形成为130nm到170nm高。
14.根据权利要求1所述的方法，其中，所述第一氮化层延伸超出所述栅电极45nm到55nm。
15.根据权利要求7所述的方法，其中，所述应力可以通过高温退火来相对于所述栅电极下方的沟道区垂直地集中。
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Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
CN102237396B (zh) * 2010-04-27 2014-04-09 中国科学院微电子研究所 半导体器件及其制造方法
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
US10522534B2 (en) 2016-04-29 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET varactor with low threshold voltage and method of making the same
FR3141800A1 (fr) * 2022-11-04 2024-05-10 Stmicroelectronics (Grenoble 2) Sas Transistor MOSFET

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1905211A (zh) * 2005-07-26 2007-01-31 东部电子株式会社 应变沟道晶体管及其制造方法
US7179696B2 (en) * 2004-09-17 2007-02-20 Texas Instruments Incorporated Phosphorus activated NMOS using SiC process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414736B1 (ko) * 2002-05-20 2004-01-13 주식회사 하이닉스반도체 반도체소자의 트랜지스터 형성방법
KR100485164B1 (ko) * 2003-08-12 2005-04-22 동부아남반도체 주식회사 반도체 소자 및 그 제조 방법
KR20060072411A (ko) * 2004-12-23 2006-06-28 동부일렉트로닉스 주식회사 에피택셜 공정을 이용한 반도체 소자의 제조 방법
KR100562309B1 (ko) * 2004-12-29 2006-03-22 동부아남반도체 주식회사 리버스 스페이서를 갖는 트랜지스터 및 그 제조 방법
KR100613294B1 (ko) * 2004-12-30 2006-08-21 동부일렉트로닉스 주식회사 단채널 효과가 개선되는 모스 전계효과 트랜지스터 및 그제조 방법
JP4493536B2 (ja) * 2005-03-30 2010-06-30 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP2007157788A (ja) 2005-11-30 2007-06-21 Toshiba Corp 半導体装置
US7432559B2 (en) * 2006-09-19 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation on SiGe
US20080242032A1 (en) * 2007-03-29 2008-10-02 Texas Instruments Incorporated Carbon-Doped Epitaxial SiGe
KR20080094501A (ko) * 2007-04-20 2008-10-23 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7179696B2 (en) * 2004-09-17 2007-02-20 Texas Instruments Incorporated Phosphorus activated NMOS using SiC process
CN1905211A (zh) * 2005-07-26 2007-01-31 东部电子株式会社 应变沟道晶体管及其制造方法

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