CN112567514A - 存储器结构及其形成方法 - Google Patents

存储器结构及其形成方法 Download PDF

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CN112567514A
CN112567514A CN201880096614.0A CN201880096614A CN112567514A CN 112567514 A CN112567514 A CN 112567514A CN 201880096614 A CN201880096614 A CN 201880096614A CN 112567514 A CN112567514 A CN 112567514A
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layer
substrate
isolation
substrate layer
contact
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CN112567514B (zh
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陈赫
董金文
朱继锋
华子群
肖亮
王永庆
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Yangtze Memory Technologies Co Ltd
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Abstract

本发明涉及一种存储器结构及其形成方法，所述存储器结构包括：第一基底，包括：衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述第一基底包括焊垫区域；介质层，位于所述衬底层的第二表面上；焊垫，位于所述焊垫区域上的介质层表面；隔离结构，贯穿所述衬底层，位于所述焊垫区域边缘，包围所述焊垫区域内的衬底层，用于隔离所述焊垫区域内的衬底层与所述隔离结构外围的衬底层。本发明的存储器结构中焊垫与衬底层之间的寄生电容被减小，有利于提高存储器性能。

Description

PCT国内申请，说明书已公开。

Claims (20)

  1. PCT国内申请，权利要求书已公开。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594163A (zh) * 2021-07-05 2021-11-02 长鑫存储技术有限公司 存储器及其制造方法
CN113725226A (zh) * 2021-08-30 2021-11-30 长江存储科技有限责任公司 三维存储器及其制造方法
US11985808B2 (en) 2021-07-05 2024-05-14 Changxin Memory Technologies, Inc. Memory and method for manufacturing same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018117102A (ja) * 2017-01-20 2018-07-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置
CN111326511A (zh) * 2020-03-09 2020-06-23 长江存储科技有限责任公司 存储器件及其制造方法
CN117649869A (zh) * 2022-08-17 2024-03-05 长鑫存储技术有限公司 一种存储系统及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101202257A (zh) * 2004-03-31 2008-06-18 恩益禧电子股份有限公司 半导体器件及其制造方法
US20120181602A1 (en) * 2011-01-13 2012-07-19 Yoshiaki Fukuzumi Semiconductor memory device and method of manufacturing the same
CN105788632A (zh) * 2016-02-26 2016-07-20 宁波时代全芯科技有限公司 记忆体结构与记忆体电路
CN106910746A (zh) * 2017-03-08 2017-06-30 长江存储科技有限责任公司 一种3d nand存储器件及其制造方法、封装方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637513A (en) * 1994-07-08 1997-06-10 Nec Corporation Fabrication method of semiconductor device with SOI structure
KR100268422B1 (ko) * 1998-07-31 2000-10-16 윤종용 반도체 장치의 콘택 패드 및 그의 형성 방법
ATE524839T1 (de) * 2004-06-30 2011-09-15 Cree Inc Verfahren zum kapseln eines lichtemittierenden bauelements und gekapselte lichtemittierende bauelemente im chip-massstab
JP4577687B2 (ja) * 2005-03-17 2010-11-10 エルピーダメモリ株式会社 半導体装置
US7745876B2 (en) * 2007-02-21 2010-06-29 Samsung Electronics Co., Ltd. Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same
US7882628B2 (en) * 2007-05-30 2011-02-08 Intel Corporation Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
KR101419882B1 (ko) * 2007-06-18 2014-08-14 삼성전자주식회사 패턴 형성 방법, 이를 이용한 전하 저장막 패턴 형성 방법,비휘발성 메모리 소자 및 이의 제조 방법.
JP5302522B2 (ja) * 2007-07-02 2013-10-02 スパンション エルエルシー 半導体装置及びその製造方法
KR101320518B1 (ko) * 2007-10-24 2013-12-19 삼성전자주식회사 적층 레벨의 트랜지스터들을 갖는 집적 회로 반도체 소자및 그 제조방법
US20100224965A1 (en) * 2009-03-09 2010-09-09 Chien-Li Kuo Through-silicon via structure and method for making the same
US8263492B2 (en) * 2009-04-29 2012-09-11 International Business Machines Corporation Through substrate vias
JP5218497B2 (ja) * 2009-12-04 2013-06-26 株式会社デンソー 半導体装置およびその製造方法
KR101697573B1 (ko) * 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
US9595533B2 (en) * 2012-08-30 2017-03-14 Micron Technology, Inc. Memory array having connections going through control gates
KR102076305B1 (ko) * 2013-05-13 2020-04-02 에스케이하이닉스 주식회사 반도체 소자 및 그 형성 방법
US9236326B2 (en) * 2014-04-25 2016-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US9324632B2 (en) * 2014-05-28 2016-04-26 Globalfoundries Inc. Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
US9728545B2 (en) * 2015-04-16 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for preventing floating gate variation
US20170317166A1 (en) * 2016-04-29 2017-11-02 Globalfoundries Inc. Isolation structures for circuits sharing a substrate
CN106920796B (zh) * 2017-03-08 2019-02-15 长江存储科技有限责任公司 一种3d nand存储器件及其制造方法
US9960181B1 (en) * 2017-04-17 2018-05-01 Sandisk Technologies Llc Three-dimensional memory device having contact via structures in overlapped terrace region and method of making thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101202257A (zh) * 2004-03-31 2008-06-18 恩益禧电子股份有限公司 半导体器件及其制造方法
US20120181602A1 (en) * 2011-01-13 2012-07-19 Yoshiaki Fukuzumi Semiconductor memory device and method of manufacturing the same
CN105788632A (zh) * 2016-02-26 2016-07-20 宁波时代全芯科技有限公司 记忆体结构与记忆体电路
CN106910746A (zh) * 2017-03-08 2017-06-30 长江存储科技有限责任公司 一种3d nand存储器件及其制造方法、封装方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594163A (zh) * 2021-07-05 2021-11-02 长鑫存储技术有限公司 存储器及其制造方法
CN113594163B (zh) * 2021-07-05 2023-12-19 长鑫存储技术有限公司 存储器及其制造方法
US11985808B2 (en) 2021-07-05 2024-05-14 Changxin Memory Technologies, Inc. Memory and method for manufacturing same
CN113725226A (zh) * 2021-08-30 2021-11-30 长江存储科技有限责任公司 三维存储器及其制造方法
CN113725226B (zh) * 2021-08-30 2024-04-16 长江存储科技有限责任公司 三维存储器及其制造方法

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