WO2021022811A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2021022811A1
WO2021022811A1 PCT/CN2020/079582 CN2020079582W WO2021022811A1 WO 2021022811 A1 WO2021022811 A1 WO 2021022811A1 CN 2020079582 W CN2020079582 W CN 2020079582W WO 2021022811 A1 WO2021022811 A1 WO 2021022811A1
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Prior art keywords
contact pad
layer
interlayer dielectric
contact
dielectric layer
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PCT/CN2020/079582
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English (en)
French (fr)
Inventor
詹益旺
黄永泰
游馨
方晓培
童宇诚
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福建省晋华集成电路有限公司
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Priority to US17/290,040 priority Critical patent/US11967571B2/en
Publication of WO2021022811A1 publication Critical patent/WO2021022811A1/zh

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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a semiconductor structure and a method of forming the same.
  • the electrical transmission performance of the interconnection structure is very important.
  • the pattern of the contact pad is often deformed, which will further cause the problem of poor contact between the contact pad and other electrical transmission components, thereby affecting the interconnection structure The electrical transmission performance.
  • the purpose of the present invention is to provide a semiconductor structure to solve the problem of poor electrical transmission performance of the interconnection structure in the existing semiconductor structure.
  • the present invention provides a semiconductor structure, including:
  • the interconnection structure includes a contact plug and a first contact pad, the contact plug penetrates the interlayer dielectric layer and extends to the semiconductor device, the first contact pad covers the top of the contact plug, and Extending to cover part of the top surface of the interlayer dielectric layer; and,
  • the second contact pad is formed on the top surface of the interlayer dielectric layer and is spaced apart on the side of the first contact pad.
  • the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer; wherein the contact plug is formed On the side of the gate conductive layer, the first contact pad extends laterally from the side of the gate conductive layer to the shielding layer.
  • the second contact pad is formed on the shielding layer and is spaced apart from the first contact pad.
  • the width dimension of the portion of the first contact pad covering the shielding layer is smaller than the width dimension of the second contact pad.
  • the interlayer dielectric layer further includes isolation sidewalls covering sidewalls of the gate conductive layer, and the contact plug is formed on a side of the isolation sidewall away from the gate conductive layer, and the second A contact pad extends laterally and covers the isolation side wall adjacent to the contact plug.
  • the interlayer dielectric layer further includes an isolation dielectric layer formed on the periphery of the gate conductive layer, and the conductive plug penetrates the isolation dielectric layer.
  • the materials of the first contact pad and the second contact pad are the same.
  • both the first contact pad and the second contact pad include a first conductive layer and a second conductive layer formed on the first conductive layer, and the first contact pad in the first contact pad.
  • the conductive layer and the first conductive layer in the second contact pad have the same material, and the second conductive layer in the first contact pad and the second conductive layer in the second contact pad have the same material.
  • the present invention also provides another semiconductor structure, including:
  • the interconnection structure includes a contact plug and a first contact pad, the contact plug penetrates the interlayer dielectric layer and extends to the semiconductor device, the first contact pad covers the top of the contact plug, and Extending to cover part of the top surface of the interlayer dielectric layer; and,
  • the second contact pad is formed on the top surface of the interlayer dielectric layer and is spaced apart from the periphery of the first contact pad;
  • a groove located between the first contact pad and the second contact pad, the groove also extends downward and stops in the interlayer dielectric layer.
  • the groove exposes part of the sidewall of the first contact pad and part of the sidewall of the second contact pad
  • the semiconductor structure further includes:
  • An insulating filling layer is filled in the groove and covers the first contact pad and the second contact pad exposed on the sidewall of the groove.
  • voids are formed in the insulating filling layer.
  • the semiconductor device includes a gate conductive layer formed on a top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer;
  • the contact plug is formed on the side of the gate conductive layer, the first contact pad extends laterally from the side of the gate conductive layer to the shielding layer, and the second contact pad It is formed on the shielding layer and is spaced apart from the first contact pad, and the groove extends downward between the first contact pad and the second contact pad to stop in the shielding layer.
  • Another object of the present invention is to provide a method for forming a semiconductor structure, including:
  • the contact hole penetrates the interlayer dielectric layer and extends to the semiconductor device;
  • the conductive material layer is patterned to form an interconnect structure and a second contact pad, wherein the interconnect structure includes a contact plug filled in the contact hole and a first contact pad covering the top of the contact plug , And the second contact pad is spaced apart on the side of the first contact pad.
  • the method of patterning the conductive material layer includes:
  • a mask layer is formed on the conductive material layer, the mask layer has a first mask pattern and a second mask pattern, and the first mask pattern covers the area of the contact hole and a part of the outer periphery of the contact hole Area, the second mask pattern is located on the side of the first mask pattern and is separated from the first mask pattern by a predetermined size; and,
  • the conductive material layer is etched using the mask layer as a mask to form the interconnection structure corresponding to the first mask pattern and the second mask pattern corresponding to the second mask pattern.
  • Contact pad is etched using the mask layer as a mask to form the interconnection structure corresponding to the first mask pattern and the second mask pattern corresponding to the second mask pattern.
  • the method further includes:
  • the interlayer dielectric layer between the first contact pad and the second contact pad is etched, and the etching stops in the interlayer dielectric layer to form a groove.
  • the groove exposes part of the side wall of the first contact pad and part of the side wall of the second contact pad.
  • the method further includes:
  • An insulating filling layer is filled in the groove, and the insulating filling layer also covers the sidewalls of the first contact pad and the second contact pad exposed to the groove.
  • a second contact pad is further provided on the side of the first contact pad of the interconnect structure, so as to prevent the first contact pad from being exposed in a larger space area.
  • FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the invention
  • FIG. 2 is a schematic flowchart of a method for forming a semiconductor structure in an embodiment of the present invention
  • 3a to 3f are structural schematic diagrams of a method for forming a semiconductor structure in an embodiment of the present invention during its manufacturing process.
  • the inventors of the present invention have discovered after research that the patterning process is generally used to define the pattern of the contact pad when preparing the interconnect structure.
  • the patterning accuracy often Affected by the density of graphics. Specifically, when the graphics are arranged too densely, it is easy to cause the graphics to be unresolved and cause adjacent patterns to stick to each other; and when the graphics are too sparse, it is easy to cause the formed patterns to be over-resolved and appear. Problems with ripples or gaps.
  • the contact pads are usually formed in a larger space area in isolation. Based on this, when preparing the contact pads, it is easy to make the pattern of the formed contact pads occur. Deformation will further affect the electrical transmission performance of the interconnect structure.
  • the present invention provides a semiconductor structure to improve the problem that the contact pads in the interconnect structure described above are prone to pattern deformation.
  • FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present invention. As shown in FIG. 1, the semiconductor structure includes:
  • the interconnection structure 400 includes a contact plug 410 and a first contact pad 420.
  • the contact plug 410 penetrates the interlayer dielectric layer 300 and extends to the semiconductor device to interact with the semiconductor device.
  • the device is electrically connected, and the first contact pad 420 covers the top of the contact plug 410 and extends laterally to cover part of the top surface of the interlayer dielectric layer 300; and,
  • the second contact pad 500 is formed on the top surface of the interlayer dielectric layer 300 and is located on the side of the first contact pad 420 at intervals.
  • the first contact pad 420 is exposed to a larger space area, which is beneficial to improve The topography of the first contact pad 420 formed.
  • the second contact pad 500 is also formed on the side of the first contact pad 420, under the protection of the second contact pad 500, the first contact can be relieved.
  • the pad 420 is subject to a relatively large etching attack to avoid defects such as etching notches or deformation of the formed first contact pad 420.
  • the first contact pad 420 and the second contact pad 500 may be formed using the same conductive material layer, that is, the first contact pad 420 and the second contact pad 500 are made of the same material.
  • the first contact pad 420 and the second contact pad 500 both include a first conductive layer 710 and a second conductive layer 720, and the second conductive layer 720 is formed on the first conductive layer 710. on.
  • the first conductive layer 710 in the first contact pad 420 and the first conductive layer 710 in the second contact pad 500 are made of the same material
  • the second conductive layer 720 in the first contact pad 420 is The material of the second conductive layer 720 in the contact pad 500 is the same.
  • the material of the first conductive layer 710 includes titanium nitride, for example
  • the material of the second conductive layer 720 includes tungsten, for example.
  • the contact plug 410 and the first contact pad 420 in the interconnect structure 400 may be formed at the same time and have the same material. That is, in the embodiment of the present application, the contact plug 410 also includes a first conductive layer 710 and a second conductive layer 720, and the second conductive layer 720 is formed on the first conductive layer 710. Specifically, a contact hole is formed in the interlayer dielectric layer 300, and the contact plug 410 is formed in the contact hole. And, the first conductive layer 710 in the contact plug 410 covers the inner wall of the contact hole, and the second conductive layer 720 in the contact plug 410 fills the contact hole.
  • a groove 600a is further provided between the first contact pad 420 and the second contact pad 500, and the groove 600a also extends downward and stops at the In the interlayer dielectric layer 300.
  • the interlayer dielectric layer 300 between the first contact pad 420 and the second contact pad 500 can be further etched to ensure that the first contact pad 420 and the second contact pad 500 They are separated from each other, and the groove 600a is formed.
  • the semiconductor structure further includes an insulating filling layer 600, which is filled in the groove 600a and covers the first contact pad 420 and the second contact pad 500 exposed to the The side wall of the groove 600a.
  • a void 610 may be formed in the insulating filling layer 600 filled in the groove 600a.
  • the gap 610 extends vertically along the height direction in the middle area of the groove 600a.
  • the top of the gap 610 is higher than the top surface of the interlayer dielectric layer 300, so that the gap 610 has a portion between the first contact pad 420 and the second contact pad 500. That is, the insulating filling layer 600 filled in the area where the first contact pad 420 and the second contact pad 500 are opposite to each other is formed with a gap 610, so that the space between the first contact pad 420 and the second contact pad 500 can be reduced.
  • the dielectric constant of the dielectric material between them can effectively alleviate the parasitic capacitance between the first contact pad 420 and the second contact pad 500.
  • the gap 610 extends vertically downward from the top surface of the insulating filling layer 600.
  • the gap 610 is formed in the insulating filling layer 600, this also helps to relieve the internal stress of the insulating filling layer 600, so as to avoid the high-strength internal stress in the insulating filling layer 600 from damaging adjacent contact pads and semiconductor devices. .
  • the insulating filling layer 600 can utilize the gap 610 to achieve stress relief, preventing the insulating filling layer 600 from squeezing other components due to high-strength stress. The problem of damage.
  • the insulating filling layer 600 when the insulating filling layer 600 is formed directly above the semiconductor device, the high-strength internal stress in the insulating filling layer 600 may damage the semiconductor device. As shown in FIG. 1, in this embodiment, the insulating filling layer 600 is formed directly above the semiconductor device.
  • the semiconductor device includes at least one transistor, for example.
  • the transistor includes a gate conductive layer 200 formed on the top surface of the substrate 100, and a first source/drain region 110 and a second source/drain region 120 formed in the substrate 100, so The first source/drain region 110 and the second source/drain region 120 are respectively located on two sides of the gate conductive layer 200.
  • the gate conductive layer 200 includes a third conductive layer 210, a fourth conductive layer 220, and a fifth conductive layer 230 that are stacked.
  • the material of the third conductive layer 210 includes, for example, polysilicon
  • the material of the fourth conductive layer 220 includes, for example, titanium nitride
  • the material of the fifth conductive layer 230 includes, for example, tungsten.
  • the interlayer dielectric layer 300 includes a shielding layer 310 covering the top surface of the gate conductive layer 200.
  • the contact plug 410 is formed on the side of the gate conductive layer 200, and the bottom of the contact plug 410 extends vertically to the first source/drain region 110 or the second source/drain region 110 of the substrate 100
  • the drain region 120 uses at least two contact plugs 410 to connect the first source/drain region 110 and the second source/drain region 120 in a one-to-one correspondence.
  • the top of the contact plug 410 is higher than the gate electrode.
  • the first contact pad 420 extends laterally from the side of the gate conductive layer 200 to the shielding layer 310. That is, the first contact pad 420 is at least partially located directly above the gate conductive layer 200.
  • the second contact pad 500 may also be formed on the shielding layer 310 and be spaced apart from the first contact pad 420.
  • the groove 600a between the first contact pad 420 and the second contact pad 500 is formed in the shielding layer 310, and the insulating filling layer 600 is also partially filled in The shielding layer 310. That is, the projections of the insulating filling layer 600 and the gate conductive layer 200 along the height direction have overlapping regions.
  • the distance between the first contact pad 420 and the second contact pad 500 and the width of the first contact pad 420 and the second contact pad 500 can be adjusted according to actual conditions. Specifically, according to the resolution accuracy of the current photolithography process and etching process, the distance between the first contact pad 420 and the second contact pad 500, and the first contact pad 420 and the second contact pad 500 can be adjusted accordingly.
  • the distance between the first contact pad 420 and the second contact pad 500 can be made smaller than the width of the gate conductive layer 200. In this way, during the process of preparing the first contact pad 420, the The second contact pad 500 can protect the pattern of the first contact pad 420.
  • the width dimension of the first contact pad 420 covering the shielding layer 310 is also made smaller than the width dimension of the second contact pad 500. Since the first contact pad 420 extends from the edge of the shielding layer 310 to the center of the shielding layer 310, the second contact pad 500 is formed on the shielding layer 310, so when the first contact pad 420 covers all When the width dimension of the shielding layer 310 is smaller than the width dimension of the second contact pad 500, it is equivalent to that the groove 600a between the first contact pad 420 and the second contact pad 500 deviates from the central area of the shielding layer 310, and The groove 600a deviates from the central area of the shielding layer 310 in a direction close to the first contact pad 420.
  • the interlayer dielectric layer 300 further includes isolation spacers 320 covering the sidewalls of the gate conductive layer 200.
  • the isolation sidewall 320 also covers the sidewall of the shielding layer 310.
  • the contact plug 410 is formed on the side of the isolation sidewall 320 away from the gate conductive layer 200, and the first contact pad 420 extends laterally and covers the isolation side adjacent to the contact plug 410 Wall 320.
  • the isolation spacer 320 is, for example, a laminated structure sequentially covering the gate conductive layer 200.
  • the isolation spacer 320 includes a first isolation layer 321, a second isolation layer 322, and a third isolation layer 323 that sequentially cover the gate conductive layer 200.
  • the first isolation layer 321 and the third isolation layer 323 may be formed of the same material, for example, both include silicon oxide, and the material of the second isolation layer 322 includes, for example, silicon nitride.
  • the interlayer dielectric layer 300 further includes an isolation dielectric layer 330 formed on the periphery of the gate conductive layer 200.
  • the isolation dielectric layer 330 surrounds the periphery of the isolation spacer 320, and the conductive plug 410 penetrates the isolation dielectric layer 330.
  • At least two transistors may be formed on the substrate 100.
  • FIG. 1 of this embodiment only schematically shows two transistors, and the two transistors can share the first source/drain region 110.
  • the contact plug 410 electrically connected to the shared first source/drain region 110 is formed between the two transistors, and the corresponding first contact pad 420 extends to the two transistors laterally to the two transistors.
  • Above the gate conductive layer Above the gate conductive layer.
  • FIGS. 3a to 3f are schematic diagrams of a method for forming a semiconductor structure in an embodiment of the present invention during its manufacturing process.
  • step S100 is performed, and specifically referring to FIG. 3a, a substrate 100 is provided on which at least one semiconductor device and an interlayer dielectric layer 300 covering the semiconductor device are formed.
  • the semiconductor device includes a transistor.
  • the transistor further includes a gate conductive layer 200 formed on the top surface of the substrate 100, and a first source/drain region 110 and a second source/drain region 120 formed in the substrate 100.
  • the interlayer dielectric layer 300 includes a shielding layer 310 covering the top surface of the gate conductive layer 200.
  • the shielding layer 310 and the gate conductive layer 200 may be formed based on the same photolithography process.
  • the method for forming the shielding layer 310 in the interlayer dielectric layer 300 and the gate conductive layer 200 includes:
  • Step 1 sequentially forming a gate material layer and a shielding material layer on the substrate 100;
  • Step 2 Perform a photolithography process and an etching process to pattern the shielding material layer to form the shielding layer 310;
  • Step three the shielding layer 310 can be used as a mask layer to etch the gate material layer to form the gate conductive layer 200.
  • the gate material layer includes stacked multi-layer material layers, and when the gate material layer is etched, the multi-layer material layers are etched sequentially to form the third conductive layer 210, The fourth conductive layer 220 and the fifth conductive layer 230 further constitute the gate conductive layer 200.
  • the method for forming the interlayer dielectric layer 300 further includes: forming the isolation spacer 320 on the sidewalls of the gate conductive layer 200 and the shielding layer 310.
  • the method for forming the interlayer dielectric layer 300 further includes: forming an isolation dielectric layer 330 on the periphery of the gate conductive layer 200.
  • the isolation dielectric layer 330 surrounds the periphery of the isolation sidewall 320.
  • the isolation dielectric layer 330 may be formed by a planarization process. Specifically, after the isolation dielectric material layer is deposited, the masking layer 310 is used as a polishing stop layer to perform a chemical mechanical polishing process on the isolation dielectric material layer, so that the top surface of the isolation dielectric layer 330 formed is consistent with the masking layer. The top surface of layer 310 is flush.
  • step S200 is performed, referring specifically to FIG. 3b, a contact hole 700a is formed in the interlayer dielectric layer 300, and the contact hole 700a penetrates the interlayer dielectric layer 300 and extends to the semiconductor device.
  • the contact hole 700a penetrates the isolation dielectric layer 330 and extends to the top surface of the substrate 100 to expose the substrate 100.
  • step S300 is performed, specifically referring to FIG. 3c, a conductive material layer 700 is formed on the interlayer dielectric layer 300, and the conductive material layer 700 fills the contact hole 700a and covers the interlayer dielectric layer 300 The top surface.
  • the conductive material layer 700 may be formed by using a deposition process and a planarization process.
  • the method for forming the conductive material layer 700 includes:
  • a first conductive layer 710 is deposited on the interlayer dielectric layer 300, and the first conductive layer 710 conformally covers the inner wall of the contact hole 700a and the top surface of the interlayer dielectric layer 300;
  • a second conductive layer 720 is formed on the first conductive layer 710, and the second conductive layer 720 fills the contact hole 700a and covers the top surface of the interlayer dielectric layer 300.
  • the second conductive layer 720 is a planarized film layer, so that the second conductive layer 720 has a flat top surface.
  • step S400 is performed, and specifically referring to FIG. 3d, the conductive material layer 700 is patterned to form the interconnect structure 400 and the second contact pad 500.
  • the interconnect structure 400 includes a contact plug 410 filled in the contact hole and a first contact pad 420 covering the top of the contact plug 410, and the second contact pad 500 is spaced apart from the first contact pad. A side of the contact pad 420.
  • the method of patterning the conductive material layer 700 to form the interconnect structure 400 and the second contact pad 500 includes:
  • a mask layer (not shown in the figure) is formed on the conductive material layer 700, and the mask layer has a first mask pattern and a second mask pattern.
  • the first mask pattern corresponds to the pattern of the interconnect structure
  • the second mask pattern corresponds to the pattern of the second contact pad. That is, the first mask pattern covers the area of the contact hole and a part of the outer periphery of the contact hole; the second mask pattern is located on the side of the first mask pattern and is connected to the first mask pattern.
  • a mask pattern is separated by a predetermined size;
  • the conductive material layer 700 is etched using the mask layer as a mask to form the interconnection structure 400 corresponding to the first mask pattern and the second mask pattern The second contact pad 500.
  • the first contact pad 420 further extends laterally from the contact plug 410 to the shielding layer 310, and the second contact pad 500 is also at least partially formed on the shielding layer 310, It is separated from the first contact pad 420 by a predetermined size.
  • etching the conductive material layer 700 after etching the conductive material layer 700, it further includes: further etching the interlayer between the first contact pad 420 and the second contact pad 500
  • the dielectric layer 300 is etched and stopped in the interlayer dielectric 300 to form a groove 600a, so as to ensure that the first contact pad 420 and the second contact pad 500 are separated from each other.
  • the first contact pad 420 and the second contact pad 500 can be used as a mask to etch the exposed interlayer dielectric layer 300 to form the groove 600a.
  • the groove 600 a extends downward from between the first contact pad 420 and the second contact pad 500 into the shielding layer 310 and is located directly above the gate conductive layer 200.
  • a groove may also be formed on the side of the second contact pad 500 away from the first contact pad 420.
  • the method for forming the semiconductor structure further includes: filling an insulating filling layer 600 in the groove 600a, and the insulating filling layer 600 also covers the first contact pad 420 and the groove 600a.
  • the second contact pad 500 is exposed on the sidewall of the groove 600a.
  • the insulating filling layer 600 may also be formed with a gap 610, and the gap 610 will help realize the stress relief of the insulating filling layer 600.
  • the gap 610 extends vertically in the middle area of the groove 600a along the height direction, for example.
  • the second contact pads are arranged at intervals on the side of the first contact pads of the interconnect structure, so as to prevent the first contact pads from being exposed in a larger space area. .
  • the first contact pads formed by patterning are not exposed in a larger space area in isolation, but are protected by the second contact pads.
  • the over-resolved problem of the first contact pad is beneficial to improve the pattern accuracy of the formed first contact pad, which in turn helps to ensure the electrical transmission performance of the formed interconnection structure.
  • the pattern density of the area corresponding to the first contact pad is adjusted to improve the pattern resolution corresponding to the first contact pad, thereby forming a first contact pad with a good pattern topography. Contact pad.

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Abstract

一种半导体结构及其形成方法。通过在互连结构（400）的第一接触垫（420）的侧边设置第二接触垫（500），如此则在制备互连结构（400）时，通过图形化处理形成的第一接触垫（420）并不是孤立的暴露在一较大的空间区域中，而是在第二接触垫（500）的保护下，避免了第一接触垫（420）被过度解析的问题，有利于提高所形成的第一接触垫（420）的图形精度，进而有利于保障所述互连结构（400）的电性传输性能。

Description

半导体结构及其形成方法 技术领域
本发明涉及半导体技术领域，特别涉及一种半导体结构及其形成方法。
背景技术
在半导体结构中，一般需要利用互连结构实现半导体器件的电性传输，因此互连结构的电性传输性能至关重要。然而，目前所制备的互连结构中，常常会出现其接触垫的图形变形的现象，从而会进一步导致接触垫与其他电性传输组件之间出现接触不良的问题，进而影响所述互连结构的电性传输性能。
发明内容
本发明的目的在于提供一种半导体结构，以解决现有的半导体结构中其互连结构的电性传输性能较差的问题。
为解决上述技术问题，本发明提供一种半导体结构，包括：
衬底，所述衬底上形成有至少一半导体器件和层间介质层，所述层间介质层覆盖所述半导体器件；
互连结构，包括接触插塞和第一接触垫，所述接触插塞贯穿所述层间介质层并延伸至所述半导体器件，所述第一接触垫覆盖所述接触插塞的顶部，并延伸覆盖部分所述层间介质层的顶表面；以及，
第二接触垫，形成在所述层间介质层的顶表面上，并间隔位于所述第一接触垫的侧边。
可选的，所述半导体器件包括形成在所述衬底顶表面上的栅极导电层，所述层间介质层包括覆盖栅极导电层顶表面的遮蔽层；其中，所述接触插塞形成在所述栅极导电层的侧边，所述第一接触垫从所述栅极导电层的侧边横向延伸至所述遮蔽层上。
可选的，所述第二接触垫形成在所述遮蔽层上，并与所述第一接触垫间隔设置。
可选的，所述第一接触垫中覆盖所述遮蔽层的部分的宽度尺寸小于所述第二接触垫的宽度尺寸。
可选的，所述层间介质层还包括覆盖栅极导电层侧壁的隔离侧墙，所述接触插塞形成在所述隔离侧墙远离所述栅极导电层的一侧，所述第一接触垫横向延伸并覆盖与所述接触插塞邻近的隔离侧墙。
可选的，所述层间介质层还包括形成在所述栅极导电层外围的隔离介质层，所述导电插塞贯穿所述隔离介质层。
可选的，所述第一接触垫和所述第二接触垫的材料相同。
可选的，所述第一接触垫和所述第二接触垫均包括第一导电层和形成在所述第一导电层上的第二导电层，并且所述第一接触垫中的第一导电层和所述第二接触垫中的第一导电层的材料相同，所述第一接触垫中的第二导电层和所述第二接触垫中的第二导电层的材料相同。
本发明还提供了另一种半导体结构，包括：
衬底，所述衬底上形成有至少一半导体器件和层间介质层，所述层间介质层覆盖所述半导体器件；
互连结构，包括接触插塞和第一接触垫，所述接触插塞贯穿所述层间介质层并延伸至所述半导体器件，所述第一接触垫覆盖所述接触插塞的顶部，并延伸覆盖部分所述层间介质层的顶表面；以及，
第二接触垫，形成在所述层间介质层的顶表面上，并间隔位于所述第一接触垫的外围；以及，
位于所述第一接触垫和所述第二接触垫之间的凹槽，所述凹槽还向下延伸停止于所述层间介质层中。
可选的，所述凹槽暴露出所述第一接触垫的部分侧壁以及所述第二接触垫的部分侧壁，所述半导体结构还包括：
绝缘填充层，填充在所述凹槽中并覆盖所述第一接触垫和所述第二接触垫暴露于所述凹槽的侧壁。
可选的，所述绝缘填充层中形成有空隙。
可选的，所述半导体器件包括形成在所述衬底顶表面上的栅极导电层，所述层间介质层包括覆盖栅极导电层顶表面的遮蔽层；
其中，所述接触插塞形成在所述栅极导电层的侧边，所述第一接触垫从所述栅极导电层的侧边横向延伸至所述遮蔽层上，所述第二接触垫形成在所述遮蔽层上并与所述第一接触垫间隔设置，以及所述凹槽在所述第一接触垫和所述第二接触垫之间向下延伸停止于所述遮蔽层中。
本发明的又一目的在于提供一种半导体结构的形成方法，包括：
提供一衬底，所述衬底上形成有至少一半导体器件以及覆盖所述半导体器件的层间介质层；
形成接触孔在所述层间介质层中，所述接触孔贯穿所述层间介质层并延伸至所述半导体器件；
形成导电材料层在所述层间介质层上，所述导电材料层填充所述接触孔，并覆盖所述层间介质层的顶表面；以及，
图形化所述导电材料层，以形成互连结构和第二接触垫，其中所述互连结构包括填充在所述接触孔中的接触插塞以及覆盖所述接触插塞顶部的第一接触垫，并且所述第二接触垫间隔位于所述第一接触垫的侧边。
可选的，图形化所述导电材料层的方法包括：
形成掩膜层在所述导电材料层上，所述掩膜层具有第一掩膜图案和第二掩膜图案，所述第一掩膜图案覆盖所述接触孔的区域以及接触孔外周的部分区域，所述第二掩膜图案位于所述第一掩膜图案的侧边，并与所述第一掩膜图案间隔预定尺寸；以及，
以所述掩膜层为掩膜刻蚀所述导电材料层，以形成对应于所述第一掩膜图案的所述互连结构，以及对应于所述第二掩膜图案的所述第二接触垫。
可选的，图形化所述导电材料层之后，还包括：
刻蚀所述第一接触垫和所述第二接触垫之间的层间介质层，并刻蚀停止于所述层间介质层中，以形成凹槽。
可选的，所述凹槽暴露出所述第一接触垫的部分侧壁以及所述第二接触 垫的部分侧壁，在形成所述凹槽之后，还包括：
填充绝缘填充层在所述凹槽中，所述绝缘填充层还覆盖所述第一接触垫和所述第二接触垫暴露于所述凹槽的侧壁。
在本发明提供的半导体结构中，在互连结构的第一接触垫的侧边还设置有第二接触垫，从而可以避免第一接触垫暴露在一较大的空间区域中。如此一来，则在制备所述互连结构时，即可以在所述第二接触垫的保护下，防止所述第一接触垫被过度解析的问题，提高了所形成的第一接触垫的图形精度，进而有利于保障所构成的互连结构的电性传输性能。
附图说明
图1为本发明一实施例中的半导体结构的示意图；
图2为本发明一实施例中的半导体结构的形成方法的流程示意图；
图3a～图3f为本发明一实施例中的半导体结构的形成方法在其制备过程中的结构示意图。
其中，附图标记如下：
100-衬底；
110-第一源/漏区；
120-第二源/漏区；
200-栅极导电层；
210-第三导电层；
220-第四导电层；
230-第五导电层；
300-层间介质层；
310-遮蔽层；
320-隔离侧墙；
321-第一隔离层；
322-第二隔离层；
323-第三隔离层；
330-隔离介质层；
400-互连结构；
410-接触插塞；
420-第一接触垫；
500-第二接触垫；
600-绝缘填充层；
610-空隙；
600a-凹槽；
700-导电材料层；
700a-接触孔；
710-第一导电层；
720-第二导电层。
具体实施方式
如背景技术所述，现有的半导体结构中常常会出现互连结构中的接触垫的图形变形的问题。
针对这一技术问题，本发明的发明人经过研究后发现，在制备互连结构时一般会利用图形化工艺界定出接触垫的图形，然而，在具体的图形化处理中，图形化精度常常会受到图形的密集程度的影响。具体而言，当图形排布过于密集时，则容易出现图形解析不开而导致相邻图案相互粘连的现象；而当图形排布过于稀疏时，则容易导致所形成的图案被过度解析而出现波纹或缺口的问题。而针对互连结构而言，其接触垫通常是孤立的形成在一较大的空间区域中，基于此，则在制备所述接触垫时，即容易使得所形成的接触垫的图形形貌发生变形，如此将会进一步影响互连结构的电性传输性能。
有鉴于此，本发明提供了一种半导体结构，以改善如上所述的互连结构中的接触垫容易出现图形变形的问题。
以下结合附图和具体实施例对本发明提出的半导体结构及其形成方法作 进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
图1为本发明一实施例中的半导体结构的示意图，如图1所示，所述半导体结构包括：
衬底100，所述衬底100上形成有至少一半导体器件和层间介质层300，所述层间介质层300覆盖所述半导体器件；
互连结构400，所述互连结构400包括接触插塞410和第一接触垫420，所述接触插塞410贯穿所述层间介质层300并延伸至所述半导体器件，以和所述半导体器件电性连接，所述第一接触垫420覆盖所述接触插塞410的顶部并横向延伸，以覆盖部分所述层间介质层300的顶表面；以及，
第二接触垫500，形成在所述层间介质层300的顶表面上，并间隔位于所述第一接触垫420的侧边。
本实施例中，通过在所述第一接触垫420的侧壁分布所述第二接触垫500，从而避免了所述第一接触垫420被暴露在一较大的空间区域中，有利于提高所形成的第一接触垫420的形貌。例如，在制备所述第一接触垫420时，由于还会在第一接触垫420的侧边形成所述第二接触垫500，从而在第二接触垫500的保护下，能够缓解第一接触垫420受到较大的刻蚀攻击，避免所形成的第一接触垫420出现刻蚀缺口或变形等缺陷。
其中，所述第一接触垫420和所述第二接触垫500可以利用同一导电材料层形成，即，所述第一接触垫420和所述第二接触垫500的材料相同。本实施例中，所述第一接触垫420和所述第二接触垫500均包括第一导电层710和第二导电层720，所述第二导电层720形成在所述第一导电层710上。并且，所述第一接触垫420中的第一导电层710和第二接触垫500中的第一导电层710的材料相同，所述第一接触垫420中的第二导电层720和第二接触垫500中第二导电层720的材料相同。其中，所述第一导电层710的材料例如包括氮化钛，所述第二导电层720的材料例如包括钨。
进一步的，所述互连结构400中的接触插塞410和所述第一接触垫420 可以同时形成并具有相同的材料。即在本申请实施例中，所述接触插塞410也包括第一导电层710和第二导电层720，所述第二导电层720形成在所述第一导电层710上。具体的，所述层间介质层300中形成有接触孔，所述接触插塞410即形成在所述接触孔中。以及，所述接触插塞410中的第一导电层710覆盖所述接触孔的内壁，所述接触插塞410中的所述第二导电层720填充所述接触孔。
继续参考图1所述，在可选的方案中，所述第一接触垫420和所述第二接触垫500之间还具有凹槽600a，并且所述凹槽600a还向下延伸停止于所述层间介质层300中。
具体而言，在利用同一导电材料层同时制备所述第一接触垫420和第二接触垫500时，为了确保所形成的第一接触垫420和第二接触垫500之间的电性隔离，则可以在刻蚀所述导电材料层之后，进一步刻蚀第一接触垫420和第二接触垫500之间的层间介质层300，以确保所述第一接触垫420和第二接触垫500相互分断，并形成所述凹槽600a。
本实施例中，所述半导体结构还包括绝缘填充层600，所述绝缘填充层600填充在所述凹槽600a中，并覆盖所述第一接触垫420和第二接触垫500暴露在所述凹槽600a的侧壁。
进一步的，填充在所述凹槽600a中的绝缘填充层600中还可以形成有空隙610。本实施例中，所述空隙610沿着高度方向竖直延伸在所述凹槽600a的中间区域中。
可选的，所述空隙610的顶部高出于层间介质层300的顶表面，以使所述空隙610具有位于所述第一接触垫420和第二接触垫500之间的部分。即，填充在所述第一接触垫420和所述第二接触垫500相互正对的区域中的绝缘填充层600形成有空隙610，从而可以降低位于第一接触垫420和第二接触垫500之间的介质材料的介电常数，从而能够有效缓解第一接触垫420和第二接触垫500之间的寄生电容。本实施例中，所述空隙610从绝缘填充层600的顶表面向下竖直延伸。
此外，由于所述绝缘填充层600中形成有空隙610，如此还有利于缓解所 述绝缘填充层600的内应力，以避免绝缘填充层600中的高强度内应力损伤邻近的接触垫和半导体器件。例如，当对所述半导体结构执行高温制程时，则所述绝缘填充层600即能够利用所述空隙610实现应力释放，避免所述绝缘填充层600由于高强度应力挤压其他组件而导致其他组件受到损伤的问题。
尤其是，当所述绝缘填充层600是形成在半导体器件的正上方时，则所述绝缘填充层600中的高强度内应力将可能会损伤到所述半导体器件。如图1所示，本实施例中，所述绝缘填充层600即形成在所述半导体器件的正上方。
继续参考图1所示，本实施例中，所述半导体器件例如包括至少一晶体管。其中，所述晶体管包括形成在所述衬底100顶表面上的栅极导电层200，以及形成在所述衬底100中的第一源/漏区110和第二源/漏区120，所述第一源/漏区110和所述第二源/漏区120分别位于所述栅极导电层200的两侧。
本实施例中，所述栅极导电层200包括堆叠设置的第三导电层210、第四导电层220和第五导电层230。其中，所述第三导电层210的材料例如包括多晶硅，所述第四导电层220的材料例如包括氮化钛，所述第五导电层230的材料例如包括钨。
进一步的，所述层间介质层300包括覆盖栅极导电层200顶表面的遮蔽层310。其中，所述接触插塞410形成在所述栅极导电层200的侧边，并且所述接触插塞410的底部竖直延伸至衬底100的第一源/漏区110或第二源/漏区120，以利用至少两个接触插塞410一一对应连接所述第一源/漏区110和第二源/漏区120，所述接触插塞410的顶部高于所述栅极导电层的顶部。以及，所述第一接触垫420即从所述栅极导电层200的侧边横向延伸至所述遮蔽层310上。即，所述第一接触垫420至少部分位于所述栅极导电层200的正上方。
本实施例中，所述第二接触垫500也可形成在所述遮蔽层310上，并与所述第一接触垫420间隔设置。本实施例中，位于所述第一接触垫420和所述第二接触垫500之间的凹槽600a即形成在所述遮蔽层310中，以及所述绝缘填充层600也相应的部分填充在所述遮蔽层310中。即，所述绝缘填充层600和所述栅极导电层200沿着高度方向的投影具有相互重叠的区域。
其中，所述第一接触垫420和所述第二接触垫500之间的间隔尺寸、以 及第一接触垫420和第二接触垫500的宽度尺寸均可以根据实际情况调整。具体而言，可以根据当前光刻工艺和刻蚀工艺的解析精度，对应调整所述第一接触垫420和第二接触垫500的间隔尺寸，以及调整第一接触垫420和第二接触垫500的宽度尺寸，只要满足当前工艺的解析精度下所对应的图形密集度即可。
例如，可使所述第一接触垫420和第二接触垫500的间隔尺寸小于栅极导电层200的宽度尺寸，如此一来，则在制备第一接触垫420的过程中，即可确保第二接触垫500能够对第一接触垫420的图形保护。
本实施例中，还使所述第一接触垫420中覆盖所述遮蔽层310的宽度尺寸小于所述第二接触垫500的宽度尺寸。由于第一接触垫420是从遮蔽层310的边缘往遮蔽层310的中心延伸，所述第二接触垫500是形成在所述遮蔽层310上，因此当所述第一接触垫420中覆盖所述遮蔽层310的宽度尺寸小于所述第二接触垫500的宽度尺寸时，即相当于位于第一接触垫420和第二接触垫500之间的凹槽600a偏离遮蔽层310的中心区域，并且所述凹槽600a是以靠近第一接触垫420的方向偏离遮蔽层310的中心区域。
继续参考图1所示，所述层间介质层300还包括覆盖栅极导电层200侧壁的隔离侧墙320。本实施例中，所述隔离侧墙320还覆盖所述遮蔽层310的侧壁。以及，所述接触插塞410形成在所述隔离侧墙320远离所述栅极导电层200的一侧，所述第一接触垫420横向延伸并覆盖与所述接触插塞410邻近的隔离侧墙320。
具体的，所述隔离侧墙320例如为依次覆盖所述栅极导电层200的叠层结构。本实施例中，所述隔离侧墙320包括依次覆盖栅极导电层200的第一隔离层321、第二隔离层322和第三隔离层323。其中，所述第一隔离层321和所述第三隔离层323可以采用相同的材料形成，例如均包括氧化硅，所述第二隔离层322的材料例如包括氮化硅，由此即可构成ONO结构的隔离侧墙320。
进一步的，所述层间介质层300还包括隔离介质层330，所述隔离介质层330形成在所述栅极导电层200的外围。本实施例中，所述隔离介质层330即 围绕在所述隔离侧墙320的外围，以及所述导电插塞410贯穿所述隔离介质层330。
此外，在具体的实施例中，所述衬底100上可以形成有至少两个晶体管。本实施例的附图1中仅示意性的示出了两个晶体管，并且所述两个晶体管可共用第一源/漏区110。其中，与共用的第一源/漏区110电性连接的接触插塞410即形成在两个晶体管之间，以及对应的第一接触垫420则往两个晶体管分别横向延伸至两个晶体管的栅极导电层的上方。
下面对本实施例中的半导体结构的形成方法进行详细说明。图2为本发明一实施例中的半导体结构的形成方法的流程示意图，图3a～图3f为本发明一实施例中的半导体结构的形成方法在其制备过程中的结构示意图。
首先执行步骤S100，具体参考图3a所示，提供一衬底100，所述衬底100上形成有至少一半导体器件以及覆盖所述半导体器件的层间介质层300。
本实施例中，所述半导体器件包括晶体管。所述晶体管进一步包括形成在所述衬底100顶表面上的栅极导电层200，以及形成在所述衬底100中的第一源/漏区110和第二源/漏区120。
进一步的，所述层间介质层300包括覆盖所述栅极导电层200顶表面的遮蔽层310。本实施例中，所述遮蔽层310和所述栅极导电层200可以基于同一道光刻工艺形成。
具体的，所述层间介质层300中的遮蔽层310和所述栅极导电层200的形成方法包括：
步骤一，依次形成栅极材料层和遮蔽材料层在所述衬底100上；
步骤二，执行光刻工艺和刻蚀工艺，图形化所述遮蔽材料层，以形成所述遮蔽层310；
步骤三，可以利用所述遮蔽层310为掩膜层，刻蚀所述栅极材料层，以形成所述栅极导电层200。
本实施例中，所述栅极材料层包括堆叠设置的多层材料层，以及刻蚀所述栅极材料层时即依次刻蚀所述多层材料层，以分别形成第三导电层210、第 四导电层220和第五导电层230，进而构成所述栅极导电层200。
进一步的方案中，所述层间介质层300的形成方法还包括：形成所述隔离侧墙320在所述栅极导电层200和所述遮蔽层310的侧壁。
继续参考图3a所示，所述层间介质层300的形成方法还包括：形成隔离介质层330在所述栅极导电层200的外围。本实施例中，所述隔离介质层330围绕在所述隔离侧墙320的外围。
其中，可以利用平坦化工艺形成所述隔离介质层330。具体的，在沉积隔离介质材料层之后，以所述遮蔽层310为研磨停止层对所述隔离介质材料层执行化学机械研磨工艺，以使所形成的隔离介质层330的顶表面与所述遮蔽层310的顶表面齐平。
接着执行步骤S200，具体参考图3b所示，形成接触孔700a在所述层间介质层300中，所述接触孔700a贯穿所述层间介质层300并延伸至所述半导体器件。
本实施例中，所述接触孔700a贯穿所述隔离介质层330，并延伸至衬底100的顶表面以暴露出所述衬底100。
接着执行步骤S300，具体参考图3c所示，形成导电材料层700在所述层间介质层300上，所述导电材料层700填充所述接触孔700a，并覆盖所述层间介质层300的顶表面。
具体的，可以利用沉积工艺和平坦化工艺形成所述导电材料层700。具体的，所述导电材料层700的形成方法包括：
第一步骤，沉积第一导电层710在所述层间介质层300上，所述第一导电层710保形的覆盖所述接触孔700a的内壁和层间介质层300的顶表面；
第二步骤，形成第二导电层720在所述第一导电层710上，所述第二导电层720填充所述接触孔700a并覆盖所述层间介质层300的顶表面。其中，所述第二导电层720为平坦化后的膜层，以使所述第二导电层720具有平坦的顶表面。
接着执行步骤S400，具体参考图3d所示，图形化所述导电材料层700，以形成互连结构400和第二接触垫500。其中，所述互连结构400包括填充在所述接触孔中的接触插塞410以及覆盖所述接触插塞410顶部的第一接触垫420，并且所述第二接触垫500间隔位于所述第一接触垫420的侧边。
具体的，图形化所述导电材料层700以形成互连结构400和第二接触垫500的方法包括：
首先，形成掩膜层(图中未示出)在所述导电材料层700上，所述掩膜层具有第一掩膜图案和第二掩膜图案。其中，所述第一掩膜图案即对应所述互连结构的图案，所述第二掩膜图案对应所述第二接触垫的图案。即，所述第一掩膜图案覆盖所述接触孔的区域，以及覆盖接触孔外周的部分区域；所述第二掩膜图案位于所述第一掩膜图案的侧边，并与所述第一掩膜图案间隔预定尺寸；
接着，以所述掩膜层为掩膜刻蚀所述导电材料层700，以形成对应于所述第一掩膜图案的所述互连结构400，以及对应于所述第二掩膜图案的所述第二接触垫500。
本实施例中，所述第一接触垫420从所述接触插塞410进一步横向延伸至所述遮蔽层310上，以及所述第二接触垫500也至少部分形成在所述遮蔽层310上，并与所述第一接触垫420间隔预定尺寸。
可选的方案中，具体参考图3e所示，在刻蚀所述导电材料层700之后，还包括：进一步刻蚀所述第一接触垫420和所述第二接触垫500之间的层间介质层300，并刻蚀停止于所述层间介质300中，以形成凹槽600a，从而可以确保第一接触垫420和第二接触垫500相互分断。
具体可以利用所述第一接触垫420和第二接触垫500为掩膜，刻蚀暴露出的层间介质层300，以形成所述凹槽600a。本实施例中，所述凹槽600a从所述第一接触垫420和第二接触垫500之间向下延伸至遮蔽层310中，并位于所述栅极导电层200的正上方。此外，本实施例中，在所述第二接触垫500远离第一接触垫420的一侧也可形成有凹槽。
进一步的，具体参考图3f所示，所述半导体结构的形成方法还包括：填充绝缘填充层600在所述凹槽600a中，所述绝缘填充层600还覆盖所述第一接触垫420和所述第二接触垫500暴露于所述凹槽600a的侧壁。
本实施例中，所述绝缘填充层600中还可以形成有空隙610，通过所述空隙610将有利于实现绝缘填充层600的应力释放。其中，所述空隙610例如为沿着高度方向竖直延伸在所述凹槽600a的中间区域。
综上所述，本实施例提供的半导体结构中，通过在互连结构其第一接触垫的侧边间隔设置第二接触垫，从而可以避免第一接触垫暴露在一较大的空间区域中。如此一来，则在制备所述互连结构时，通过图形化处理以形成第一接触垫并不是孤立的暴露在较大的空间区域中，而是在第二接触垫的保护下，避免了第一接触垫被过度解析的问题，有利于提高所形成的第一接触垫的图形精度，进而有利于保障所构成的互连结构的电性传输性能。或者，也可以理解为，本实施例中，通过调整对应于第一接触垫的区域的图形密集度，以提高对应于第一接触垫的图形解析度，从而形成具有良好图形形貌的第一接触垫。
需要说明的是，虽然本发明已以较佳实施例披露如上，然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围。
还应当理解的是，除非特别说明或者指出，否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。
此外还应该认识到，此处描述的术语仅仅用来描述特定实施例，而不是用来限制本发明的范围。必须注意的是，此处的以及所附权利要求中使用的单数形式“一个”和“一种”包括复数基准，除非上下文明确表示相反意思。 例如，对“一个步骤”或“一个装置”的引述意味着对一个或多个步骤或装置的引述，并且可能包括次级步骤以及次级装置。应该以最广义的含义来理解使用的所有连词。以及，词语“或”应该被理解为具有逻辑“或”的定义，而不是逻辑“异或”的定义，除非上下文明确表示相反意思。此外，本发明实施例中的方法和/或设备的实现可包括手动、自动或组合地执行所选任务。

Claims (17)

  1. 一种半导体结构，其特征在于，包括：
    衬底，所述衬底上形成有至少一个半导体器件和层间介质层，所述层间介质层覆盖每个所述半导体器件；
    互连结构，包括接触插塞和第一接触垫，所述接触插塞贯穿所述层间介质层并延伸至所述半导体器件，所述第一接触垫覆盖所述接触插塞的顶部，并延伸覆盖部分所述层间介质层的顶表面；以及，
    第二接触垫，形成在所述层间介质层的顶表面上，并间隔位于所述第一接触垫的侧边。
  2. 如权利要求1所述的半导体结构，其特征在于，所述半导体器件包括形成在所述衬底顶表面上的栅极导电层，所述层间介质层包括覆盖所述栅极导电层顶表面的遮蔽层；其中，所述接触插塞形成在所述栅极导电层的侧边，所述第一接触垫从所述栅极导电层的侧边横向延伸至所述遮蔽层上。
  3. 如权利要求2所述的半导体结构，其特征在于，所述第二接触垫形成在所述遮蔽层上，并与所述第一接触垫间隔设置。
  4. 如权利要求3所述的半导体结构，其特征在于，所述第一接触垫中覆盖所述遮蔽层的部分的宽度尺寸小于所述第二接触垫的宽度尺寸。
  5. 如权利要求2所述的半导体结构，其特征在于，所述层间介质层还包括覆盖所述栅极导电层侧壁的隔离侧墙，所述接触插塞形成在所述隔离侧墙远离所述栅极导电层的一侧，所述第一接触垫横向延伸并覆盖与所述接触插塞邻近的所述隔离侧墙。
  6. 如权利要求2所述的半导体结构，其特征在于，所述层间介质层还包括形成在所述栅极导电层外围的隔离介质层，所述导电插塞贯穿所述隔离介质层。
  7. 如权利要求1所述的半导体结构，其特征在于，所述第一接触垫和所述第二接触垫的材料相同。
  8. 如权利要求7所述的半导体结构，其特征在于，所述第一接触垫和所 述第二接触垫均包括第一导电层和形成在所述第一导电层上的第二导电层，并且所述第一接触垫中的第一导电层和所述第二接触垫中的第一导电层的材料相同，所述第一接触垫中的第二导电层和所述第二接触垫中的第二导电层的材料相同。
  9. 一种半导体结构，其特征在于，包括：
    衬底，所述衬底上形成有至少一个半导体器件和层间介质层，所述层间介质层覆盖每个所述半导体器件；
    互连结构，包括接触插塞和第一接触垫，所述接触插塞贯穿所述层间介质层并延伸至所述半导体器件，所述第一接触垫覆盖所述接触插塞的顶部，并延伸覆盖部分所述层间介质层的顶表面；以及，
    第二接触垫，形成在所述层间介质层的顶表面上，并间隔位于所述第一接触垫的外围；以及，
    位于所述第一接触垫和所述第二接触垫之间的凹槽，所述凹槽还向下延伸停止于所述层间介质层中。
  10. 如权利要求9所述的半导体结构，其特征在于，所述凹槽暴露出所述第一接触垫的部分侧壁以及所述第二接触垫的部分侧壁，所述半导体结构还包括：
    绝缘填充层，填充在所述凹槽中并覆盖所述第一接触垫和所述第二接触垫暴露于所述凹槽的侧壁。
  11. 如权利要求10所述的半导体结构，其特征在于，所述绝缘填充层中形成有空隙。
  12. 如权利要求9所述的半导体结构，其特征在于，所述半导体器件包括形成在所述衬底顶表面上的栅极导电层，所述层间介质层包括覆盖栅极导电层顶表面的遮蔽层；
    其中，所述接触插塞形成在所述栅极导电层的侧边，所述第一接触垫从所述栅极导电层的侧边横向延伸至所述遮蔽层上，所述第二接触垫形成在所述遮蔽层上并与所述第一接触垫间隔设置，以及所述凹槽在所述第一接触垫和所述第二接触垫之间向下延伸停止于所述遮蔽层中。
  13. 一种半导体结构的形成方法，其特征在于，包括：
    提供一衬底，所述衬底上形成有至少一个半导体器件以及覆盖每个所述半导体器件的层间介质层；
    形成接触孔在所述层间介质层中，所述接触孔贯穿所述层间介质层并延伸至所述半导体器件；
    形成导电材料层在所述层间介质层上，所述导电材料层填充所述接触孔，并覆盖所述层间介质层的顶表面；以及，
    图形化所述导电材料层，以形成互连结构和第二接触垫，其中所述互连结构包括填充在所述接触孔中的接触插塞以及覆盖所述接触插塞顶部的第一接触垫，并且所述第二接触垫间隔位于所述第一接触垫的侧边。
  14. 如权利要求13所述的半导体结构的形成方法，其特征在于，图形化所述导电材料层的方法包括：
    形成掩膜层在所述导电材料层上，所述掩膜层具有第一掩膜图案和第二掩膜图案，所述第一掩膜图案覆盖所述接触孔的区域以及接触孔外周的部分区域，所述第二掩膜图案位于所述第一掩膜图案的侧边，并与所述第一掩膜图案间隔预定尺寸；以及，
    以所述掩膜层为掩膜刻蚀所述导电材料层，以形成对应于所述第一掩膜图案的所述互连结构，以及对应于所述第二掩膜图案的所述第二接触垫。
  15. 如权利要求13所述的半导体结构的形成方法，其特征在于，图形化所述导电材料层之后，还包括：
    刻蚀所述第一接触垫和所述第二接触垫之间的所述层间介质层，并刻蚀停止于所述层间介质层中，以形成凹槽。
  16. 如权利要求15所述的半导体结构的形成方法，其特征在于，所述凹槽暴露出所述第一接触垫的部分侧壁以及所述第二接触垫的部分侧壁，在形成所述凹槽之后，还包括：
    填充绝缘填充层在所述凹槽中，所述绝缘填充层还覆盖所述第一接触垫和所述第二接触垫暴露于所述凹槽的侧壁。
  17. 如权利要求16所述的半导体结构的形成方法，其特征在于，所述绝 缘填充层中形成有空隙。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907788A (en) * 1994-07-29 1999-05-25 Nec Corporation Semiconductor device capable of easily filling contact conductor plug in contact hole
US20090115065A1 (en) * 2007-11-06 2009-05-07 Cheon-Man Shim Semiconductor device and manufacturing method thereof
US9502267B1 (en) * 2014-06-26 2016-11-22 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with support structure and method of manufacture thereof
US20190198468A1 (en) * 2017-12-26 2019-06-27 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476690B1 (ko) * 2003-01-17 2005-03-18 삼성전자주식회사 반도체 장치 및 그 제조방법
US8940635B1 (en) * 2013-08-30 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming interconnect structure
KR102472133B1 (ko) * 2016-09-22 2022-11-29 삼성전자주식회사 집적회로 소자
US10825910B1 (en) * 2019-04-17 2020-11-03 Globalfoundries Inc. Shaped gate caps in dielectric-lined openings

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907788A (en) * 1994-07-29 1999-05-25 Nec Corporation Semiconductor device capable of easily filling contact conductor plug in contact hole
US20090115065A1 (en) * 2007-11-06 2009-05-07 Cheon-Man Shim Semiconductor device and manufacturing method thereof
US9502267B1 (en) * 2014-06-26 2016-11-22 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with support structure and method of manufacture thereof
US20190198468A1 (en) * 2017-12-26 2019-06-27 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same

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