WO2020125515A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2020125515A1
WO2020125515A1 PCT/CN2019/124588 CN2019124588W WO2020125515A1 WO 2020125515 A1 WO2020125515 A1 WO 2020125515A1 CN 2019124588 W CN2019124588 W CN 2019124588W WO 2020125515 A1 WO2020125515 A1 WO 2020125515A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive
isolation
trench
insulating
Prior art date
Application number
PCT/CN2019/124588
Other languages
English (en)
French (fr)
Inventor
童宇诚
周运帆
黄德浩
朱贤士
黄丰铭
Original Assignee
福建省晋华集成电路有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 福建省晋华集成电路有限公司 filed Critical 福建省晋华集成电路有限公司
Priority to US16/635,208 priority Critical patent/US11145715B2/en
Publication of WO2020125515A1 publication Critical patent/WO2020125515A1/zh
Priority to US17/465,803 priority patent/US11688764B2/en
Priority to US18/140,595 priority patent/US20230261046A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a method for forming the same.
  • Shallow trench isolation is currently the main method used to achieve device isolation in large-scale integrated circuits.
  • the trench isolation structure can be used to isolate adjacent active areas (Active Areas, AA) from each other, so that components formed on different active areas can be prevented from interfering with each other.
  • AA Active Areas
  • a large number of electrical conductive structures are usually provided, and the electrical conductive structures can be used, for example, to implement electrical transmission, or only as redundant components (ie, do not implement electrical functions).
  • the electrical conductive structure in the integrated circuit will deviate from the trench isolation structure. Based on this, it is necessary to reserve a certain accommodating space for the electrical conductive structure.
  • An object of the present invention is to provide a semiconductor structure to facilitate the reduction of the overall size of a semiconductor integrated circuit.
  • the present invention provides a semiconductor structure, including:
  • a trench isolation structure is formed in an isolation trench of a substrate, wherein the trench isolation structure includes multiple layers of insulating layers, the multiple layers of insulating layers sequentially cover the inner wall of the isolation trench, and the multiple layers The top surface of the insulating layer in the innermost layer of the insulating layer sinks more than the top surface of the substrate to form a first groove in the isolation trench; and,
  • the present invention also provides a method for forming a semiconductor structure, including:
  • first conductive layer and a second conductive layer Forming a first conductive layer and a second conductive layer on the substrate, and the first conductive layer completely fills the first groove and extends upward from the isolation trench, the second conductive layer is formed on On the first conductive layer.
  • the semiconductor structure provided by the present invention based on the trench isolation structure formed in the substrate, at least part of the electrically conductive structure is further formed on the trench isolation structure, so that the space above the trench isolation structure can be effectively utilized, Correspondingly, the additional space reserved for the electrically conductive structure can be reduced, and even no space needs to be reserved for the electrically conductive structure. In this way, it is conducive to reducing the size of the formed semiconductor integrated circuit.
  • FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the invention.
  • FIG. 2 is a schematic flowchart of a method for forming a semiconductor structure in an embodiment of the invention
  • FIG. 3a to FIG. 3d are schematic structural views of a semiconductor structure in the preparation process of an embodiment of the invention.
  • FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present invention. As shown in FIG. 1, the semiconductor structure in this embodiment includes:
  • the trench isolation structure 200 is formed in the isolation trench 200a of a substrate 100, and at least a part of the top surface of the trench isolation structure 200 is more sinking relative to the top surface of the substrate 100; and,
  • An electrically conductive structure 300 is formed on the substrate 100.
  • the electrically conductive structure 300 is at least partially located above the trench isolation structure 200 and fills the isolation trench 200a.
  • the electrically conductive structure 300 includes a first conductive layer 310a and a second conductive layer 320a, the first conductive layer 310a fills the isolation trench 200a and extends out of the isolation trench 200a, the second The conductive layer 320a is formed on the first conductive layer 310a.
  • the first conductive layer 310a extends out of the isolation trench 200a, so that the entire top surface of the first conductive layer 310a is higher than the top surface of the substrate 100.
  • the space above the trench isolation structure 200 can be effectively used, so that the accommodation space reserved for the electrically conductive structure can be reduced, or There is no need to reserve space for the electrically conductive structure 300, which is beneficial to reducing the size of the entire integrated circuit.
  • the electrically conductive structure 300 formed on the trench isolation structure 200 is partially embedded in the isolation trench 200a, this does not affect the performance of the electrically conductive structure 300. Big impact. For example, when the electrically conductive structure 300 is used to realize electrical transmission, although the electrically conductive structure 300 is partially filled in the isolation trench 200a, this can still make the first conductive layer 310a and the second conductive layer The electrical transmission performance of 320a meets the requirements; or, when the electrical conductive structure 300 is used to form a redundant component, such as a dummy gate (Dummy Gate), the redundant component does not need to be implemented at this time There is no problem with the electrical function, and thus the function is affected.
  • a redundant component such as a dummy gate (Dummy Gate)
  • the projected area of the second conductive layer 320a in the height direction is not less than the area of the top surface of the first conductive layer 310a. That means that the top surface of the first conductive layer 310a is not exposed under the direct or indirect coverage of the second conductive layer 320a, so that the first conductive layer 310a is conductive with respect to the second Only the side walls of layer 320a are laterally exposed.
  • the material of the first conductive layer 310a includes, for example, doped polysilicon (poly), and the second conductive layer 320a may be a metal layer, for example, the material of the second conductive layer 320a includes tungsten (W).
  • the trench isolation structure 200 has multiple insulating layers, the multiple insulating layers sequentially cover the inner wall of the isolating trench 200a, and the top surface of the innermost insulating layer among the multiple insulating layers is opposite The top surface of the substrate sinks further to form a first groove in the isolation trench 200a.
  • the sidewall boundary of the electrically conductive structure 300 is between the boundary of the first groove and the boundary of the isolation trench 200a, so that the electrically conductive structure 300 completely fills
  • the first groove that is, the first conductive layer 310a of the electrically conductive structure 300 is at least partially formed on the innermost insulating layer to completely fill the first groove and further extend up the isolation trench ⁇ 200a.
  • the “side wall boundary of the electrically conductive structure” described here is, for example, a side wall extending along the longitudinal direction of the electrically conductive structure.
  • the multilayer insulation layer in the trench isolation structure 200 includes a first insulation layer 210, a second insulation layer 220 and a third insulation layer 230.
  • the first insulating layer 210 and the second insulating layer 220 sequentially conformally cover the inner wall of the isolation trench 200a, and the third insulating layer 230 is located at the innermost layer of the multilayer insulating layer to fill the The isolation trench 200a is described.
  • the second insulating layer 220 is located between the first insulating layer 210 and the third insulating layer 230, and the third insulating layer 230 constitutes the innermost layer of the trench isolation structure 200, and the third The top surface of the insulating layer 230 is lower than the top of the isolation trench 200a, thereby making the third insulating layer 230 sink more with respect to the top surface of the substrate 100.
  • the top surface of the third insulating layer 230 is still lower than the top surface of the second insulating layer 220, so that the first groove is surrounded by the second insulating layer 220 in the third insulation Above layer 230.
  • the boundary of the sidewall of the electrically conductive structure 300 exceeds the boundary of the sidewall of the third insulating layer 230 and overlaps the second insulating layer 220. It can be understood that the width of the electrically conductive structure 300 in the predetermined direction is larger than the opening of the first groove surrounded by the second insulating layer, and is smaller than the width of the trench isolation structure 200.
  • the first conductive layer 310a in the electrically conductive structure 300 fills the first groove surrounded by the second insulating layer 220 to cover the third insulating layer 230 and the second
  • the insulating layer 220 is close to the side wall of the third insulating layer and further extends out of the first groove so that the boundary of the side wall of the first conductive layer 310a overlaps the top of the second insulating layer 220
  • the first conductive layer 310a has a side wall extending out of the first groove.
  • the top surface of the first insulating layer 210 may also sink more relative to both the second insulating layer 220 and the substrate 100, so that the second insulating layer 220 may A side wall, the side wall of the isolation trench 200a, and the top surface of the first insulating layer 210 surround a micro second groove, and the second groove is correspondingly located on the second insulating layer 220 and the isolation Between the sidewalls of the trench.
  • the first insulating layer 210 and the third insulating layer 230 may include the same material, and the second insulating layer 220 may have a material different from that of the third insulating layer 230.
  • the top surfaces of the first insulating layer 210 and the third insulating layer 230 are both below the top surface of the substrate 100 Shen.
  • the second insulating layer 220 may have a material different from that of the third insulating layer 230, through the etch-back process, the first insulating layer 210 and the third insulating layer 230 may both be lower than the The top surface of the second insulating layer 220.
  • the materials of the first insulating layer 210 and the third insulating layer 230 both include silicon oxide (SiO), and the materials of the second insulating layer 220 include silicon nitride (SiN), for example.
  • the trench isolation structure 200 is presented as an ONO structure to improve the isolation performance of the trench isolation structure 200.
  • the semiconductor structure further includes a sidewall structure 400 that covers at least the sidewall of the electrically conductive structure 300 so that the sidewall structure 400 covers at least the first
  • the sidewall of the isolation trench 200a and the sidewall of the second conductive layer 320a extend from a conductive layer 310a.
  • the width dimension of the electrically conductive structure 300 in a predetermined direction is larger than the width dimension of the third insulating layer 230 and smaller than the width dimension of the trench isolation structure 200, so that the electrical property
  • the conductive structure 300 does not cover the second groove between the second insulating layer and the sidewall of the isolation trench.
  • the sidewall structure 400 may be further extended to cover the second insulating layer 220 and the first insulating layer 210, so that the sidewall structure 400 is also embedded in the second groove. That is, the second groove is also filled with the sidewall structure 400, so that the gap of the edge portion of the isolation trench 200a can be compensated.
  • the side wall structure 400 may be a single-layer structure or a laminated structure.
  • the sidewall structure 400 includes a first isolation layer 410 and a second isolation layer 420, and the first isolation layer 410 and the second isolation layer 420 sequentially cover the side of the electrically conductive structure 300 Walls, and conform to the second insulating layer 220 to further fill the second groove.
  • the first isolation layer 410 and the second isolation layer 420 may have different materials, for example, the material of the first isolation layer 410 includes silicon oxide, and the material of the second isolation layer 420 includes nitrogen Silicone.
  • the sidewall structure may further include three isolation layers, and the three isolation layers sequentially cover the sidewalls of the electrically conductive structure.
  • the materials of the three isolation layers in the sidewall structure are, for example, silicon oxide, silicon nitride, and silicon oxide, so as to form the isolation structure of the ONO structure.
  • the trench isolation structure 200 further defines a first groove in the isolation trench 200a, the first conductive layer 310a fills the first groove in the isolation trench 200a, and the The side wall boundary of the first conductive layer 310a is also overlapped on the top of the side wall of the first groove. And, the trench isolation structure 200 further defines a second groove in the isolation trench 200a, the second groove is located on the side of the first groove, and can make the sidewall structure 400 fills the second groove to compensate for the gap in the edge region of the isolation trench 200a.
  • the boundary of the side wall of the first conductive layer 310a also overlaps the top of the side wall of the first groove, so that the first conductive layer 310a A first depression is formed on the top surface corresponding to the isolation trench 200a (more specifically, a first depression is formed on the top surface corresponding to the first groove in the first conductive layer 310a), and the The bottom of the first recess is higher than the top of the isolation trench 200a.
  • the second conductive layer 320a is located above the first conductive layer 310a, so that the bottom surface of the second conductive layer 320a corresponding to the isolation trench 200a can be oriented toward the first conductive layer 310a
  • the direction is convex, and the top surface of the second conductive layer 320a corresponding to the isolation trench 200a is recessed toward the first conductive layer 310a to form a second recess.
  • the position of the first recess on the first conductive layer 310a corresponds to the position of the second recess on the second conductive layer 320a, more specifically, the first recess on the first conductive layer 310a
  • the bottom of the recess and the bottom of the second recess on the second conductive layer 320a are aligned on the same vertical line.
  • the electrically conductive structure 300 further includes a third conductive layer 330a, and the third conductive layer 330a is formed between the first conductive layer 310a and the second conductive layer 320a.
  • the material of the third conductive layer 330a includes titanium nitride, for example.
  • the third conductive layer 330a conformally covers the top surface of the first conductive layer 310a, so that the third conductive layer 330a corresponds to the first depression of the first conductive layer 310a and appears curved Folded structure. That is, the bottom of the third conductive layer 330a corresponding to the first recess protrudes into the first recess, so that the top surface of the third conductive layer 330a corresponding to the first recess is oriented toward the first The direction of the conductive layer 310a is recessed to form a third recess. And, a portion of the second conductive layer 320a close to the third conductive layer protrudes into the third recess.
  • the electrically conductive structure 300 further includes a shielding layer 340a, the shielding layer 340a is formed on the second conductive layer 320a, and the top surface of the shielding layer 340a is opposite to the first
  • the top surface of the two conductive layers 320a is more flat.
  • a planarization process may be performed to make the shielding layer 340a have a flat top surface.
  • the bottom surface of the shielding layer 340a corresponding to the second recess and the second recess further surround a gap 341.
  • the top surface of the second conductive layer 320a has a second recess, so that the slit 341 may be formed above the second recess.
  • the semiconductor structure of this embodiment includes at least two trench isolation structures 200, and adjacent trench isolation structures 200 can be used to define an active area (Active Area, AA), and A semiconductor device may also be provided in the active area.
  • an electrically conductive structure is also formed on the active area, and the electrically conductive structure located in the active area may also include a first conductive layer, a third conductive layer, and a second Conductive layer and shielding layer.
  • the electrically conductive structure in the semiconductor device is used to form the gate structure 300b, for example.
  • the gate structure 300b may include a first conductive layer 310b and a second conductive layer 320b, and may further include a third conductive layer 330b and a shielding layer 340b.
  • the gate structure 300b located in the active region and the electrically conductive structure 300 located in the isolation region constitute a semiconductor integrated circuit such as a peripheral circuit of a memory.
  • the gate structure 300b located in the active area may further constitute a switching transistor in a peripheral circuit, for example.
  • the electrically conductive structure 300 located in the isolation region is used, for example, to realize electrical transmission, or to form a dummy gate structure.
  • the electrically conductive structure 300 in the isolation region is used to realize electrical transmission, even if the bottom of the electrically conductive structure 300 extends into the isolation trench 200a, the electrical conductivity structure 300 can still be protected.
  • the width of the electrically conductive structure 300 in the isolation region is smaller than the width of the isolation trench 200a, so that the electrically conductive structure 300 in the isolation region can be prevented from extending into the active region. Disturb the semiconductor devices in the active area.
  • the electrical conductive structure 300 in the isolation region is used to form the dummy gate structure 300a as an example for further explanation.
  • the gate structure 300b is formed on the top surface of the substrate 100, and the top surface of the first conductive layer 310b in the gate structure 300b is opposite to the first in the dummy gate structure 300a
  • the top surface of the conductive layer 310a is more flat.
  • the top surfaces of the third conductive layer 330b and the second conductive layer 320b in the gate structure 300b are more relative to the top surfaces of the third conductive layer 330a and the second conductive layer 320a in the dummy gate structure 300a For flat.
  • the bottom surface of the shielding layer 340b and the top surface of the second conductive layer 320b are in close contact, so no gap is formed in the shielding layer 340b of the gate structure 300b.
  • the top surface of the first conductive layer 310b in the gate structure 300b is also higher than the top surface of the first conductive layer 310a in the dummy gate structure 300a.
  • the third conductive layer 330b in the gate structure 300b is also higher than the third conductive layer 330a in the dummy gate structure 300a; and, the second conductive layer 320b in the gate structure 300b is also It is higher than the second conductive layer 320a in the dummy gate structure 300a.
  • the top surface of the shielding layer 340b in the gate structure 300b may be flush with the top surface of the shielding layer 340a in the dummy gate structure 300a, that is, located in the trench isolation structure
  • the top surface of the shielding layer and the shielding layer on the active area are coplanar.
  • FIG. 2 is a schematic flowchart of a method for forming a semiconductor structure in an embodiment of the present invention. As shown in FIG. 2, the method for forming a semiconductor structure in this embodiment includes:
  • Step S100 providing a substrate, and forming an isolation trench in the substrate;
  • Step S200 forming a trench isolation structure in the isolation trench, and at least a part of the top surface of the trench isolation structure sinks more than the top surface of the substrate;
  • Step S300 a first conductive layer and a second conductive layer are formed on the substrate, the first conductive layer fills the isolation trench and extends out of the isolation trench, and the second conductive layer is formed on the substrate On the first conductive layer.
  • FIGS. 3a to 3d are schematic structural views of a semiconductor structure in an embodiment of the present invention during its preparation process. The following describes the steps for forming the semiconductor structure in this embodiment in detail with reference to the drawings.
  • the method for forming the isolation trench 200a includes: first, forming a mask layer (not shown in the figure) on the substrate 100 to define the isolation trench by the mask layer Next, the substrate 100 is etched using the mask layer as a mask to form the isolation trench 200a.
  • the opening size of the isolation trench 200a may be gradually reduced from the top of the trench to the bottom of the trench, so that the isolation trench 200a has inclined sidewalls.
  • the isolation trench 200a With forming the isolation trench 200a with inclined sidewalls, when the insulating material is subsequently filled in the isolation trench 200a, the filling performance of the insulating material can be effectively improved to avoid filling in the insulating material layer of the isolation trench 200a There are hollow problems.
  • a trench isolation structure 200 is formed in the isolation trench 200a, and at least a portion of the top surface of the trench isolation structure 200 is relative to the top surface of the substrate 100 Sink more.
  • the trench isolation structure is often prepared by a planarization process, so that the top surface of the formed trench isolation structure is flush with the top surface of the substrate, or even the trench isolation structure It protrudes from the top surface of the substrate (ie, the top surface of the trench isolation structure is higher than the top surface of the substrate).
  • a multi-layer insulating layer is formed in the isolation trench 200a based on an etching process to form a trench isolation structure 200 to at least reduce the height of the innermost insulating layer in the trench isolation structure 200, Thereby, the trench isolation structure 200 formed can be recessed relative to the top surface of the substrate 100.
  • the method for forming the trench isolation structure 200 includes the following steps, for example.
  • Step one a first insulating material layer and a second insulating material layer are sequentially formed on the substrate 100, and the first insulating material layer and the second insulating material layer sequentially conformally cover the isolation trench 200a
  • the inner wall (including the bottom wall and the side walls) of the substrate also covers the top surface of the substrate 100.
  • the first insulating material layer includes, for example, a silicon oxide layer
  • the second insulating material layer includes, for example, a silicon nitride layer.
  • the silicon oxide layer may be formed by an oxidation process
  • the silicon nitride layer may be formed by a chemical vapor deposition process.
  • Step 2 Deposit a third insulating material layer on the substrate 100, the third insulating material layer covers the second insulating material layer and fills the isolation trench 200a.
  • the material of the third insulating material layer includes silicon oxide, for example.
  • Step 3 Perform an etching process to etch the third insulating material layer, the second insulating material layer and the first insulating material layer to remove the third insulating material layer and the second insulating material A portion of the first insulating material layer and the first insulating material layer on the top surface of the substrate, and the remaining third insulating material layer, the second insulating material layer and the first insulating material layer are filled in the isolation trench to A third insulating layer 230, a second insulating layer 220, and a first insulating layer 210 are respectively formed, wherein the top surface of the third insulating layer 230 is lower than the top surface of the substrate 100.
  • the third insulating material layer covers the top layer, so in the etching process, the etchant preferentially etches the third insulating material layer to remove the third insulating material layer located on top of the substrate A portion of the surface, which in turn exposes the second insulating material layer; then, the second insulating material layer on the top surface of the substrate is continuously removed so that the second insulating material layer remaining in the isolation trench 200a constitutes the second insulating layer 220; Then, the exposed first insulating material layer can be etched to form the first insulating layer 210.
  • the etchant also etches the third insulating material layer located in the isolation trench, so that it can remain in the The third insulating material layer in the isolation trench 200a sinks more with respect to the top surface of the substrate 100.
  • the third insulating material layer located in the isolation trench may also be etched using an etchant, thereby remaining in the isolation trench 200a
  • the third insulating material layer and the first insulating material layer both sink more with respect to the top surface of the substrate 100, and constitute a third insulating layer 230 and a first insulating layer 210, respectively.
  • the top surfaces of the first insulating layer 210 and the third insulating layer 230 are both lower than the top surfaces of the second insulating layer 220.
  • the first groove 200b can be surrounded by the second insulating layer 220 in the isolation trench 200a; and, the second insulating layer 220 and the sidewall of the isolation trench 200a can also be used to surround Second groove 200c.
  • trench isolation structures 200 are formed on the substrate 100, and adjacent trench isolation structures 200 can be used to further define an active area of the semiconductor device (Active Area) , AA). In the subsequent process, corresponding semiconductor devices can be prepared in the active region.
  • a first conductive layer 310a and a second conductive layer 320a are formed on the substrate 100, wherein a sidewall boundary of the first conductive layer 310a is interposed between the first Between the boundary of the groove 200b and the boundary of the isolation trench 200a to fill the first groove 200b, and the top of the first conductive layer 310a also extends upward from the isolation trench 200a, the The second conductive layer 320a is formed on the first conductive layer 310a.
  • the first conductive layer 310a and the second conductive layer 320a can be used to form the electrically conductive structure 300.
  • the projected area of the second conductive layer 320a in the height direction may be not less than the area of the top surface of the first conductive layer 310a.
  • the sidewall boundary of the second conductive layer 320a and the sidewall boundary of the first conductive layer 310a coincide.
  • the electrically conductive structure has a portion formed on the trench isolation structure 200, and may further constitute a dummy gate structure 300a.
  • an electrical conductive structure when an electrical conductive structure (dummy gate structure 300a) is prepared on the trench isolation structure 200, an electrical conductive structure may also be prepared on the active area at the same time to form the gate structure 300b In the active area.
  • the method of simultaneously forming the dummy gate structure 300a and the gate structure 300b includes, for example, the following steps.
  • a first conductive material layer is deposited on the substrate 100.
  • the first conductive material layer covers the substrate of the active region, and covers the trench isolation structure 200 and fills the first groove 200b.
  • a first depression is formed in the first conductive material layer corresponding to the top surface of the first groove 200b, and the bottom of the first depression is higher than the top of the isolation trench 200a. That is, the top surface of the first conductive material layer corresponding to the active region is flatter than the top surface of the first conductive material layer corresponding to the isolation region.
  • a second conductive material layer is deposited on the first conductive material layer.
  • the second conductive material layer covers the active region and the isolation region (ie, trench isolation structure), and the bottom surface of the second conductive material layer corresponding to the first recess is correspondingly oriented toward the The direction of the first conductive material layer is convex, and the top surface of the second conductive material layer corresponding to the first recess is recessed toward the first conductive material layer to form a second recess.
  • the second conductive material layer before depositing the second conductive material layer, it further includes: depositing a third conductive material layer on the first conductive material layer. And the second conductive material layer is formed on the third conductive material layer.
  • the second conductive material layer after depositing the second conductive material layer, it further includes: forming a shielding material layer on the second conductive material layer.
  • the shielding material layer may be formed using a planarization process, so that the top surface of the shielding material layer is flatter than the top surface of the second conductive material layer, that is, the shielding material layer is located in The top surface of the isolation region is flush with the top surface of the active region.
  • the second conductive material layer located in the isolation region has a second recess, based on which, when the shielding material layer is deposited, the portion of the shielding material layer corresponding to the second recess A gap is formed.
  • the second conductive material layer and the first conductive material layer are patterned to form a stacked arrangement of the second conductive layer and the first conductive layer.
  • the method for patterning the second conductive material layer and the first conductive material layer includes, for example:
  • a patterned mask layer is formed on the second conductive material layer; in this embodiment, the mask layer is formed on the shielding material layer, and the pattern of the mask layer includes corresponding to the isolation The dummy gate pattern of the area and the gate pattern corresponding to the active area;
  • the second conductive material layer and the first conductive material layer are sequentially etched to form the second conductive layer and the first conductive layer, respectively.
  • the masking layer is also used as a mask to etch the shielding material layer and the third conductive material layer to form the shielding layer and the third conductive layer, respectively.
  • the top surface of the isolation region and the top surface of the active region are flush. Based on this, after forming the shielding layer on the isolation region and the active region, the The top surface of the shielding layer and the shielding layer on the active region are correspondingly coplanar.
  • the first conductive layer, the third conductive layer, the second conductive layer, and the shielding layer are formed in both the isolation region (region corresponding to the trench isolation structure) and the active region .
  • the first conductive layer 310a, the third conductive layer 330a, the second conductive layer 320a, and the shielding layer 340a located in the isolation region are used to form the dummy gate structure 300a; and, the first conductive layer located in the active region 310b, the third conductive layer 330b, the second conductive layer 320b, and the shielding layer 340b are used to constitute the gate structure 300b.
  • the dummy gate structure 300a fills the first groove 200b of the isolation trench 200a, and the sidewall boundary of the dummy gate structure 300a overlaps the second insulating layer 220, that is, the The dummy gate structure 300a does not fill the second groove 200c in the isolation trench 200a.
  • the method for forming a semiconductor structure further includes: Step S400, forming a sidewall structure.
  • the sidewall structure 400 at least covers the side walls of the first conductive layer 310a extending out of the isolation trench and the side walls of the second conductive layer 320a. And, the sidewall structure 400 further extends into the second groove to fill the second groove.
  • a sidewall structure 400 is formed on the sidewall of the dummy gate structure 300a, and a sidewall structure is also formed on the sidewall of the gate structure 300b to cover The sidewalls of the first conductive layer 310b, the third conductive layer 330b, and the second conductive layer 320b in the gate structure 300b.
  • the gate structure 300b can be simultaneously formed in the active region and the dummy gate structure 300a can be simultaneously formed in the isolation region, and the sidewalls of the gate structure 300b and the dummy gate structure 300a can be simultaneously formed.
  • the sidewall structures 400 are formed on the upper sides, which is beneficial to simplify the process.
  • the space above the trench isolation structure can be fully utilized, which is equivalent to reducing the electrical conduction
  • the space occupied by the structure in the entire semiconductor integrated circuit which in turn contributes to the reduction in size of the semiconductor integrated circuit formed.
  • the width of the electrically conductive structure used to form the dummy gate structure is smaller than the opening size of the isolation trench to prevent the dummy gate structure from causing interference to the semiconductor device in the active area (for example, (The gate structure in the source region affects).
  • the same etching process is used to sequentially etch the multiple layers of insulating material. At this time, based on the difference in the etching rate of different insulating materials, the resulting There is a difference in height between multiple insulating layers (for example, in this embodiment, there is a difference in height between the first insulating layer and the second insulating layer).
  • the isolation trench is formed by the second insulating layer and the isolation trench
  • the second groove surrounded by the side wall is not filled by the electrically conductive structure.
  • the side wall structure can further fill the second groove on the basis of covering the side wall of the electrically conductive structure to compensate for the gap at the edge of the isolation trench and ensure the isolation performance of the trench isolation structure.
  • the trench isolation structure is formed by a conventional planarization process
  • the trench isolation structure includes multiple layers of insulating materials
  • a planarization process needs to be performed separately for specific materials of different insulating material layers.
  • the operation steps are more complicated. It can be seen that, in comparison with the conventional process, when preparing the trench isolation structure in this embodiment, the process can be simplified on the basis of ensuring the isolation performance of the trench isolation structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)

Abstract

一种半导体结构及其形成方法。该半导体结构通过将电性传导结构(300)设置在沟槽隔离结构(200)上，以利用沟槽隔离结构(200)上方的空间，从而可以缩减电性传导结构(300)在整个半导体集成电路中所占用的空间，进而有利于实现所构成的半导体集成电路的尺寸缩减。

Description

半导体结构及其形成方法 技术领域
本发明涉及半导体技术领域，特别涉及一种半导体结构及其形成方法。
背景技术
浅沟槽隔离(Shallow Trench Isolation，STI)是目前大规模集成电路中用于实现器件隔离的主要方法。例如，可利用沟槽隔离结构将相邻的有源区(Active Area，AA)相互隔离，从而可以避免形成在不同的有源区上的元器件相互干扰。此外，在半导体集成电路中，通常还会设置有大量的电性传导结构，该电性传导结构例如可用于实现电性传输，或者仅作为冗余组件(即，不实现电性功能)。通常而言，集成电路中的电性传导结构会偏离沟槽隔离结构设置，基于此，则必然需要为电性传导结构预留一定的容置空间。
随着半导体技术的不断发展，集成电路的尺寸趋于减小，即使通过缩减电性传导结构的尺寸可以实现集成电路的尺寸缩减，然而由于仍然需要为电性传导结构预留较大的空间，从而使得半导体集成电路的整体尺寸难以再进一步缩减。
发明内容
本发明的目的在于提供一种半导体结构，以利于缩减半导体集成电路的整体尺寸。
为解决上述技术问题，本发明提供一种半导体结构，包括：
沟槽隔离结构，形成在一衬底的隔离沟槽中，其中所述沟槽隔离结构包括多层绝缘层，所述多层绝缘层依次覆盖所述隔离沟槽的内壁，并且所述多层绝缘层中位于最内层的绝缘层顶表面相对于衬底顶表面更为下沉，以构成第一凹槽在所述隔离沟槽中；以及，
电性传导结构，形成在所述衬底上且至少部分位于所述沟槽隔离结构上，并且所述电性传导结构完全填充所述第一凹槽；其中，所述电性传导结构包括第一导电层和第二导电层，所述第一导电层填充所述第一凹槽并向上延伸出所述隔离沟槽，所述第二导电层形成在所述第一导电层上。
基于如上所述的半导体结构，本发明还提供了一种半导体结构的形成方法，包括：
提供一衬底，并形成隔离沟槽在所述衬底中；
依次形成多层绝缘层在所述隔离沟槽中，以构成沟槽隔离结构，并且所述多层绝缘层中位于最内层的绝缘层顶表面相对于衬底顶表面更为下沉，以构成第一凹槽在所述隔离沟槽中；以及，
形成第一导电层和第二导电层在所述衬底上，并且所述第一导电层完全填充所述第一凹槽并向上延伸出所述隔离沟槽，所述第二导电层形成在所述第一导电层上。
在本发明提供的半导体结构中，基于衬底中形成有沟槽隔离结构，进一步将至少部分电性传导结构形成在所述沟槽隔离结构上，从而可以有效利用沟槽隔离结构上方的空间，相应的可以减小为所述电性传导结构额外预留的空间，甚至可以不需要为所述电性传导结构预留空间。如此，即有利于实现所构成的半导体集成电路的尺寸缩减。
附图说明
图1为本发明一实施例中的半导体结构的示意图；
图2为本发明一实施例中的半导体结构的形成方法的流程示意图；
图3a～图3d为本发明一实施例中的半导体结构在其制备过程中的结构示意图。
其中，附图标记如下：
100-衬底；
200a-隔离沟槽；
200b-第一凹槽；
200c-第二凹槽；
200-沟槽隔离结构；
210-第一绝缘层；
220-第二绝缘层；
230-第三绝缘层；
300-电性传导结构；
300a-伪栅极结构；
300b-栅极结构；
310a/310b-第一导电层；
320a/320b-第二导电层；
330a/330b-第三导电层；
340a/340b-遮蔽层；
341-缝隙；
400-侧墙结构；
410-第一隔离层；
420-第二隔离层。
具体实施方式
以下结合附图和具体实施例对本发明提出的半导体结构及其形成方法作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
图1为本发明一实施例中的半导体结构的示意图，如图1所示，本实施例中的半导体结构包括：
沟槽隔离结构200，形成在一衬底100的隔离沟槽200a中，并且所述沟槽隔离结构200的至少部分顶表面相对于所述衬底100的顶表面更为下沉；以及，
电性传导结构300，形成在所述衬底100上，所述电性传导结构300至少部分位于所述沟槽隔离结构200的上方并填充所述隔离沟槽200a。
其中，所述电性传导结构300包括第一导电层310a和第二导电层320a，所述第一导电层310a填充所述隔离沟槽200a并延伸出所述隔离沟槽200a，所述第二导电层320a形成在所述第一导电层310a上。本实施例中，所述第一导电层310a延伸出所述隔离沟槽200a，从而使第一导电层310a的整个顶表面均高出于所述衬底100的顶表面。
需要说明的是，通过将电性传导结构300形成在沟槽隔离结构200上，因 此可以有效利用沟槽隔离结构200上方的空间，从而可以减少为电性传导结构预留的容置空间，或者可以不需要再为所述电性传导结构300额外预留容置空间，如此，即有利于缩减整个集成电路的尺寸。
此外，还需要说明的是，形成在沟槽隔离结构200上的电性传导结构300，虽然部分嵌入至所述隔离沟槽200a中，然而这并不会对电性传导结构300的性能造成较大影响。例如，当所述电性传导结构300用于实现电性传输时，虽然所述电性传导结构300部分填充在隔离沟槽200a中，然而这仍然可以使第一导电层310a和第二导电层320a的电性传输性能满足要求；或者，当所述电性传导结构300用于构成冗余组件时，例如构成伪栅极(Dummy Gate)时，此时由于所述冗余组件并不需要实现电性功能，进而也不存在功能被影响的问题。
本实施例中，所述第二导电层320a在高度方向上的投影面积不小于所述第一导电层310a的顶表面面积。即意味着，所述第一导电层310a的顶表面在所述第二导电层320a的直接覆盖或间接覆盖下未被暴露出，从而使得所述第一导电层310a相对于所述第二导电层320a仅侧壁为侧向暴露出。其中，所述第一导电层310a的材料例如包括掺杂的多晶硅(poly)，以及所述第二导电层320a可以为金属层，例如所述第二导电层320a的材料包括钨(W)。
进一步的，所述沟槽隔离结构200多层绝缘层，所述多层绝缘层依次覆盖所述隔离沟槽200a的内壁，并且所述多层绝缘层中位于最内层的绝缘层顶表面相对于衬底顶表面更为下沉，以构成第一凹槽在所述隔离沟槽200a中。
本实施例中，所述电性传导结构300的侧壁边界介于所述第一凹槽的边界和所述隔离沟槽200a的边界之间，以使所述电性传导结构300完全填充所述第一凹槽，即，所述电性传导结构300中其第一导电层310a至少部分形成在最内层的绝缘层上，以完全填充所述第一凹槽并进一步向上延伸出隔离沟槽200a。需要说明的是，此处所述的“电性传导结构的侧壁边界”例如为：电性传导结构沿着长度方向延伸的侧壁。
继续参考图1所示，本实施例中，所述沟槽隔离结构200中的多层绝缘层包括第一绝缘层210、第二绝缘层220和第三绝缘层230。所述第一绝缘层210和所述第二绝缘层220依次保形的覆盖所述隔离沟槽200a的内壁，所述第三绝缘层230位于所述多层绝缘层的最内层以填充所述隔离沟槽200a。即，所述第二绝缘层220位于所述第一绝缘层210和所述第三绝缘层230之间，以及所述 第三绝缘层230构成沟槽隔离结构200的最内层，并且第三绝缘层230的顶表面低于隔离沟槽200a的顶部，进而使第三绝缘层230相对于所述衬底100的顶表面更为下沉。
进一步的，所述第三绝缘层230的顶表面还低于所述第二绝缘层220的顶表面，以利用所述第二绝缘层220围绕出所述第一凹槽在所述第三绝缘层230的上方。
继续参考图1所示，所述电性传导结构300的侧壁边界超出所述第三绝缘层230的侧壁边界，并搭接在所述第二绝缘层220上。可以理解为，所述电性传导结构300在预定方向上的宽度尺寸大于由所述第二绝缘层围绕出的第一凹槽的开口尺寸，并小于所述沟槽隔离结构200的宽度尺寸。
本实施例中，所述电性传导结构300中的第一导电层310a填充由所述第二绝缘层220围绕出的第一凹槽，以覆盖所述第三绝缘层230和所述第二绝缘层220靠近所述第三绝缘层的侧壁，并进一步延伸出所述第一凹槽，以使所述第一导电层310a的侧壁边界搭接在所述第二绝缘层220的顶部上，相应的使所述第一导电层310a具有延伸出所述第一凹槽的侧壁。
可选的方案中，还可以使所述第一绝缘层210的顶表面也相对于所述第二绝缘层220和衬底100均更为下沉，从而可以由所述第二绝缘层220的侧壁、隔离沟槽200a的侧壁和第一绝缘层210的顶表面围绕出一微型的第二凹槽，所述第二凹槽即相应的位于所述第二绝缘层220和所述隔离沟槽的侧壁之间。
基于此，例如可使所述第一绝缘层210和所述第三绝缘层230包括相同的材料，所述第二绝缘层220可以具有不同于所述第三绝缘层230的材料，如此一来，当利用回刻蚀工艺形成所述沟槽隔离结构200时，即可使所述第一绝缘层210和所述第三绝缘层230的顶表面均相对于所述衬底100的顶表面下沉。以及，由于所述第二绝缘层220可以具有不同于所述第三绝缘层230的材料，从而通过回刻蚀工艺，还可以使第一绝缘层210和第三绝缘层230均低于所述第二绝缘层220的顶表面。
具体的，所述第一绝缘层210和所述第三绝缘层230的材料例如均包括氧化硅(SiO)，所述第二绝缘层220的材料例如包括氮化硅(SiN)，以使所述沟槽隔离结构200呈现为ONO结构，以提高所述沟槽隔离结构200的隔离性能。
接着参考图1所示，所述半导体结构还包括侧墙结构400，所述侧墙结构 400至少覆盖所述电性传导结构300的侧壁，以使所述侧墙结构400至少覆盖所述第一导电层310a中延伸出所述隔离沟槽200a的侧壁以及所述第二导电层320a的侧壁。
本实施例中，所述电性传导结构300在预定方向上的宽度尺寸大于所述第三绝缘层230的宽度尺寸，并小于所述沟槽隔离结构200的宽度尺寸，从而使所述电性传导结构300未覆盖位于第二绝缘层和隔离沟槽侧壁之间的第二凹槽。基于此，可进一步使所述侧墙结构400延伸覆盖所述第二绝缘层220和所述第一绝缘层210，以使所述侧墙结构400还嵌入至所述第二凹槽中。即，还利用所述侧墙结构400填充所述第二凹槽，从而可以补偿所述隔离沟槽200a其边缘部分的空隙。
其中，所述侧墙结构400可以为单层结构，也可以为叠层结构。本实施例中，所述侧墙结构400包括第一隔离层410和第二隔离层420，所述第一隔离层410和所述第二隔离层420依次覆盖所述电性传导结构300的侧壁，并顺应所述第二绝缘层220进一步填充所述第二凹槽。具体的，所述第一隔离层410和所述第二隔离层420可以分别具有不同的材料，例如所述第一隔离层410的材料包括氧化硅，所述第二隔离层420的材料包括氮化硅。
当然，在其他实施例中，所述侧墙结构还可以包括三层隔离层，所述三层隔离层依次覆盖所述电性传导结构的侧壁。以及，所述侧墙结构中的三层隔离层的材料例如分别为氧化硅、氮化硅和氧化硅，如此以构成ONO结构的隔离结构。
可以理解为，所述沟槽隔离结构200在所述隔离沟槽200a中进一步界定出第一凹槽，所述第一导电层310a填充所述隔离沟槽200a中的第一凹槽，并且所述第一导电层310a的侧壁边界还搭接在所述第一凹槽的侧壁顶部上。以及，所述沟槽隔离结构200在所述隔离沟槽200a中还界定有第二凹槽，所述第二凹槽位于所述第一凹槽的侧边，并可使所述侧墙结构400填充所述第二凹槽，以补偿所述隔离沟槽200a其边缘区域的空隙。
具体参考图1所示，结合如上所述，所述第一导电层310a的侧壁边界还搭接在所述第一凹槽的侧壁顶部上，因此可使所述第一导电层310a中对应所述隔离沟槽200a的顶表面上形成有第一凹陷(更具体为，所述第一导电层310a中对应所述第一凹槽的顶表面上形成有第一凹陷)，并且所述第一凹陷的底部高出于 所述隔离沟槽200a的顶部。以及，所述第二导电层320a位于第一导电层310a的上方，相应的可使所述第二导电层320a中对应所述隔离沟槽200a的底表面以朝向所述第一导电层310a的方向凸出，所述第二导电层320a中对应所述隔离沟槽200a的顶表面以朝向所述第一导电层310a的方向下凹，以构成第二凹陷。
即，本实施例中，所述第一导电层310a上的第一凹陷和所述第二导电层320a上的第二凹陷位置对应，更具体为，所述第一导电层310a上的第一凹陷的底部和所述第二导电层320a上的第二凹陷的底部对齐在同一竖直线上。
继续参考图1所示，所述电性传导结构300还包括第三导电层330a，所述第三导电层330a形成在所述第一导电层310a和所述第二导电层320a之间。其中，所述第三导电层330a的材料例如包括氮化钛。
本实施例中，所述第三导电层330a为保形的覆盖所述第一导电层310a的顶表面，从而使第三导电层330a对应于第一导电层310a的第一凹陷而呈现为弯折状结构。即，所述第三导电层330a中对应于第一凹陷的底部凸出至所述第一凹陷中，进而使所述第三导电层330a中对应第一凹陷的顶表面以朝向所述第一导电层310a的方向下凹，以构成第三凹陷。以及，所述第二导电层320a中靠近第三导电层的部分即凸出至所述第三凹陷中。
继续参考图1所示，所述电性传导结构300还包括遮蔽层340a，所述遮蔽层340a形成在所述第二导电层320a上，以及所述遮蔽层340a的顶表面相对于所述第二导电层320a的顶表面更为平坦。具体的，例如可以通过平坦化工艺，以使所述遮蔽层340a具有平坦的顶表面。
此外，本实施例中，所述遮蔽层340a对应于所述第二凹陷处的底表面与所述第二凹陷还围绕出一缝隙341。具体而言，所述第二导电层320a的顶表面具有第二凹陷，从而可以在第二凹陷的上方形成有所述缝隙341。
接着参考图1所示，本实施例的半导体结构包括至少两个沟槽隔离结构200，并可利用相邻的沟槽隔离结构200界定出有源区(Active Area，AA)，以及在所述有源区中还可设置有半导体器件。本实施例中，在所述有源区上也形成有电性传导结构，以及位于有源区中的电性传导结构也可以包括依次堆叠设置的第一导电层、第三导电层、第二导电层和遮蔽层。
具体的，所述半导体器件中的电性传导结构例如用于构成栅极结构300b。 即，所述栅极结构300b可以包括第一导电层310b和第二导电层320b，还可以进一步包括第三导电层330b和遮蔽层340b。
进一步的，位于有源区中的栅极结构300b和位于隔离区(对应于沟槽隔离结构的区域)中的电性传导结构300，所构成的半导体集成电路例如为存储器的外围电路。其中，位于有源区中的栅极结构300b例如可进一步构成外围电路中的开关晶体管。以及，位于隔离区中的电性传导结构300例如用于实现电性传输，或者用于构成伪栅极结构。
如上所述，当隔离区中的电性传导结构300用于实现电性传输时，即使所述电性传导结构300其底部延伸至隔离沟槽200a中，仍然可以保障电性传导结构300中第一导电层310a和第二导电层320a的电性传输性能。此外，本实施例中，还使隔离区中的电性传导结构300的宽度尺寸小于隔离沟槽200a的宽度尺寸，从而可以避免隔离区中的电性传导结构300延伸至有源区中，防止对有源区中的半导体器件造成干扰。
下面以隔离区中的电性传导结构300用于构成伪栅极结构300a为例，进一步解释说明。
如图1所示，所述栅极结构300b形成在衬底100的顶表面上，以及所述栅极结构300b中第一导电层310b的顶表面相对于所述伪栅极结构300a中第一导电层310a的顶表面更为平坦。相应的，所述栅极结构300b中第三导电层330b和第二导电层320b的顶表面均相对于所述伪栅极结构300a中第三导电层330a和第二导电层320a的顶表面更为平坦。
以及，在所述栅极结构300b中，其遮蔽层340b的底表面和第二导电层320b的顶表面之间闭合接触，因此栅极结构300b的遮蔽层340b中并没有形成有缝隙。
此外，所述栅极结构300b中第一导电层310b的顶表面还高于所述伪栅极结构300a中第一导电层310a的顶表面。对应的，所述栅极结构300b中的第三导电层330b也高于所述伪栅极结构300a中的第三导电层330a；以及，所述栅极结构300b中的第二导电层320b也高于所述伪栅极结构300a中的第二导电层320a。然而需要说明的是，本实施例中，所述栅极结构300b中遮蔽层340b的顶表面可以和所述伪栅极结构300a中遮蔽层340a的顶表面齐平，即，位于沟槽隔离结构上的遮蔽层和位于有源区上的遮蔽层的顶表面为共平面设置。
基于如上所述的半导体结构，本实施例中还提供了一种半导体结构的形成方法。图2为本发明一实施例中的半导体结构的形成方法的流程示意图，如图2所示，本实施例中的半导体结构的形成方法包括：
步骤S100，提供一衬底，并形成隔离沟槽在所述衬底中；
步骤S200，形成沟槽隔离结构在所述隔离沟槽中，并且所述沟槽隔离结构的至少部分顶表面相对于所述衬底的顶表面更为下沉；
步骤S300，形成第一导电层和第二导电层在所述衬底上，所述第一导电层填充所述隔离沟槽并延伸出所述隔离沟槽，所述第二导电层形成在所述第一导电层上。
图3a～图3d为本发明一实施例中的半导体结构在其制备过程中的结构示意图，以下结合附图，对本实施例中形成所述半导体结构的各个步骤进行详细说明。
在步骤S100中，具体参考图3a所示，提供一衬底100，并形成隔离沟槽200a在所述衬底100中。
其中，所述隔离沟槽200a的形成方法例如包括：首先，形成掩膜层(图中未示出)在所述衬底100上，以利用所述掩膜层界定出所述隔离沟槽的图形；接着，以所述掩膜层为掩膜刻蚀所述衬底100，以形成所述隔离沟槽200a。
具体参考图3a所示，本实施例中，所述隔离沟槽200a的开口尺寸可以从沟槽顶部至沟槽底部逐渐减小，以使所述隔离沟槽200a具有倾斜侧壁。通过形成具有倾斜侧壁的隔离沟槽200a，从而在后续填充绝缘材料于所述隔离沟槽200a中时，即可有效提高绝缘材料的填充性能，避免填充于隔离沟槽200a的绝缘材料层中产生有空洞的问题。
在步骤S200中，具体参考图3b所示，形成沟槽隔离结构200在所述隔离沟槽200a中，并且所述沟槽隔离结构200的至少部分顶表面相对于所述衬底100的顶表面更为下沉。
需要说明的是，在传统工艺中，常常是利用平坦化工艺制备沟槽隔离结构，以使所形成的沟槽隔离结构的顶表面与衬底的顶表面齐平，甚至使沟槽隔离结构还凸出于所述衬底的顶表面(即，沟槽隔离结构的顶表面高于衬底的顶表面)。
而本实施例中，基于刻蚀工艺形成多层绝缘层在所述隔离沟槽200a中，构成沟槽隔离结构200，以至少降低沟槽隔离结构200中的最内层的绝缘层的高度，从而实现所形成的沟槽隔离结构200能够相对于所述衬底100的顶表面凹陷。
具体的，所述沟槽隔离结构200的形成方法例如包括如下步骤。
步骤一，依次形成第一绝缘材料层和第二绝缘材料层在所述衬底100上，所述第一绝缘材料层和所述第二绝缘材料层依次保形的覆盖所述隔离沟槽200a的内壁(包括底壁和侧壁)，还覆盖所述衬底100的顶表面。
本实施例中，所述第一绝缘材料层例如包括氧化硅层，所述第二绝缘材料层例如包括氮化硅层。其中，所述氧化硅层可以采用氧化工艺形成，所述氮化硅层可以采用化学气相沉积工艺形成。
步骤二，沉积第三绝缘材料层在所述衬底100上，所述第三绝缘材料层覆盖所述第二绝缘材料层并填充所述隔离沟槽200a。其中，所述第三绝缘材料层的材料例如包括氧化硅。
步骤三，执行刻蚀工艺，刻蚀所述第三绝缘材料层、所述第二绝缘材料层和所述第一绝缘材料层，以去除所述第三绝缘材料层、所述第二绝缘材料层和所述第一绝缘材料层中位于衬底顶表面上的部分，并使剩余的第三绝缘材料层、第二绝缘材料层和第一绝缘材料层填充在所述隔离沟槽中，以分别构成第三绝缘层230、第二绝缘层220和第一绝缘层210，其中所述第三绝缘层230的顶表面低于所述衬底100的顶表面。
具体而言，所述第三绝缘材料层覆盖在顶层，因此在所述刻蚀工艺中，刻蚀剂优先刻蚀第三绝缘材料层，以去除所述第三绝缘材料层中位于衬底顶表面上的部分，进而暴露出第二绝缘材料层；接着，继续去除衬底顶表面上的第二绝缘材料层，以使保留于隔离沟槽200a中的第二绝缘材料层构成第二绝缘层220；接着，即可继续刻蚀暴露出的第一绝缘材料层，以形成第一绝缘层210。
进一步的，在刻蚀所述第一绝缘材料层和/或第二绝缘材料层时，刻蚀剂还刻蚀位于所述隔离沟槽中的第三绝缘材料层，从而可使保留于所述隔离沟槽200a中的第三绝缘材料层相对于所述衬底100的顶表面更为下沉。
本实施例中，可以在刻蚀所述第一绝缘材料层时，利用刻蚀剂还刻蚀位于所述隔离沟槽中的第三绝缘材料层，进而使保留于所述隔离沟槽200a中的第三绝缘材料层和第一绝缘材料层均相对于所述衬底100的顶表面更为下沉，并分 别构成第三绝缘层230和第一绝缘层210。
即，本实施例中，所述第一绝缘层210和第三绝缘层230的顶表面均低于所述第二绝缘层220的顶表面。如此一来，即能够由所述第二绝缘层220围绕出第一凹槽200b在所述隔离沟槽200a中；以及，还可以利用第二绝缘层220和隔离沟槽200a的侧壁围绕出第二凹槽200c。
此外，需要说明的是，所述衬底100上例如形成有至少两个沟槽隔离结构200，并可利用相邻的所述沟槽隔离结构200进一步界定出半导体器件的有源区(Active Area，AA)。后续工艺中，即可在所述有源区中制备相应的半导体器件。
在步骤S300中，具体参考图3c所示，形成第一导电层310a和第二导电层320a在所述衬底100上，其中所述第一导电层310a的侧壁边界介于所述第一凹槽200b的边界和所述隔离沟槽200a的边界之间，以填充所述第一凹槽200b，并且所述第一导电层310a的顶部还向上延伸出所述隔离沟槽200a，所述第二导电层320a形成在所述第一导电层310a上。其中，所述第一导电层310a和所述第二导电层320a即可用于构成电性传导结构300。
进一步的，还可使所述第二导电层320a在高度方向上的投影面积不小于所述第一导电层310a的顶表面面积。本实施例中，所述第二导电层320a的侧壁边界和所述第一导电层310a的侧壁边界重合。
本实施例中，所述电性传导结构具有形成在所述沟槽隔离结构200上的部分，并可进一步构成伪栅极结构300a。
可选的方案中，在沟槽隔离结构200上制备电性传导结构(伪栅极结构300a)时，还可以同时在所述有源区上也制备电性传导结构，以构成栅极结构300b在所述有源区中。具体的，同时形成所述伪栅极结构300a和所述栅极结构300b的方法例如包括如下步骤。
第一步骤，沉积第一导电材料层在所述衬底100上。本实施例中，所述第一导电材料层覆盖有源区的衬底，以及覆盖所述沟槽隔离结构200并填充所述第一凹槽200b。
其中，所述第一导电材料层中对应所述第一凹槽200b的顶表面形成有第一凹陷，所述第一凹陷的底部高出于所述隔离沟槽200a的顶部。即，对应有源区的第一导电材料层的顶表面相对于对应隔离区的第一导电材料层的顶表面更为 平坦。
第二步骤，沉积第二导电材料层在所述第一导电材料层上。
同样的，所述第二导电材料层覆盖有源区和隔离区(即，沟槽隔离结构)，以及所述第二导电材料层中对应所述第一凹陷的底表面相应的以朝向所述第一导电材料层的方向凸出，所述第二导电材料层中对应所述第一凹陷的顶表面即以朝向所述第一导电材料层的方向下凹，以构成第二凹陷。
进一步的，在沉积所述第二导电材料层之前，还包括：沉积第三导电材料层在所述第一导电材料层上。以及所述第二导电材料层即形成在所述第三导电材料层上。
更进一步的，在沉积所述第二导电材料层之后，还包括：形成遮蔽材料层在所述第二导电材料层上。具体的，所述遮蔽材料层可利用平坦化工艺形成，以使所述遮蔽材料层的顶表面相对于所述第二导电材料层的顶表面更为平坦，即，所述遮蔽材料层中位于隔离区的顶表面和位于有源区的顶表面齐平。
此外，本实施例中，位于隔离区的第二导电材料层上具有第二凹陷，基于此，则在沉积所述遮蔽材料层时，可使所述遮蔽材料层中对应第二凹陷的部分中形成有缝隙。
第三步骤，图形化所述第二导电材料层和所述第一导电材料层，以形成堆叠设置所述第二导电层和所述第一导电层。具体的，对所述第二导电材料层和所述第一导电材料层的图形化方法例如包括：
首先，形成图形化的掩膜层在所述第二导电材料层上；本实施例中，所述掩膜层形成在所述遮蔽材料层上，以及所述掩膜层的图形包括对应于隔离区的伪栅极图形和对应于有源区的栅极图形；
接着，以所述掩膜层为掩膜，依次刻蚀所述第二导电材料层和第一导电材料层，以分别形成所述第二导电层和第一导电层。本实施例中，还以所述掩膜层为掩膜刻蚀遮蔽材料层和第三导电材料层，以分别形成遮蔽层和第三导电层。如上所述，所述遮蔽材料层中位于隔离区的顶表面和位于有源区的顶表面齐平，基于此，则分别在隔离区和有源区上形成遮蔽层后，位于隔离区上的遮蔽层和位于有源区上的遮蔽层的顶表面相应的为共平面。
重点参考图3c所示，在所述隔离区(对应沟槽隔离结构的区域)和所述有源区中均形成有所述第一导电层、第三导电层、第二导电层和遮蔽层。其中， 位于所述隔离区中第一导电层310a、第三导电层330a、第二导电层320a和遮蔽层340a用于构成伪栅极结构300a；以及，位于有源区中的第一导电层310b、第三导电层330b、第二导电层320b和遮蔽层340b用于构成栅极结构300b。
本实施例中，所述伪栅极结构300a填充隔离沟槽200a的第一凹槽200b，并且伪栅极结构300a的侧壁边界搭接在所述第二绝缘层220上，即，所述伪栅极结构300a未填充所述隔离沟槽200a中第二凹槽200c。
在进一步的方案中，所述半导体结构的形成方法还包括：步骤S400，形成侧墙结构。
具体参考图3d所示，所述侧墙结构400至少覆盖所述第一导电层310a中延伸出所述隔离沟槽的侧壁以及所述第二导电层320a的侧壁。以及，所述侧墙结构400还进一步延伸至所述第二凹槽中，以填充所述第二凹槽。
如图3d所示，本实施例中，在所述伪栅极结构300a的侧壁上形成有侧墙结构400，以及所述栅极结构300b的侧壁上也形成有侧墙结构，以覆盖栅极结构300b中第一导电层310b、第三导电层330b和第二导电层320b的侧壁。
至此，即实现了利用同一工艺步骤，可以同时在有源区中形成栅极结构300b以及在隔离区中形成伪栅极结构300a，以及同时在栅极结构300b和伪栅极结构300a的侧壁上均形成侧墙结构400，有利于简化工艺。
综上所述，在本实施例的半导体结构中，通过将至少部分电性传导结构设置在沟槽隔离结构的上方，从而可以充分利用沟槽隔离结构上方的空间，相当于减少了电性传导结构在整个半导体集成电路中所占用的空间，进而有利于实现所构成的半导体集成电路的尺寸缩减。
可选的方案中，用于构成伪栅极结构的电性传导结构的宽度尺寸小于隔离沟槽的开口尺寸，以防止伪栅极结构对有源区中的半导体器件造成干扰(例如，对有源区中的栅极结构造成影响)。
进一步的方案中，即使沟槽隔离结构由多层绝缘材料层构成，仍采用同一刻蚀工艺依次刻蚀多层绝缘材料层，此时基于不同绝缘材料的刻蚀速率的差异，使得所得到的多层绝缘层之间的高度存在差异(例如，本实施例中第一绝缘层和第二绝缘层之间存在高度差异)。以及，由于隔离区中的电性传导结构在预定 方向(例如，电性传导结构的宽度方向)上未延伸至隔离沟槽的边缘，从而使得隔离沟槽中由第二绝缘层和隔离沟槽侧壁围绕出的第二凹槽未被电性传导结构填充。基于此，则可使侧墙结构在覆盖电性传导结构侧壁的基础上，进一步填充所述第二凹槽，以补偿隔离沟槽边缘的空隙，保障沟槽隔离结构的隔离性能。
需要说明的是，在传统的利用平坦化工艺形成沟槽隔离结构时，当沟槽隔离结构包括多层绝缘材料层时，则需要针对不同的绝缘材料层的具体材质分别执行平坦化工艺，其操作步骤较为繁琐。可见，与传统工艺相比，本实施例中在制备沟槽隔离结构时，能够在确保沟槽隔离结构的隔离性能的基础上，简化工艺。
需要说明的是，上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定。对于任何熟悉本领域的技术人员而言，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。
还需要说明的是，除非特别说明或者指出，否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等，而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。以及，词语“或”应该被理解为具有逻辑“或”的定义，而不是逻辑“异或”的定义，除非上下文明确表示相反意思。

Claims (19)

  1. 一种半导体结构，其特征在于，包括：
    沟槽隔离结构，形成在一衬底的隔离沟槽中，其中所述沟槽隔离结构包括多层绝缘层，所述多层绝缘层依次覆盖所述隔离沟槽的内壁，并且所述多层绝缘层中位于最内层的绝缘层顶表面相对于衬底顶表面更为下沉，以构成第一凹槽在所述隔离沟槽中；以及，
    电性传导结构，形成在所述衬底上且至少部分位于所述沟槽隔离结构上，并且所述电性传导结构完全填充所述第一凹槽；其中，所述电性传导结构包括第一导电层和第二导电层，所述第一导电层填充所述第一凹槽并向上延伸出所述隔离沟槽，所述第二导电层形成在所述第一导电层上。
  2. 如权利要求1所述的半导体结构，其特征在于，所述电性传导结构的侧壁边界介于所述第一凹槽的边界和所述隔离沟槽的边界之间。
  3. 如权利要求1所述的半导体结构，其特征在于，所述多层绝缘层包括第一绝缘层、第二绝缘层和第三绝缘层，所述第一绝缘层和所述第二绝缘层依次保形的覆盖所述隔离沟槽的内壁，所述第三绝缘层位于所述多层绝缘层的最内层以填充所述隔离沟槽。
  4. 如权利要求3所述的半导体结构，其特征在于，所述第三绝缘层的顶表面低于所述第二绝缘层的顶表面，以利用所述第二绝缘层围绕出所述第一凹槽在所述第三绝缘层的上方。
  5. 如权利要求3所述的半导体结构，其特征在于，所述电性传导结构的侧壁边界超出所述第三绝缘层的侧壁边界，并搭接在所述第二绝缘层上。
  6. 如权利要求1所述的半导体结构，其特征在于，所述第二导电层在高度方向上的投影面积不小于所述第一导电层的顶表面面积。
  7. 如权利要求1所述的半导体结构，其特征在于，所述第一导电层中对应所述第一凹槽的顶表面上形成有第一凹陷，所述第一凹陷的底部高于所述第一凹槽的顶部。
  8. 如权利要求7所述的半导体结构，其特征在于，所述电性传导结构还包括第三导电层，所述第三导电层形成在所述第一导电层和所述第二导电层之间；以及，所述第三导电层中对应于所述第一凹陷的底部凸出至所述第一凹陷 中，所述第三导电层中对应第一凹陷的顶表面以朝向所述第一导电层的方向下凹。
  9. 如权利要求1所述的半导体结构，其特征在于，所述第二导电层中对应所述第一凹槽的底表面以朝向所述第一导电层的方向凸出，所述第二导电层中对应所述第一凹槽的顶表面以朝向所述第一导电层的方向下凹，以构成第二凹陷。
  10. 如权利要求9所述的半导体结构，其特征在于，所述电性传导结构还包括遮蔽层，所述遮蔽层形成在所述第二导电层上，并且所述遮蔽层对应于所述第二凹陷处的底表面与所述第二凹陷围绕出一缝隙。
  11. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构中，利用所述沟槽隔离结构界定出有源区，并且在所述有源区上也形成有电性传导结构；
    其中，位于沟槽隔离结构上的电性传导结构和位于有源区上的电性传导结构均包括遮蔽层，所述遮蔽层形成在所述电性传导结构的导电层上，并且位于沟槽隔离结构上的遮蔽层和位于有源区上的遮蔽层的顶表面为共平面。
  12. 一种半导体结构，其特征在于，包括：
    沟槽隔离结构，形成在一衬底的隔离沟槽中，并且所述沟槽隔离结构的至少部分顶表面相对于所述衬底的顶表面更为下沉；
    电性传导结构，形成在所述衬底的所述沟槽隔离结构上，并填充所述隔离沟槽，其中所述电性传导结构包括第一导电层和第二导电层，所述第一导电层填充所述隔离沟槽并延伸出所述隔离沟槽，所述第二导电层形成在所述第一导电层上，并且所述第一导电层和所述第二导电层中对应所述隔离沟槽的顶表面上均形成有凹陷；以及，
    遮蔽层，形成在所述电性传导结构的所述第二导电层上，并且所述遮蔽层中对应于所述第二导电层的凹陷处与所述第二导电层的凹陷围绕出一缝隙。
  13. 一种半导体结构的形成方法，其特征在于，包括：
    提供一衬底，并形成隔离沟槽在所述衬底中；
    形成多层绝缘层在所述隔离沟槽中，以构成沟槽隔离结构，并且所述多层绝缘层中位于最内层的绝缘层顶表面相对于衬底顶表面更为下沉，以构成第一凹槽在所述隔离沟槽中；以及，
    形成第一导电层和第二导电层在所述衬底上，以构成电性传导结构，其中所述第一导电层完全填充所述第一凹槽并向上延伸出所述隔离沟槽，所述第二导电层形成在所述第一导电层上。
  14. 如权利要求13所述的半导体结构的形成方法，其特征在于，所述第一导电层的侧壁边界介于所述第一凹槽的边界和所述隔离沟槽的边界之间。
  15. 如权利要求13所述的半导体结构的形成方法，其特征在于，形成所述沟槽隔离结构的方法包括：
    依次形成第一绝缘材料层和第二绝缘材料层在所述衬底上，所述第一绝缘材料层和所述第二绝缘材料层依次覆盖所述隔离沟槽的内壁，还覆盖所述衬底的顶表面；
    沉积第三绝缘材料层在所述衬底上，所述第三绝缘材料层覆盖所述第二绝缘材料层并填充所述隔离沟槽；以及，
    执行刻蚀工艺，刻蚀所述第三绝缘材料层、所述第二绝缘材料层和所述第一绝缘材料层，以去除所述第三绝缘材料层、所述第二绝缘材料层和所述第一绝缘材料层中位于衬底顶表面上的部分，并使剩余的第三绝缘材料层、第二绝缘材料层和第一绝缘材料层填充在所述隔离沟槽中，以分别构成第三绝缘层、第二绝缘层和第一绝缘层。
  16. 如权利要求15所述的半导体结构的形成方法，其特征在于，所述刻蚀工艺中，在刻蚀所述第二绝缘材料层和/或第一绝缘材料层时，刻蚀剂还刻蚀位于所述隔离沟槽中的第三绝缘材料层，以使所形成的第三绝缘层的顶表面低于所述第二绝缘层的顶表面，并利用所述第二绝缘层围绕出所述第一凹槽在所述第三绝缘层的上方。
  17. 如权利要求15所述的半导体结构的形成方法，其特征在于，所述刻蚀工艺中，在去除衬底顶表面上的第二绝缘材料层之后，并刻蚀第一绝缘材料层时，刻蚀剂还刻蚀位于所述隔离沟槽中的第三绝缘材料层，以使保留于所述隔离沟槽中的第一绝缘层和第三绝缘层均相对于所述第二绝缘层的顶表面更为下沉，并利用所述第二绝缘层和所述隔离沟槽的侧壁围绕出第二凹槽。
  18. 如权利要求13所述的半导体结构的形成方法，其特征在于，形成所述第一导电层和所述第二导电层的方法包括：
    沉积第一导电材料层在所述衬底上，所述第一导电材料层覆盖所述沟槽隔 离结构并填充所述第一凹槽，并且所述第一导电材料层中对应所述第一凹槽的顶表面形成有第一凹陷，所述第一凹陷的底部高于所述第一凹槽的顶部；
    沉积第二导电材料层在所述第一导电材料层上，所述第二导电材料层中对应所述第一凹陷的底部凸出至所述第一凹陷中，所述第二导电材料层中对应所述第一凹陷的顶表面以朝向所述第一导电材料层的方向下凹，以构成第二凹陷；以及，
    图形化所述第二导电材料层和所述第一导电材料层，形成堆叠设置的所述第二导电层和所述第一导电层。
  19. 如权利要求13所述的半导体结构的形成方法，其特征在于，所述半导体结构中，利用所述沟槽隔离结构界定出有源区，以及在沟槽隔离结构上制备电性传导结构时，还在所述有源区上也制备电性传导结构；
    其中，在形成电性传导结构的导电层之后，还包括：
    利用平坦化工艺，形成遮蔽层在电性传导结构的导电层上，并且位于沟槽隔离结构上的遮蔽层和位于有源区上的遮蔽层的顶表面为共平面。
PCT/CN2019/124588 2019-07-02 2019-12-11 半导体结构及其形成方法 WO2020125515A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US16/635,208 US11145715B2 (en) 2019-07-02 2019-12-11 Semiconductor structure and method of forming same
US17/465,803 US11688764B2 (en) 2019-07-02 2021-09-02 Semiconductor structure and method of forming same
US18/140,595 US20230261046A1 (en) 2019-07-02 2023-04-27 Method of forming semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910591043.4 2019-07-02
CN201910591043.4A CN111640703A (zh) 2019-07-02 2019-07-02 半导体结构及其形成方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/635,208 A-371-Of-International US11145715B2 (en) 2019-07-02 2019-12-11 Semiconductor structure and method of forming same
US17/465,803 Division US11688764B2 (en) 2019-07-02 2021-09-02 Semiconductor structure and method of forming same

Publications (1)

Publication Number Publication Date
WO2020125515A1 true WO2020125515A1 (zh) 2020-06-25

Family

ID=71102029

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/124588 WO2020125515A1 (zh) 2019-07-02 2019-12-11 半导体结构及其形成方法

Country Status (3)

Country Link
US (3) US11145715B2 (zh)
CN (1) CN111640703A (zh)
WO (1) WO2020125515A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113178483B (zh) * 2021-04-27 2022-09-02 福建省晋华集成电路有限公司 一种半导体结构以及半导体结构制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002237518A (ja) * 2001-02-08 2002-08-23 Sony Corp 半導体装置及びその製造方法
US20040072408A1 (en) * 2002-10-10 2004-04-15 Yun Jae-Sun Methods of forming trench isolated integrated circuit devices including grooves, and trench isolated integrated circuit devices so formed
CN101009243A (zh) * 2006-01-23 2007-08-01 海力士半导体有限公司 用于制造半导体器件的方法
CN101582429A (zh) * 2008-05-13 2009-11-18 海力士半导体有限公司 快闪存储器件及其制造方法
CN107134486A (zh) * 2017-04-28 2017-09-05 睿力集成电路有限公司 存储器
CN210110741U (zh) * 2019-07-02 2020-02-21 福建省晋华集成电路有限公司 半导体结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4377676B2 (ja) * 2003-12-24 2009-12-02 株式会社東芝 半導体装置およびその製造方法
US7205639B2 (en) * 2005-03-09 2007-04-17 Infineon Technologies Ag Semiconductor devices with rotated substrates and methods of manufacture thereof
JP5583315B2 (ja) * 2007-07-19 2014-09-03 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
CN104752344A (zh) * 2015-04-27 2015-07-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002237518A (ja) * 2001-02-08 2002-08-23 Sony Corp 半導体装置及びその製造方法
US20040072408A1 (en) * 2002-10-10 2004-04-15 Yun Jae-Sun Methods of forming trench isolated integrated circuit devices including grooves, and trench isolated integrated circuit devices so formed
CN101009243A (zh) * 2006-01-23 2007-08-01 海力士半导体有限公司 用于制造半导体器件的方法
CN101582429A (zh) * 2008-05-13 2009-11-18 海力士半导体有限公司 快闪存储器件及其制造方法
CN107134486A (zh) * 2017-04-28 2017-09-05 睿力集成电路有限公司 存储器
CN210110741U (zh) * 2019-07-02 2020-02-21 福建省晋华集成电路有限公司 半导体结构

Also Published As

Publication number Publication date
US20210399092A1 (en) 2021-12-23
US20230261046A1 (en) 2023-08-17
US11145715B2 (en) 2021-10-12
US11688764B2 (en) 2023-06-27
US20210020742A1 (en) 2021-01-21
CN111640703A (zh) 2020-09-08

Similar Documents

Publication Publication Date Title
KR100630666B1 (ko) 금속 콘택 및 커패시터를 포함하는 반도체 소자 제조방법
KR102076060B1 (ko) 커패시터를 포함하는 반도체 소자 및 이의 제조 방법
KR101116359B1 (ko) 매립게이트를 구비한 반도체장치 및 그 제조 방법
KR101215952B1 (ko) 반도체 장치 및 그 제조 방법
US9230858B2 (en) Semiconductor device and method for manufacturing the same
KR20110011426A (ko) 반도체 소자의 형성 방법
KR20090041167A (ko) 반도체 장치 및 그 제조방법
US7052952B2 (en) Method for forming wire line by damascene process using hard mask formed from contacts
KR20120035398A (ko) 반도체 소자의 형성 방법
US10930654B2 (en) Semiconductor devices
US6221714B1 (en) Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole
KR100594279B1 (ko) 반도체메모리소자의 자기정렬컨택 형성방법 및 이를이용한 반도체메모리소자의 제조방법
KR20180042591A (ko) 반도체 소자의 제조 방법
WO2020125515A1 (zh) 半导体结构及其形成方法
TWI733440B (zh) 動態隨機存取記憶體及其製造方法
US20230154993A1 (en) Semiconductor structure and method for fabricating same
US8445957B2 (en) Semiconductor device and method of manufacturing the same
KR20040012367A (ko) 누설전류를 방지할 수 있는 반도체 장치의 비트라인구조및 그의 형성방법
US11665889B2 (en) Semiconductor memory structure
CN210110741U (zh) 半导体结构
CN212085009U (zh) 栅极结构
CN211929495U (zh) 栅极结构
KR20040006556A (ko) 다마신 게이트 및 에피택셜공정을 이용한 반도체메모리장치 및 그의 제조방법
WO2021022811A1 (zh) 半导体结构及其形成方法
WO2024098569A1 (zh) 半导体结构及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19898582

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19898582

Country of ref document: EP

Kind code of ref document: A1