CN101009243A - 用于制造半导体器件的方法 - Google Patents

用于制造半导体器件的方法 Download PDF

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CN101009243A
CN101009243A CNA2006100770505A CN200610077050A CN101009243A CN 101009243 A CN101009243 A CN 101009243A CN A2006100770505 A CNA2006100770505 A CN A2006100770505A CN 200610077050 A CN200610077050 A CN 200610077050A CN 101009243 A CN101009243 A CN 101009243A
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李殷星
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Abstract

根据本发明的一实施例的一种用于制造半导体器件的方法提供形成在器件隔离结构上的沟道区域以形成包括SOI(绝缘体上硅)沟道结构的半导体器件，藉此减少沟道区域的离子注入浓度并且改善该器件的tWR(写入恢复时间)及LTRAS(行地址选通的长时间)的特性。

Description

用于制造半导体器件的方法
技术领域
本发明涉及一种用于制造存储器件的方法。具体而言，本发明涉及一种用于制造半导体器件的方法，其中外延层形成于凹形栅极区域的器件隔离结构之上，以形成包括SOI(绝缘体上硅)沟道结构的半导体器件，藉此减少沟道区域的离子注入浓度并且改善该器件的tWR(写入恢复时间)及LTRAS(行地址选通的长时间)的特性。
背景技术
图1是一种常规的半导体器件的简化的布局，其中附图标记1、3及5分别代表有源区域、凹形栅极区域以及栅极区域。
图2a至2f是描绘一种用于制造半导体器件的方法的简化的剖面图，其中该些剖面图是沿着图1的线I-I′所取得的。
请参照图2a，器件隔离结构20形成于半导体衬底10上，该半导体衬底10具有垫(pad)氧化膜13以及垫氮化膜15。
请参照图2b，移除该垫氮化膜15。接着在整个表面上进行离子注入工艺，以在半导体衬底10中形成阱以及离子注入区域(未显示)。接着，平坦化多晶硅层25被形成在该所得结构的整个表面上。
请参照图2c，利用凹形栅极掩模(未显示)作为蚀刻掩模蚀刻该多晶硅层25以及垫氧化膜13，以形成多晶硅层图案25a以及垫氧化膜图案13a以界定在图1中所示的凹形栅极区域3。
请参照图2d，图1中所示的凹形栅极区域3的半导体衬底10被蚀刻以形成凹槽(recess)35。该多晶硅层图案25a在用于形成该凹槽35的工艺期间被移除。
请参照图2e，该垫氧化膜图案13a被移除以露出该半导体衬底10。栅极绝缘膜60接着形成于该露出的半导体衬底10之上。接着，形成填满该凹槽35的平坦化栅极导电层65。硬掩模层90接着形成于该栅极导电层65之上。该栅极导电层65包括下栅极导电层70以及上栅极导电层80的堆叠结构。
请参照图2f，利用栅极掩模(未显示)作为蚀刻掩模构图该硬掩模层90和栅极导电层65，以形成栅极99。
然而，根据上述的用于制造半导体器件的方法，该栅极在有关沟道的可控制性方面效率差。再者，该器件的可靠性会由于当该器件的偏压电平改变时所造成的基体效应(body eeffect)而变差。
发明内容
根据本发明，提供了一种用于制造存储器件的方法的技术。具体而言，本发明提出一种用于制造半导体器件的方法，其中外延层被形成在凹形栅极区域的器件隔离结构之上，以形成包括SOI(绝缘体上硅)沟道结构的半导体器件，藉此减少沟道区域的离子注入浓度并且改善该器件的tWR(写入恢复时间)及LTRAS(行地址选通的长时间)的特性。
在本发明的一个实施例中，一种用于制造半导体器件的方法包括：(a)形成器件隔离结构，其在具有垫绝缘膜的半导体衬底上界定有源区域；(b)在该所产生的结构的整个表面上形成硬掩模层图案，该硬掩模层图案露出在凹槽区域中的器件隔离结构以及垫绝缘膜；(c)利用该硬掩模层图案作为蚀刻掩模来蚀刻该露出的器件隔离结构，以形成露出该有源区域的侧壁的凹槽；(d)移去该硬掩模层图案；(e)利用该有源区域的露出的侧壁作为晶种层，以在该凹槽中形成外延层；(f)选择性地蚀刻该外延层预定厚度，以在该凹槽中形成SOI(绝缘体上硅)沟道区域；(g)移去该垫绝缘膜以露出该有源区域；(h)在包括该SOI沟道区域的露出的有源区域上形成栅极绝缘膜；(i)形成填满该凹槽的平坦化栅极导电层以及栅极硬掩模层；并且(j)利用栅极掩模作为蚀刻掩模来构图该栅极硬掩模层与栅极导电层，以形成栅极。
附图说明
图1是一种常规的半导体器件的简化的布局；
图2a至2f是描绘一种用于制造常规的半导体器件的方法的简化的剖面图；
图3是根据本发明的一个实施例的一种半导体器件的简化的布局；以及
图4a至4i是描绘根据本发明的一个实施例的一种用于制造半导体器件的方法的简化的剖面图。
主要器件符号说明
1、101   有源区域
3、103   凹形栅极区域
5、105   栅极区域
10、110  半导体衬底
20、120  器件隔离结构
13、113  垫氧化膜
15、115  垫氮化膜
25       多晶硅层
25a      多晶硅层图案
13a      垫氧化膜图案
35、135  凹槽
60、160  栅极绝缘膜
65       栅极导电层
90       硬掩模层
70、175  下栅极导电层
80、185  上栅极导电层
99、199  栅极
107      位线接触区域
109      储存节点接触区域
117      光致抗蚀剂薄膜图案
119      沟槽
125      硬掩模层图案
133      衬底氧化膜
137      衬垫氮化膜
150      外延层
155      SOI沟道区域
195      栅极硬掩模层
197      栅电极
具体实施方式
现在将详细参考本发明的示范性实施例。只要有可能的话，相同的附图标记将会在所有附图中被用来指示相同或类似的器件。应该理解的是，提供这些实施例是为了描述本发明并且使得本发明对于本领域技术人员而言是可行的。于是，在此所述的实施例可以在不脱离本发明的范畴下加以修改。
图3是根据本发明的一个实施例的一种半导体器件的简化的布局，其中附图标记101、103及105分别代表藉由该器件隔离结构120所界定的有源区域、凹形栅极区域以及栅极区域。
请参照图3，该有源区域101被设置在位线接触区域107以及储存节点接触区域109的半导体衬底处。该凹槽区域(或开口)103是从该位线接触区域107延伸至相邻的储存节点接触区域109的区域。该栅极区域105被设置在该位线接触区域107以及相邻的储存节点接触区域109之间的区域处，亦即，其被设置于该位线接触区域107以及相邻的储存节点接触区域109之间的器件隔离结构120(或是第一类型的隔离结构)之内。该第一类型的器件隔离结构和其它的器件隔离结构(第二类型的隔离结构)一起被形成。不同于该第二类型的器件隔离结构，该第一类型的器件隔离结构之后被用来形成栅极区域/结构。于是，此种第一类型的器件隔离结构也被称为“器件隔离结构”。
图4a至4i是描绘根据本发明的一个实施例的一种用于制造半导体衬底的方法的简化的剖面图，其中该些剖面图是沿着图3的线II-II′所取得的。
请参照图4a与4b，垫氧化膜113、垫氮化膜115以及光致抗蚀剂膜(未显示)被形成在半导体衬底110之上，并且接着利用一界定在图3中所示的有源区域101的掩模来加以曝光及显影，以形成光致抗蚀剂膜图案117。接着，该垫氮化膜115、垫氧化膜113以及半导体衬底110利用作为蚀刻掩模的光致抗蚀剂膜图案117而被蚀刻预定厚度，以形成界定在图3中所示的有源区域101的沟槽(trench)119。该光致抗蚀剂膜图案117接着被移除。之后，衬垫(liner)氧化膜133被形成在该沟槽119的侧壁处。衬垫氮化膜137接着形成在该所产生的结构的整个表面上。
请参照图4c与4d，填满该沟槽119的用于器件隔离的绝缘膜(未显示)被形成在该所产生的结构的整个表面上。该用于器件隔离的绝缘膜接着被抛光直到该垫氮化膜115露出为止，以形成器件隔离结构120。接着，硬掩模层(未显示)被形成在该所产生的结构的整个表面上。之后，光致抗蚀剂膜(未显示)被形成在该硬掩模层之上，并且接着利用界定在图3中所示的凹槽区域103的掩模而被曝光及显影，以形成光致抗蚀剂膜图案(未显示)。在此之后，该硬掩模层利用该光致抗蚀剂膜图案作为蚀刻掩模而被蚀刻以形成硬掩模层图案125，该硬掩模层图案125露出在图3中所示的凹槽区域103中的器件隔离结构120及垫氮化膜115。该光致抗蚀剂膜图案接着被移除。在某些实施例中，该硬掩模层由氮化膜、多晶硅膜、非晶(amorphous)碳膜、SiON膜或其组合制成。
请参照图4e与4f，该露出的器件隔离结构120利用该硬掩模层图案125作为蚀刻掩模而被蚀刻预定厚度，以形成凹槽135。该硬掩模层图案125接着被移除。接着，在该凹槽135中露出的垫氮化膜115及衬垫氮化膜137被移除。之后，在该凹槽135中露出的衬底氧化膜133选择性地被移除，以在该凹槽135的侧壁处露出该半导体衬底110。在某些实施例中，用于移除该垫氮化膜115及衬垫氮化膜137的工艺通过湿式或干式蚀刻方法而被执行。在该凹形栅极区域135中露出的衬底氧化膜133可以藉由各向异性蚀刻方法而被移除。
请参照图4g与4h，外延层150利用在该凹槽135的侧壁处露出的半导体衬底110作为晶种层而被形成。接着，该外延层150的预定厚度选择性地被蚀刻，以在该凹槽135中形成SOI沟道区域155。之后，该垫氧化膜113被移除以露出该半导体衬底110。在某些实施例中，该外延层150藉由固相外延法来生长，并且该SOI沟道区域的厚度范围是从大约50至大约200。
请参照图4i，栅极绝缘膜160被形成在包括该SOI沟道区域155的露出的半导体衬底110之上。填满该凹槽135的平坦化下栅极导电层175被形成。接着，上栅极导电层185以及栅极硬掩模层195被形成在该下栅极导电层之上。之后，该栅极硬掩模层、上栅极导电层以及下栅极导电层被蚀刻以形成栅极199，该栅极199是栅电极197以及栅极硬掩模层195的堆叠结构。
此外，例如是用于在栅极的侧壁上形成间隙壁的工艺、用于在有源区域中形成源极/漏极区域的离子注入工艺、用于形成连接插塞的工艺、用于形成位线接点及位线的工艺、用于形成电容器的工艺、以及用于形成互连的工艺的后续工艺都可被执行。
如上所述，根据本发明的一实施例的用于制造半导体衬底的方法提供形成在器件隔离结构上的沟道区域，以形成包括SOI(绝缘体上硅)沟道结构的半导体器件，藉此减少沟道区域的离子注入浓度并且改进该器件的tWR(写入恢复时间)以及LTRAS(行地址选通的长时间)特征。由于该SOI沟道结构，基体效应也被改善。于是，该器件的栅极可控制性得以改善。
先前针对本发明的各种实施例的说明已经为了举例及说明的目的而被提供。其并非意欲全部列举出或是限制本发明仅止于所揭露的明确的形式，而是依据上述的教示或是从本发明的实施都可以得到对其的修改与变化。该些实施例被选择与描述以便于解说本发明的原理及其实际的应用，以使得本领域技术人员能够在各种实施例中以及在适合所思及的特定用途的各种修改下利用本发明。

Claims (12)

1.一种用于制造半导体器件的方法，该方法包括：
(a)形成器件隔离结构，其在具有垫绝缘膜的半导体衬底上界定有源区域；
(b)在该器件隔离结构之上形成图案化的掩模层，该图案化的掩模层界定露出该器件隔离结构及垫绝缘膜的开口；
(c)利用该图案化的掩模层来蚀刻该露出的器件隔离结构，以形成露出该有源区域的侧壁的凹槽；
(d)移除该图案化的掩模层；
(e)利用该有源区域的露出的侧壁作为晶种层，以在该凹槽中形成外延层；
(f)选择性地蚀刻该外延层预定厚度，以在该凹槽中形成绝缘体上硅沟道区域；
(g)移除该垫绝缘膜以露出该有源区域；
(h)在包括该绝缘体上硅沟道区域的露出的有源区域之上形成栅极绝缘膜；
(i)在该栅极绝缘膜之上形成栅极导电层；以及
(j)构图该栅极导电层，以形成栅极结构。
2.根据权利要求1所述的方法，其中该有源区域对应于位线接触区域或储存节点接触区域。
3.根据权利要求1所述的方法，其中该开口是延伸位线接触区域至相邻的储存节点接触区域的区域。
4.根据权利要求1所述的方法，其中该垫绝缘膜包括垫氧化膜以及垫氮化膜。
5.根据权利要求1所述的方法，其中该图案化的硬掩模层从氮化膜、多晶硅膜、非晶碳膜、SiON膜及其组合所构成的群组中选出。
6.根据权利要求1所述的方法，其中用于形成该外延层的工艺藉由固相外延法而被执行。
7.根据权利要求1所述的方法，其中用于移除该垫绝缘膜的工艺藉由湿式或干式蚀刻方法而被执行。
8.根据权利要求1所述的方法，其中该绝缘体上硅沟道区域的厚度范围是从大约50至大约200。
9.根据权利要求1所述的方法，其中该栅极导电层包括上栅极导电层以及下栅极导电层。
10.根据权利要求1所述的方法，其中形成器件隔离结构包括在该半导体衬底之上形成衬垫氧化膜以及衬垫氮化膜。
11.根据权利要求10所述的方法，其中用于移除该衬垫氮化膜的工艺藉由湿式或干式蚀刻方法而被执行。
12.根据权利要求10所述的方法，其中用于移除该衬垫氧化膜的工艺藉由各向异性蚀刻方法而被执行。
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