TWI304247B - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
TWI304247B
TWI304247B TW095111908A TW95111908A TWI304247B TW I304247 B TWI304247 B TW I304247B TW 095111908 A TW095111908 A TW 095111908A TW 95111908 A TW95111908 A TW 95111908A TW I304247 B TWI304247 B TW I304247B
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Taiwan
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layer
film
gate
region
isolation structure
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TW095111908A
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TW200729393A (en
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Eun Sung Lee
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J45/00—Devices for fastening or gripping kitchen utensils or crockery
    • A47J45/06—Handles for hollow-ware articles
    • A47J45/061—Saucepan, frying-pan handles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J36/00—Parts, details or accessories of cooking-vessels
    • A47J36/34—Supports for cooking-vessels
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J45/00—Devices for fastening or gripping kitchen utensils or crockery
    • A47J45/06—Handles for hollow-ware articles
    • A47J45/062—Bowl handles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Food Science & Technology (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

1304247 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種用於製造一記憶體元件之方法。 尤其’本發明係有關於一種用於製造一半導體元件之方 去其中一蠢晶層係被形成在一凹形閘極區域的元件隔離 二構之上’以形成一包含S0I(絕緣層上覆矽）通道結構的 半導體70件’藉此減少通道區域的離子植入濃度並且改善 元件的tWR(寫入恢復時間）及ltraS(列位址選通的長時 間）的特性。 【先前技術】 圖1疋一種習知的半導體元件之簡化的佈局，其中參 考圖號1、3及5係分別代表一主動區域、一凹形問極區 域以及一閘極區域。 圖2a至2f是描繪—種用於製造—半導體元件之方法 ' 的面圖，其中遠些剖面圖是沿著圖1的線1-1，所 取得的。 :青翏照圖2a，一元件隔離結構2〇係被形成在一半導 1^1 Μ之上，該半導體基板1G係具有—#(pad)氧化膜 13以及一墊氮化膜15。 Ο月參照圖2b，該墊筒J卜日替q H — 鼠化膜15係被移除。離子植入的 、征係接者在整個表面上進 Λ Jm ^ 丁 A在卞導體基板10中形 成-個井以及離子植入區域(未 ： 晶石夕層25係被形成在該 ：千土-化夕 厓生的結構的整個表面上。 1304247 請參照圖2e，該多晶♦層25以及塾氧化膜i3係利用 -凹形閘極光罩（未顯*)作為_光罩而被㈣，以形成 -多晶矽層圖案25a以及-墊氧化膜圖帛Ua以界定在圖 1中所示的凹形閘極區域3。 請參照圖2d，圖1中所示的凹形閘極區域3的半導體 基板10係被敍刻以形成一凹槽（recess)35。該多晶石夕層圖 案25a係在用於形成該凹槽35的製程期間被移除。 .月…'圖& ’ 墊氧化膜圖案13a係、被移除以露出該 半導體基板1 0。一閘極絕缝勝& W往、、巴緣膜60係接著形成在該露出的 半導體基板10之上。接著，一按 、 者 填滿该凹槽3 5的平坦化閘 極導電層6 5係被形成。一石承_i? ™ 饭〜成 硬式先罩層90係接著形成在該 閘極導電層65之上。該閘極導雷 丨甲j位等冤層65係包含一下方的閘 極導電層70以及一上方的閑極導電層肋之堆疊的結構。 請參照圖2f，該硬式光罩層9〇以及閉極導電層“係 利用一閘極光罩（未顯示）作為 )芍蚀到光罩而被形成圖案，以 形成一閘極99。 然而’根據上述的用於製造一半導體元件的方法，該 閑極在^關通道的可控制性方面是效率差的。再者，該元 件的叮罪度會由於當該元件的^ ^ ^ ^ J 1雨&位旱改變時所造成的基 體效應而變差。 【發明内容】 根據本發明， 術係被提出。尤其 種用於製造一記憶體元件之方法的技 本發明係提出一種用於製造一半導體 1304247 一件之方法其中一蠢晶層係被形成在一凹形閘極區域的 ^件隔離結構之上，以形成-包含啊絕緣層上覆石夕）通 逼結構的半導體元件，藉此減少通道區域的離子植入濃度 亚且改善該元件^ W(寫入恢復時間）及LTRAS(列位址選 通的長時間）的特性。 在本發明的—個實施例中，一種用於製造一半導體元 件之方法係包含：⑷形成一元件隔離結構，其係在一具有 -墊絕緣膜的半導體基板上界定—主動區域；（b)在該所產 生的、.Ό構的整個表面上形成一硬式光罩層圖案，該硬式光 罩層圖案係露出在一凹槽區域中的元件隔離結構以及塾絕 $膜；⑷利用該硬式光罩層圖案作為—㈣光罩來姓刻該 露出的元件隔離結構’以形成一露出該主動區域的側壁之 凹槽；⑷移去該硬式光罩層圖案；⑷利用該主動區域之露 出的侧壁作為-晶種層，以在該凹槽中形成一蟲晶層；⑴ 選擇性地姓刻該蟲晶層一預設的厚度，以在該凹槽中形成 鲁-sm(絕緣層上覆石夕）通道區域；（g)移去該塾絕緣膜以露 出該主動區域；⑻在包含該S0I通道區域之露出的主動區 域上形成一閘極絕緣膜.；（i)形成一填滿該凹槽的平坦化閘 極導電層以及-閘極硬式光罩層；並且⑴利用一閑極光罩 作為一蝕刻光罩來使得該閘極硬式光罩層以及閘極導電層 形成圖案’以形成一閘極。 【實施方式】 現在將詳細參考本發明之範例 σ ^ . 礼燜的貫施例。只要有可能 1304247 的話，相同的參考圖號將會在整個圖式被利用來參照相同 或類似的元件。應該體認到的是，該些實施例係被提供來 描述本發明並且使得本發明對於熟習此項技術者而言是可 行的。於是，在此所述的實施例可以在不脫離本發明的範 臂下加以修改。 圖3是根據本發明的一個實施例之一種半導體元件的 簡化的佈局，其中參考圖號101、1〇3及1〇5係分別代表
一藉由該元件隔離結構12〇所界定的主動區域、一凹形閉 極區域以及一閘極區域。 睛筝照圖3，該主動區域丨〇丨係被設置在一位元線的 接點區域107以及一儲存節點的接點區域1〇9的半導體基 板處。該凹槽區域（或開口）1〇3是一個從該位元線的接點 區域107延伸至相鄰的儲存節點的接點區域ι〇9之區域。 該閘極區…05係被設置在該位元線的接點區域107以及 相鄰的儲存節點的接點區域1〇9之間的一個區域處，亦即， 其係在被設置於該位元線的 勺接”，、占£域107以及相鄰的儲存 即點的接點區域109之間沾-从„ 1的70件隔離結構12〇(或是第一 型的隔離結構）之内。該第一 類 ^ — π 弟類型的元件隔離結構係和复仓 的兀件隔離結構（第二類都 /、匕 頰型的隔離結構）一起被形成。 於該第二類型的元件隔離 同 Μ ^ ^ ^ m + 邊弟一類型的元件隔離姓 構之後係被用來形成—個閑極區 隹、、、° 相荆AA -从 A /、、、吉構。於是，此種箓 類型的7L件隔離結構亦被 喱弟一 圖心41是描^元件隔離結構”。 於製造-半導體基板之方^的-個貫施例之-種用 '勺間化的剖面圖，其中該些剖 1304247 面圖是沿著圖3的線π-π，所取得的。 、請參照圖4a與4b，一墊氧化膜113、一墊氮化膜U5 乂及光阻膜（未顯不）係被形成在一半導體基板丨丨〇之 上，亚且接著利用—界定在圖3中所示的主動區域101之 光罩來加以曝光及顯影，以形成一光阻膜圖案117。接著， 該墊氮化膜115、墊氧化膜113以及半導體隸110係利 用作為i刻光罩的光阻膜圖案1Π而被㈣卜預設的厚 又、开/成界疋在圖3中所示的主動區域101的溝槽 ⑽nch)119。該光阻膜圖案117係接著被移除。之後，一 氧化g 133係被形成在該溝槽m #側壁處。 概底氮化膜137係接著形成在該所產生的結構的整個表 面上。 請參照圖4c與4d，一填滿該溝槽119之用於元件隔 離的、.’巴、’彖膜(未顯不)係被形成在該所產生的結構的整個表 X用於元件隔離的絕緣膜係接著被拋光直到該墊氮 化膜115露出為止’以形成一元件隔離結才冓12〇。接著， -硬式光罩層（未顯示）係被形成在該所產生的結構的整個 表面上之後 光阻膜（未顯示）係被形成在該硬式光罩 層之上，並且接著利用-界定在圖3中所示的凹槽區域1〇3 之光罩而被曝光及顯影’以形成一光阻膜圖案(未顯示）。 在此之後，該硬式光罩層係利用該光阻膜圖案作為一姓刻 光罩而被蝕刻以形成-硬式光罩層圖帛125,該硬式光罩 層圖案⑵係露出在圖3中所示的凹槽區域ι〇3中之 隔離結構m及塾氮化膜115。該光阻膜圖案係接著被移 1304247 除。在某些實施例中，該硬式光罩層係由一氮化膜、—多 晶矽膜、一非晶系（amorphous)碳膜、一 Si0N膜或該等膜 之組合所製成。 睛參照圖4e與4f，該露出的元件隔離結構丨2〇係利 用該硬式光罩層圖案125作為一蝕刻光罩而被蝕刻一預設 的厚度，以形成一凹槽135。該硬式光罩層圖案125係^ 著被移除。接著，在該凹槽U5中露出的墊氮化膜115及 襯底氮化膜1 3 7係被移除。之後，在該凹槽丨3 $中露出的 襯底氧化膜133係選擇性地被移除，以在該凹槽135的側 壁處露出該半導體基板110。在某些實施例中，用於移除 該塾氮化膜115及襯底氮化膜137的製程係藉由一種濕式 或乾式蝕刻方法而被執行。在該凹形閘極區域135中露出 的襯底氧化膜133可以藉由一種非等向性蝕刻方法而被移 除。 請參照圖4g與4h，一磊晶層15〇係利用在該凹槽ι35 的側壁處露出的半導體基板110作為一晶種層而被形成。 接著，該磊晶層150之一預設的厚度係選擇性地被蝕刻， 以在該凹槽135中形成一個SOI通道區域155。之後，該 墊氧化膜113係被移除以露出該半導體基板11 〇。在某些 實施例中，該磊晶層1 50係藉由一種固相磊晶法來生長， 並且該SOI通道區域的厚度範圍是從大約5〇A至大約 200A。 請參照圖4i，一閘極絕緣膜！ 6〇係被形成在包含該s〇I 通道區域1 5 5之露出的半導體基板丨丨〇之上。一填滿該凹 10 1304247 槽135的平坦化下方的閘極導電層175係被形成。接著， -上方的閘極導電層185以及—閘極硬式光罩層195係被 形成在該下方的間極導電層之上。之後，該閉極硬式光罩 層、上方的閘極導電層以及下方的閘極導電層係被蝕刻以 形成一閘極199，該間極199是一閘極電極197以及一閘 極硬式光罩層1 95之堆疊的結構。 此外，例如是用於在閘極的側壁上形成一間隙壁的製 程、用於在主動區域中形成源極/汲極區域的離子植入的製 程、用於形成連接插塞的製程、用於形成位元線接點及^ 元線的製程、用於形成電容器的製程、以及用於形成内連 線的製程之後續的製程都可被執行。 如上所述，根據本發明的一個實施例之用於製造一半 導體基板的方法係提供一個形成在一元件隔離結構上之通 這區域，以形成一個包含一 s〇I(絕緣層上覆矽）通道結構 的半導體7G件，藉此減少通道區域的離子植入濃度並且改 進該兀件的tWR(寫入恢復時間）以及LTRAS(列位址選通的 長時間）特徵。由於該S0I通道結構，基體效應亦被改善。 於是’該元件的閘極可控制性係被改善。 先丽針對本發明的各種實施例的說明已經為了舉例及 說明之目的而被提供。其並非意欲全部列舉出或是限制本 發明僅止於所揭露的明確的形式，而是依據上述的教示或 是從本發明的實施都可以得到對其的修改與變化。該些實 施例係被選擇與描述以便於解說本發明的原理及其實際的 XI'用 以使付^習此項技術者能夠在各種的實施例中以及 11 1304247 在適合所思及的特定用途之各種修改下利用本發明。 【圖式簡單說明】 圖1是-種習知的半導體元件之簡化的佈局； 圖2 a至2 f是描繪一種用於掣皮 知的半導體元件 之方法的間化的剖面圖； 圖3是根據本發明的一 簡化的佈局；以及 自…列之-種半導體元件的 圖4a至4i是描繪根據本發 於製造一半導體元件之方 個貫施例之一種用 的間化的剖面圖。 【主要元件符號說明】 1、101主動區域 3、103凹形閘極區域 5、105閘極區域 10、110半導體基板 20、120元件隔離結構 1 3、11 3墊氧化膜 1 5、11 5墊氮化膜 2 5多晶秒層 25a多晶石夕層圖案 1 3 a墊氧化膜圖案 35、135凹槽 60、160閘極絕緣膜 12 1304247 65閘極導電層 90硬式光罩層 70、175下方的閘極導電層 80、185上方的閘極導電層 99、199閘極 107位元線的接點區域 109儲存節點的接點區域 11 7光阻薄膜圖案
11 9溝槽 125硬式光罩層圖案 133襯底氧化膜 137襯底氮化膜 150磊晶層 155 SOI通道區域 195閘極硬式光罩層 197閘極電極
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1304247 十、申請專利範圍： 1· 一種用於製造-半導體元件之方法，該方法係包括： ⑷形成一元件隔離結構，其係在一具 半導體基板上界定-主動區域； 邑緣膜的 ::)在該元件隔離結構之上形成一形成有圖案的光罩 及塾絕緣膜的開口 界疋一露出該元件隔離結構 :)利用該形成有圖案的光罩層來钮刻該露出的元件隔 、、口冓，以形成一露出該主動區域的側壁之凹槽； (d)移除该形成有圖案的光罩層； ()利用4主動區域之露出的側壁作為 該凹槽中形成一蠢晶層； 以在 (f) 選擇性地钱刻該蠢晶層一預設的厚度，以在該凹槽 中形成一 SOI(絕緣層上覆矽）通道區域； (g) 移除該墊絕緣膜以露出該主動區域； I “亥SQI通道區域之露出的主動區域之上形成 一閘極絕緣膜； ⑴在該問極絕緣膜之上形成_開極導電層；以及 ⑴使該閘極導電層形成圖案’以形成—閘極結構。 係對2庫根射請專利範㈣1項之方法，其中該主動區域 域。Ά &70線的接點區域或是-儲存節點的接點區 3.根據中請專利範圍第i項之方法，其中該開口是— 個延伸-位元線的接點區域至相鄰的儲存節點的接點區域 14 1304247 之區域。 虞申明專利範圍第1項之方法，其中該墊絕緣膜 係包含-塾氧化膜以及一墊氮化膜。 、 5·根據申請專利範圍第1項之方法，其中該形成有圖 月:的：式光罩層係從-氮化膜、-多晶矽膜、-非晶系碳 ' N膜以及該等膜的組合所構成的群組中選出。
6·根據申請專利範圍第1項之方法，其中用於形成該 蟲晶層的製程係藉由一種固相蟲晶法而被執行。 7·根據申請專利範圍繁 墊絕緣膜的製…:一 ,，其令用於移除該 y ’、9由種濕式或乾式钱刻方法而被執 行0 Λ根據申請專利範圍第1項之方法，其中該SOI通道 區域的厚度範圍是從大約50A至大約200A。 9 ·根據申請專利餘_ | 圍 項之方法，其中該閘極導電 層係包括一上方06 P弓;音Α Ω 万的閘極導電層以及一下方的閘極導。 10·根據申請專利截圖隹 曰 j乾圍第1項之方法，其中形成一 隔離結構係包含在嗲主道Μ * 1 χ 疋什 在忒丰導體基板之上形成一襯底氧 及一襯底氮化膜。 .UG胰从 π·根據申請專利範圍第 該襯底氮化膜的製程係藉由 執行。 12 ·根據申請專利範圍第 该概底氧化膜的製程係藉由 行。 1 〇項之方法，其中用於移除 一種濕式或乾式蝕刻方法而被 項之方法，其中用於移除 一種非等向性蝕刻方法而被執 15
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CN100505215C (zh) 2009-06-24
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KR100673133B1 (ko) 2007-01-22
TW200729393A (en) 2007-08-01
CN101009243A (zh) 2007-08-01
JP5105785B2 (ja) 2012-12-26

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