JP5105785B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 238000000034 method Methods 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000003860 storage Methods 0.000 claims description 7
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000000348 solid-phase epitaxy Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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Description
図12〜図17は、従来の技術に係る半導体素子の製造方法を示し、図11のI−I’に沿う断面図である。
図13に示されているように、パッド窒化膜15を除去した後、全体表面にイオンを注入して半導体基板10にウェル及びチャンネルイオン注入領域(図示省略)を形成する。次に、全体表面上部に平坦化されたポリシリコン層25を形成する。
図15に示されているように、図11のリセスゲート領域3の半導体基板10を所定厚さに食刻してリセスゲート領域35を形成する。このとき、リセスゲート領域35の形成時にポリシリコン層パターン25aも同時に除去される。
図17に示されているように、ゲートマスク(図示省略)を食刻マスクにハードマスク層90とゲート導電層65をパターニングしてゲート構造物99を形成する。
(a)パッド絶縁膜が備えられた半導体基板に活性領域を画成する素子分離構造を形成した後、全体表面上部にリセス領域を露出するハードマスク層パターンを形成する段階と、
(b)前記ハードマスク層パターンを食刻マスクに前記リセス領域内に露出した素子分離構造を所定厚さに食刻して前記活性領域の側壁を露出するリセスゲート領域を形成する段階と、
(c)前記ハードマスク層を除去した後、前記露出した活性領域の側壁をシード層(Seed layer)にして前記リセスゲート領域内にエピタキシャル層(Epitaxial layer)を形成する段階
と、
(d)前記エピタキシャル層を所定厚さに選択的に食刻して前記リセスゲート領域内にSOI(Silicon-On-Insulator)チャンネル領域を形成する段階と、
(e)前記パッド絶縁膜を除去して前記活性領域を露出する段階と、
(f)前記SOIチャンネル領域を含む前記露出した活性領域上部にゲート絶縁膜を形成する段階と、
(g)前記リセスゲート領域を埋め込むゲート導電層を形成した後、その上部にゲートハードマスク層を形成する段階と、
(h)ゲートマスクを食刻マスクに前記ゲートハードマスク層及びゲート導電層をパターニングしてゲートを形成する段階と
を含むことを特徴としている。
前記活性領域は、ビットラインコンタクト領域または格納電極コンタクト領域に相当することを特徴としている。
前記リセスゲート領域は、ビットラインコンタクト領域からその両側に隣接した格納電極コンタクト領域まで延長された領域であることを特徴としている。
前記パッド絶縁膜は、パッド窒化膜とパッド酸化膜の積層構造でなることを特徴としちる。
前記ハードマスク層パターンは、窒化膜、ポリシリコン膜、非晶質炭素膜、SiON膜及びこれらの組み合わせのうち選択されたいずれか一つで形成することを特徴としている。
前記エピタキシャル層の形成工程は、固体状エピタキシ法で行われることを特徴としている。
前記パッド絶縁膜の除去工程は、湿式または乾式食刻方法で行われることを特徴としている。
前記SOIチャンネル領域の厚さは50〜200Åであることを特徴としている。
図1は、本発明の一つの実施の形態に係り素子分離構造120により画成される活性領域101、リセス領域103及びゲート領域105を示す半導体素子のレイアウトである。図1に示されているように、活性領域101はビットラインコンタクト領域107と格納電極コンタクト領域109に位置し、リセス領域103はビットラインコンタクト領域107からその両側に隣接した格納電極コンタクト領域109まで延長された領域であり、ゲート領域105は活性領域101等の間の素子分離構造120上部に形成される。
図2及び図3に示されているように、半導体基板110上部にパッド酸化膜113、パッド窒化膜115及び感光膜(図示省略)を形成した後、図3の活性領域101を画成するマスクで感光膜を露光及び現像して感光膜パターン117を形成する。次に、感光膜パターン117を食刻マスクにパッド窒化膜115、パッド酸化膜113及び半導体基板110を所定厚さに食刻して図1の活性領域101を画成するトレンチ119を形成した後、感光膜パターンを除去する。以後、トレンチ119側壁にライナー酸化膜133を形成し、全体表面にライナー窒化膜137を形成する。
103 リセス領域
105 ゲート領域
107 ビットラインコンタクト領域
109 格納電極コンタクト領域
110 半導体基板
113 パッド酸化膜
115 パッド窒化膜
117 感光膜パターン
119 トレンチ
120 素子分離構造
125 ハードマスク層パターン
133 ライナー酸化膜
135 リセスゲート領域
137 ライナー窒化膜
150 エピタキシャル層
155 SOIチャンネル領域
160 ゲート絶縁膜
195 ゲートハードマスク層パターン
197 ゲート電極
199 ゲート構造物
Claims (8)
- (a)パッド絶縁膜が備えられた半導体基板に活性領域を画成する素子分離構造を形成した後、全体表面上部にリセス領域を露出するハードマスク層パターンを形成する段階と、
(b)前記ハードマスク層パターンを食刻マスクに前記リセス領域内に露出した素子分離構造を所定厚さに食刻して前記活性領域の側壁を露出するリセスゲート領域を形成する段階と、
(c)前記ハードマスク層を除去した後、前記露出した活性領域の側壁をシード層にして前記リセスゲート領域内にエピタキシャル層を形成する段階と、
(d)前記エピタキシャル層を所定厚さに選択的に食刻して前記リセスゲート領域内にSOIチャンネル領域を形成する段階と、
(e)前記パッド絶縁膜を除去して前記活性領域を露出する段階と、
(f)前記SOIチャンネル領域を含む前記露出した活性領域上部にゲート絶縁膜を形成する段階と、
(g)前記リセスゲート領域を埋め込むゲート導電層を形成した後、その上部にゲートハードマスク層を形成する段階と、
(h)ゲートマスクを食刻マスクに前記ゲートハードマスク層及びゲート導電層をパターニングしてゲートを形成する段階と
を含むことを特徴とする半導体素子の製造方法。 - 前記活性領域は、ビットラインコンタクト領域または格納電極コンタクト領域に相当することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記リセスゲート領域は、ビットラインコンタクト領域からその両側に隣接した格納電極コンタクト領域まで延長された領域であることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記パッド絶縁膜は、パッド窒化膜とパッド酸化膜の積層構造でなることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記ハードマスク層パターンは、窒化膜、ポリシリコン膜、非晶質炭素膜、SiON膜及びこれらの組み合わせのうち選択されたいずれか一つで形成することを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記エピタキシャル層の形成工程は、固体状エピタキシ法で行われることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記パッド絶縁膜の除去工程は、湿式または乾式食刻方法で行われることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記SOIチャンネル領域の厚さは50〜200Åであることを特徴とする請求項1に記載の半導体素子の製造方法。
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KR1020060006968A KR100673133B1 (ko) | 2006-01-23 | 2006-01-23 | 반도체 소자의 제조 방법 |
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KR100790296B1 (ko) * | 2006-12-04 | 2008-01-02 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조방법 |
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KR101000472B1 (ko) * | 2008-05-07 | 2010-12-14 | 주식회사 하이닉스반도체 | Soi 소자 및 그의 제조방법 |
KR101035393B1 (ko) * | 2008-11-06 | 2011-05-20 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
KR101150552B1 (ko) | 2009-12-04 | 2012-06-01 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그의 형성 방법 |
KR101610831B1 (ko) * | 2010-02-09 | 2016-04-12 | 삼성전자주식회사 | 비트 라인 배선이 비트 라인 콘택 상에서 그 폭이 확장되고 그 레벨이 낮아지는 반도체 소자 및 그 제조방법 |
KR101095745B1 (ko) * | 2010-04-07 | 2011-12-21 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US8877582B2 (en) | 2013-02-20 | 2014-11-04 | Globalfoundries Inc. | Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode |
JP6629159B2 (ja) * | 2016-09-16 | 2020-01-15 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR20180049337A (ko) * | 2016-10-31 | 2018-05-11 | 삼성전자주식회사 | 반도체 메모리 장치의 제조 방법 |
CN111640703A (zh) * | 2019-07-02 | 2020-09-08 | 福建省晋华集成电路有限公司 | 半导体结构及其形成方法 |
US11069774B2 (en) * | 2019-09-26 | 2021-07-20 | Fujian Jinhua Integrated Circuit Co., Ltd. | Shallow trench isolation structure and semiconductor device with the same |
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JPH03200350A (ja) * | 1989-12-27 | 1991-09-02 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5214603A (en) * | 1991-08-05 | 1993-05-25 | International Business Machines Corporation | Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors |
JPH08316335A (ja) * | 1995-05-18 | 1996-11-29 | Sony Corp | 半導体装置およびその製造方法 |
FR2746544B1 (fr) * | 1996-03-20 | 1998-05-15 | Commissariat Energie Atomique | Substrat de type silicium sur isolant pour la fabrication de transistors et procede de preparation d'un tel substrat |
US6093614A (en) * | 1998-03-04 | 2000-07-25 | Siemens Aktiengesellschaft | Memory cell structure and fabrication |
JP3884266B2 (ja) * | 2001-02-19 | 2007-02-21 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
KR100526852B1 (ko) * | 2003-08-18 | 2005-11-08 | 주식회사 케이이씨 | 트랜지스터 및 그 제조 방법 |
KR20050043424A (ko) * | 2003-11-06 | 2005-05-11 | 삼성전자주식회사 | 트랜지스터의 리세스 채널 형성 방법 |
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JP2007201402A (ja) | 2007-08-09 |
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CN101009243A (zh) | 2007-08-01 |
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