CN112530916A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN112530916A
CN112530916A CN202010106894.8A CN202010106894A CN112530916A CN 112530916 A CN112530916 A CN 112530916A CN 202010106894 A CN202010106894 A CN 202010106894A CN 112530916 A CN112530916 A CN 112530916A
Authority
CN
China
Prior art keywords
metal pad
semiconductor chip
semiconductor
semiconductor device
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010106894.8A
Other languages
English (en)
Other versions
CN112530916B (zh
Inventor
百百信幸
中塚圭祐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Publication of CN112530916A publication Critical patent/CN112530916A/zh
Application granted granted Critical
Publication of CN112530916B publication Critical patent/CN112530916B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4821—Bridge structure with air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/065—Material
    • H01L2224/06505—Bonding areas having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08052—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08057—Shape in side view
    • H01L2224/08058—Shape in side view being non uniform along the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/0807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0901—Structure
    • H01L2224/0903—Bonding areas having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0905—Shape
    • H01L2224/09051—Bonding areas having different shapes
    • H01L2224/09055—Bonding areas having different shapes of their bonding interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0951—Function
    • H01L2224/09515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1205—Capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

实施方式提供一种具备低成本且电容器特性优异的电容元件的半导体装置。实施方式的半导体装置(1)具备：第一半导体芯片(2)，具备第一金属焊盘(4)和第二金属焊盘(5)；以及第二半导体芯片(3)，具备与第一金属焊盘(4)接合的第三金属焊盘(8)和隔着介电层(12、14)而与第二金属焊盘(5)对置配置的第四金属焊盘(9)，第二半导体芯片(3)经由第一金属焊盘(4)和第三金属焊盘(8)而与第一半导体芯片(2)贴合。

Description

半导体装置及其制造方法
相关申请
本申请享受以日本专利申请2019－168887号(申请日：2019年9月17日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的所有内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
作为用于半导体装置等的电容元件，已知有MIM(金属(Metal)－绝缘物(Insulator)－金属(Metal))构造、MOM(金属(Metal)－氧化物(Oxide)－金属(Metal))构造、MOS(金属(Metal)－氧化物(Oxide)－半导体(Semiconductor))构造等。
发明内容
本发明将要解决的课题在于，提供具备低成本且能够实现高集成·大电容且电压依赖性小的电容元件的半导体装置及其制造方法。
实施方式的半导体装置具备：第一半导体芯片，具备第一金属焊盘和第二金属焊盘；以及第二半导体芯片，具备与所述第一金属焊盘接合的第三金属焊盘、以及隔着介电层而与所述第二金属焊盘对置配置的第四金属焊盘，所述第二半导体芯片经由所述第一金属焊盘和所述第三金属焊盘而与所述第一半导体芯片贴合。
附图说明
图1是表示实施方式的半导体装置的一部分的剖面图。
图2是表示实施方式的半导体装置的其他一部分的剖面图。
图3是表示图1所示的半导体装置的制造工序的剖面图。
图4是表示图2所示的半导体装置的制造工序的剖面图。
图5是表示实施方式的半导体装置的变形例的立体图。
图6是表示实施方式的半导体装置的变形例的俯视图。
图7是表示实施方式的半导体装置的整体构造的一个例子的剖面图。
附图标记说明
1…半导体装置，2…第一半导体芯片，3…第二半导体芯片，4…第一金属焊盘，5…第二金属焊盘，6…第一绝缘层，7…第一布线层，8…第三金属焊盘，9…第四金属焊盘，10…第二绝缘层，11…第二布线层，12…绝缘层，13、15…电容元件，14…空隙层。
具体实施方式
以下，参照附图对实施方式的半导体装置进行说明。
另外，在各实施方式中，有时对实质上相同的构成部位标注相同的附图标记，并将其说明省略一部分。附图为示意性的，有厚度与平面尺寸的关系、各部的厚度的比率等与现实不同的情况。说明中的上下等的表示方向的词语在无特别明示的情况下，表示以后述的第一半导体芯片的金属焊盘的形成面为上方的情况下的相对方向，有与以重力加速度方向为基准的现实方向不同的情况。
图1是表示实施方式的半导体装置1的一部分的剖面图。另外，在图1中，将纸面左右方向设为x方向，将纸面深度方向设为y方向，将纸面上下方向设为z方向。其他图也相同。图1所示的半导体装置1具备第一半导体芯片2与第二半导体芯片3。第一半导体芯片2与第二半导体芯片3贴合，由此构成了所示的半导体装置1。附图标记S示出了第一半导体芯片2与第二半导体芯片3的贴合面。另外，图1放大示出了第一半导体芯片2与第二半导体芯片3的贴合部分，但如后述那样，第一以及第二半导体芯片2、3分别具备晶体管等半导体元件、布线层。
第一半导体芯片2具备第一金属焊盘4、第二金属焊盘5、以及埋入有这些第一以及第二金属焊盘4、5的第一绝缘层6。在第一以及第二金属焊盘4、5连接有布线层7。第二半导体芯片3具备第三金属焊盘8、第四金属焊盘9、埋入有这些第三以及第四金属焊盘8、9的第二绝缘层10。在第三以及第四金属焊盘8、9连接有布线层11。在本实施方式中，作为一个例子，在第一绝缘层6仅设有第一金属焊盘4与第二金属焊盘5，但在第一绝缘层6设有多个金属焊盘。同样，在第二绝缘层10仅设有第三金属焊盘8与第四金属焊盘9，但设有与设于第一绝缘层6的多个金属焊盘的各个连接的金属焊盘。另外，这里示出了在第一以及第三金属焊盘4、8连接有布线层7、11的状态，但第一金属焊盘4以及第三金属焊盘8也可以是未连接于布线层的虚设焊盘。
第一金属焊盘4与第三焊盘8有助于第一半导体芯片2与第二半导体芯片3的贴合。另外，第一绝缘层6与第二绝缘层10也有助于第一半导体芯片2与第二半导体芯片3的贴合。即，利用范德华力等使在第一半导体芯片2的表面露出的第一金属焊盘4的表面与在第二半导体芯片3的表面露出的第三金属焊盘8的表面直接接合，并且利用范德华力等使在第一半导体芯片2的表面露出的第一绝缘层6的表面与在第二半导体芯片3的表面露出的第二绝缘层10的表面直接接合，从而将第一半导体芯片2与第二半导体芯片3贴合。
另外，在图1中，为了方便，图示了第一金属焊盘4与第三金属焊盘8的界面以及第一绝缘层6与第二绝缘层10的界面，但有时直接接合的第一金属焊盘4与第三金属焊盘8以及第一绝缘层6与第二绝缘层10被一体化，不存在可目视确认的界面。但是，通过分析半导体装置1的剖面，能够辨别第一半导体芯片2与第二半导体芯片3贴合。另外，在第一至第四金属焊盘4、5、8、9中使用铜、铜合金等，但也可以由除它们以外的金属材料构成。在第一以及第二绝缘层6、10中使用氧化硅(SiO2)、氮氧化硅(SiON)、氮化硅(Si3N4)等，但也可以由除它们以外的绝缘材料构成，但是优选的是金属氧化物、金属氮氧化物、金属氮化物等无机绝缘物。
第一半导体芯片2具有不直接参与贴合的第二金属焊盘5，第二半导体芯片3具有不直接参与贴合的第四金属焊盘9。在这些第二金属焊盘5与第四金属焊盘9之间配置有作为介电层的绝缘层12。即，第二金属焊盘5与第四金属焊盘9隔着绝缘层12对置配置。第二金属焊盘5、第四金属焊盘9与绝缘层12构成了MIM构造的电容元件(电容器)13。作为绝缘层12，能够使用氧化硅(SiO2)、氮氧化硅(SiON)、氮化硅(Si3N4)等、钛酸钡(BaTiO3)、锆酸铅(PbZrO3)、钛酸铅(PbTiO3)等、HfO2等高介电常数绝缘材料、掺氟的氧化硅(SiOF)、掺碳的氧化硅(SiOC)等低介电常数绝缘材料等各种电介质材料。
对于具有第二金属焊盘5/绝缘层12/第四金属焊盘9的构造的电容元件13而言，由于将在金属贴合工序中利用的多个金属焊盘的一部分利用于电容元件的电极(5、9)，因此仅靠在金属贴合工序中追加绝缘层12的形成工序就能够形成。因而，能够以低成本提供MIM构造的电容元件13。在贴合中，在多个金属焊盘中的、作为未与布线连接的虚设焊盘使用的金属焊盘间，设置介电层，从而能够将电极间置换为电容元件。由此，能够通过置换为布线层的电容元件而提高半导体芯片的面积效率。另外，为了用作电容元件，将金属焊盘与布线电连接。另外，具有绝缘层12作为介电层的电容元件13具有能够通过选择绝缘层12的构成材料而提高介电常数并提高每单位面积的电容这一优点。但是，若绝缘层12的膜厚过厚而高低差变大，则担心难以通过贴合工序进行第一半导体芯片2与第二半导体芯片3的贴合，因此绝缘层12的膜厚优选的是5nm以下。如果绝缘层12的膜厚为5nm以下，则能够不阻碍第一金属焊盘4与第三金属焊盘8的接合地、在第二金属焊盘5与第四金属焊盘9之间配置绝缘层12而形成电容元件13。
电容元件13中的介电层并不限定于绝缘层12。例如，如图2所示，也可以在第二金属焊盘5与第四金属焊盘9之间配置作为介电层的空隙层14、换言之是气隙。在该情况下，第二金属焊盘5与第四金属焊盘9经由空隙层14而对置配置。第二金属焊盘5、第四金属焊盘9与空隙层14构成了电容元件(电容器)15。电容元件15具有气隙，因此具有耐压优异这一优点。在构成气隙类型的电容元件15时，空隙层14的深度优选的是邻接的金属焊盘的膜厚以下。
形成电容元件13、15的第二以及第四金属焊盘5、9的形状可以与通常的贴合工序中的金属焊盘相同，为正方形。但是，在该情况下，在第一半导体芯片2与第二半导体芯片3之间产生了位置偏移(未对准)的情况下，担心电容元件13、15的面积变动、并且电容元件13、15的电容产生偏差。对于这一点，具有图5所示那样的平面形状的第二以及第四金属焊盘5、9是有效的。即，第二金属焊盘5优选的是，在与第一以及第二半导体芯片2、3平行的x方向上的长度比第四金属焊盘9的x方向上的长度长，此外，第二金属焊盘5优选的是，在与第一以及第二半导体芯片2、3平行的y方向上的长度比第四金属焊盘9的y方向上的长度短。这些条件只要满足至少一方即可，更优选的是满足两方。
优选的是具有这种平面形状的第二金属焊盘5的x方向与第四金属焊盘9的y方向正交地配置。另外，介电层(绝缘层12或者耗尽层14)也可以设于在x方向上比第四金属焊盘9长的第二金属焊盘5上。即，可以在不与第四金属焊盘9重叠的第二金属焊盘5的面上也设有介电层。虽然在图5中记载为一个例子，但也可以是第二金属焊盘5的x方向的长度比第四金属焊盘9长，在y方向上长度大致相同。另外，也可以是，第四金属焊盘9的y方向的长度比第二金属焊盘5的y方向的长度长，在x方向上大致相同。在该情况下，介电层也可以设于不与第二金属焊盘5重叠的面、且是第四金属焊盘9的面。通过使用具有这种形状的第二以及第四金属焊盘5、9，如图6的(A)以及图6的(B)所示，即使第二金属焊盘5与第四金属焊盘9之间产生了位置偏移，也能够将隔着介电层配置的第二金属焊盘5与第四金属焊盘9的重合面积保持为一定。因而，能够获得减少了电容的偏差的电容元件13、15。
接下来，参照图7对具有图1或者图2所示的电容元件13、15的半导体装置1的整体构成的一个例子进行说明。图7所示的半导体装置1由贴合的第一半导体芯片2以及第二半导体芯片3构成。在第一半导体芯片2设有包含第一以及第二金属焊盘4、5的多个金属焊盘。第一半导体芯片2中可以包含半导体基板也可以不包含半导体基板。在本实施方式中，作为一个例子，以包含半导体基板来进行说明。在半导体基板上形成单层或者多层的布线层，以及具有形成在半导体基板上的晶体管、无源元件等多个第一元件21。另外，在第一半导体芯片2设有存储单元。存储单元设于沿z方向相互分离地层叠的多个导电体与贯通多个导电体而设置的柱的交叉部。存储单元例如由柱、隧道绝缘膜、电荷蓄积膜，阻挡绝缘膜构成。存储单元具有存储信息的功能。构成存储单元的多个导电体中的一个导电体电连接于金属焊盘。作为多个第一元件21的一部分的半导体元件在栅极电极连接着第一布线层7的一端。第一布线层7也可以连接于第一半导体元件21以外的部分。连接于第一半导体元件21的栅极电极等的第一布线层7的另一端连接于构成金属贴合部的第一金属焊盘4、构成电容元件13的第二金属焊盘5。
在第二半导体芯片3也同样设有包含第三以及第四金属焊盘8、9的多个金属焊盘。第二半导体芯片3设于第一半导体芯片2上。在第二半导体芯片3可以包含半导体基板也可以不包含半导体基板。在第二半导体芯片设置单层或者多个层的布线层，以及具有在设于第二半导体芯片的半导体基板上形成的晶体管、无源元件等多个第二元件22。多个第二元件22中的半导体元件的一部分在栅极电极连接着第二布线层11的一端。连接于第二半导体元件22的栅极电极等的第二布线层11的至少一部分的另一端连接于构成金属贴合部的第三金属焊盘8、构成电容元件13的第四金属焊盘9。第二布线层11可以将多个第二半导体元件22的栅极电极间连接，此外，也可以将第三金属焊盘8与第四金属焊盘9之间连接。
上述那样的第二布线层11的连接构造在第一半导体芯片2的第一布线层7中也相同，第一以及第二布线层7、11能够配置成根据半导体装置1的功能形成各种电路。在图7中，示出了具有绝缘层12的电容元件13，但是当然也可以是具有空隙层14的电容元件15，此外，它们也可以混合存在。另外，在将设于第一半导体芯片2的存储单元与设于第二半导体芯片3的元件电连接的金属焊盘间也可以不设置介电层。即，与存储单元和元件电连接的金属焊盘不被用作电容元件。而且，在图7所示的半导体装置1中，虽然省略了图示，但第一半导体芯片2具有未连接于第一布线层7的金属焊盘，并且第二半导体芯片3具有未连接于第二布线层11并且与第一半导体芯片2的金属焊盘接合的金属焊盘。
在图7所示的半导体装置1中，利用原本构成金属贴合部的第一至第四金属焊盘4、5、8、9的一部分形成了MIM构造的电容元件13、15，因此能够以低成本获得每单位面积的电容、线形成(电压依赖性)等方面优异的电容元件13、15。而且，通过在构成电容元件13、15的第二以及第四金属焊盘5、9利用原本形成金属贴合部的虚设焊盘的一部分，能够不新配置金属焊盘地形成电容元件13、15。因而，能够不使半导体装置1内的金属焊盘的形成面积增大地获得具有上述那样的电容元件13、15的半导体装置1。
具有图1所示的电容元件13的半导体装置1例如如图3所示而制作。首先，与通常的贴合工序相同，准备露出了第一金属焊盘4、第二金属焊盘5、以及第一绝缘层6的表面的第一半导体芯片(半导体基板)2。第一半导体芯片(半导体基板)2的表面例如通过CMP而被平坦化。在这种第一半导体芯片2的表面，如图3的(A)所示那样成膜出成为介电层的绝缘膜16。接着，如图3的(B)所示，通过照相雕刻工艺(PEP：Photo Engraving Process)，根据电容元件13的绝缘层12的形状形成掩模层17。
通过利用掩模层17将绝缘膜16的不需要部分蚀刻去除，从而如图3的(C)所示那样在第二金属焊盘5上形成绝缘层12。在具有这种绝缘层12的第一半导体芯片(半导体基板)2上如图3的(D)所示那样贴合露出了第三金属焊盘8、第四金属焊盘9、以及第二绝缘层10的表面的第二半导体芯片(半导体基板)3。第一半导体芯片(半导体基板)2与第二半导体芯片(半导体基板)3的贴合通过各种公知的贴合方法而实施。电容元件13的形成工序由于是仅对通常的贴合工序追加一次PEP与一次加工工序，因此能够减少电容元件13的制造成本。
具有图2所示的电容元件15的半导体装置1例如如图4所示那样制作。首先，与通常的贴合工序相同，准备露出了第一金属焊盘4、第二金属焊盘5、以及第一绝缘层6的表面的第一半导体芯片(半导体基板)2。在这种第一半导体芯片2的表面如图4的(A)所示那样形成掩模层18。接着，如图4的(B)所示，通过PEP根据第四金属焊盘5的形状将掩模层18的一部分去除而形成开口。通过根据掩模层18的开口将第二金属焊盘5的一部分蚀刻去除，如图4的(C)所示那样使第二金属焊盘5后退以形成空隙层14。另外，空隙层14可以在通过CMP使第一半导体芯片(半导体基板)2的表面平坦化时使第二金属焊盘5选择性地凹陷(dishing)而形成。
在具有这种空隙层14的第一半导体芯片(半导体基板)2上，如图4的(D)所示那样贴合露出了第三金属焊盘8、第四金属焊盘9、以及第二绝缘层10的表面的第二半导体芯片(半导体基板)3。第一半导体芯片(半导体基板)2与第二半导体芯片(半导体基板)3的贴合通过各种公知的贴合方法而实施。电容元件15的形成工序由于仅是在通常的贴合工序中追加一次PEP与一次加工工序或利用CMP工序的凹陷，因此能够减少电容元件15的制造成本。
另外，上述各实施方式的构成能够分别组合地应用，此外，也能够替换一部分。这里虽然说明了本发明的几个实施方式，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更等。这些实施方式及其变形包含在发明的范围、主旨中，同时包含在权利要求书所记载的发明及与其等效的范围内。

Claims (17)

1.一种半导体装置，其中，具备：
第一半导体芯片，具备第一金属焊盘和第二金属焊盘；以及
第二半导体芯片，具备与所述第一金属焊盘接合的第三金属焊盘、和隔着介电层而与所述第二金属焊盘对置配置的第四金属焊盘，所述第二半导体芯片经由所述第一金属焊盘和所述第三金属焊盘而与所述第一半导体芯片贴合。
2.根据权利要求1所述的半导体装置，其中，
所述第一半导体芯片具备第一半导体元件和第一布线层，该第一布线层的一端连接于所述第一金属焊盘以及所述第二金属焊盘的至少一方，并且另一端的至少一部分连接于所述第一半导体元件，
所述第二半导体芯片具备第二半导体元件和第二布线层，该第二布线层的一端连接于所述第三金属焊盘以及所述第四金属焊盘的至少一方，并且另一端的至少一部分连接于所述第二半导体元件。
3.根据权利要求1所述的半导体装置，其中，
所述第二金属焊盘与所述第四金属焊盘隔着作为所述介电层的绝缘层而对置配置。
4.根据权利要求1所述的半导体装置，其中，
所述第二金属焊盘与所述第四金属焊盘隔着作为所述介电层的空隙层而对置配置。
5.根据权利要求1所述的半导体装置，其中，
满足如下至少一个条件：
与所述第一半导体芯片以及所述第二半导体芯片平行的第一方向上的所述第二金属焊盘的长度比所述第四金属焊盘的所述第一方向上的长度长；以及
与所述第一方向交叉且与所述半导体芯片平行的第二方向上的所述第二金属焊盘的长度比所述第四金属焊盘的所述第二方向上的长度短。
6.根据权利要求5所述的半导体装置，其中，
所述介电层设于所述第二金属焊盘上。
7.一种半导体装置，其中，具备：
第一半导体芯片，具有与存储器电连接的第一金属焊盘、与第一布线电连接的第二金属焊盘、以及第三金属焊盘；以及
第二半导体芯片，包含一端与第一电路电连接且另一端与所述第一金属焊盘连接的第四金属焊盘、一端与第二电路电连接且另一端经由介电层而与所述第二金属焊盘连接的第五金属焊盘、以及与所述第三金属焊盘连接的第六金属焊盘，所述第二半导体芯片设于所述第一半导体芯片上。
8.根据权利要求7所述的半导体装置，其中，
所述介电层是绝缘层。
9.根据权利要求7所述的半导体装置，其中，
所述介电层是空隙层。
10.根据权利要求7所述的半导体装置，其中，
所述第三金属焊盘以及所述第六金属焊盘未与布线连接。
11.根据权利要求7所述的半导体装置，其中，
满足如下至少一个条件：
与所述第一半导体芯片以及所述第二半导体芯片平行的第一方向上的所述第二金属焊盘的长度比所述第五金属焊盘的所述第一方向上的长度长；以及
与所述第一方向交叉且与所述半导体芯片平行的第二方向上的所述第二金属焊盘的长度比所述第五金属焊盘的所述第二方向上的长度短。
12.根据权利要求7所述的半导体装置，其中，
所述存储器设置于相互分离地层叠的多个导电体与贯通所述多个导电体地设置的柱的交叉部。
13.根据权利要求12所述的半导体装置，其中，
所述多个导电体中的一个导电层电连接于所述第一金属焊盘。
14.一种半导体装置的制造方法，其中，具备如下工序：
在具备第一金属焊盘以及第二金属焊盘的第一半导体芯片的所述第二金属焊盘上形成绝缘层的工序；
在所述第一半导体芯片上，将具备第三金属焊盘以及第四金属焊盘的第二半导体芯片，以所述第一金属焊盘与所述第三金属焊盘对置、并且所述第二金属焊盘与所述第四金属焊盘隔着所述绝缘层而对置的方式进行配置的工序；以及
通过将所述第一金属焊盘与所述第三金属焊盘直接接合，从而将所述第一半导体芯片与所述第二半导体芯片贴合的工序。
15.一种半导体装置的制造方法，其中，具备如下工序：
使具备第一金属焊盘以及第二金属焊盘的第一半导体芯片的所述第二金属焊盘后退而形成空隙的工序；
在所述第一半导体芯片上，将具备第三金属焊盘以及第四金属焊盘的第二半导体芯片，以所述第一金属焊盘与所述第三金属焊盘对置、并且所述第二金属焊盘与所述第四金属焊盘隔着所述空隙而对置的方式进行配置的工序；以及
通过将所述第一金属焊盘与所述第三金属焊盘接合，从而将所述第一半导体芯片与所述第二半导体芯片贴合的工序。
16.根据权利要求14或15所述的半导体装置的制造方法，其中，
所述第一金属焊盘以及所述第二金属焊盘以表面露出的方式埋入于第一绝缘层内，所述第三金属焊盘以及所述第四金属焊盘以表面露出的方式埋入于第二绝缘层内，
通过将所述第一金属焊盘与所述第三金属焊盘接合并且将第一绝缘层与所述第二绝缘层接合，从而将第一半导体芯片与所述第二半导体芯片贴合。
17.根据权利要求14或15所述的半导体装置的制造方法，其中，
所述第一半导体芯片具备第一半导体元件和第一布线层，该第一布线层的一端连接于所述第一金属焊盘以及所述第二金属焊盘的至少一方，并且另一端的至少一部分连接于所述第一半导体元件，
所述第二半导体芯片具备第二半导体元件和第二布线层，该第二布线层的一端连接于所述第三金属焊盘以及所述第四金属焊盘的至少一方，并且另一端的至少一部分连接于所述第二半导体元件。
CN202010106894.8A 2019-09-17 2020-02-21 半导体装置及其制造方法 Active CN112530916B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-168887 2019-09-17
JP2019168887A JP2021048204A (ja) 2019-09-17 2019-09-17 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN112530916A true CN112530916A (zh) 2021-03-19
CN112530916B CN112530916B (zh) 2024-04-09

Family

ID=74868644

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010106894.8A Active CN112530916B (zh) 2019-09-17 2020-02-21 半导体装置及其制造方法

Country Status (4)

Country Link
US (2) US11437324B2 (zh)
JP (1) JP2021048204A (zh)
CN (1) CN112530916B (zh)
TW (1) TWI765220B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024007379A1 (zh) * 2022-07-07 2024-01-11 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11527501B1 (en) * 2020-12-15 2022-12-13 Intel Corporation Sacrificial redistribution layer in microelectronic assemblies having direct bonding
WO2023136170A1 (ja) * 2022-01-17 2023-07-20 ソニーセミコンダクタソリューションズ株式会社 半導体素子及び半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004146814A (ja) * 2002-09-30 2004-05-20 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
CN105190865A (zh) * 2013-03-25 2015-12-23 旭化成微电子株式会社 半导体装置及半导体装置的制造方法
CN107615481A (zh) * 2015-05-18 2018-01-19 索尼公司 半导体装置和成像装置
CN109698209A (zh) * 2017-10-24 2019-04-30 三星电子株式会社 堆叠互补金属氧化物半导体图像传感器
JP2019114595A (ja) * 2017-12-21 2019-07-11 ソニーセミコンダクタソリューションズ株式会社 半導体装置およびその製造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3018017B2 (ja) 1989-04-03 2000-03-13 猛英 白土 半導体装置及びその製造方法
JPH0621333A (ja) * 1992-07-03 1994-01-28 Seiko Epson Corp 半導体装置の製造方法
JPH06252347A (ja) * 1993-02-25 1994-09-09 Mitsubishi Electric Corp Ｍｉｍキャパシタ及びその製造方法
SG99939A1 (en) * 2000-08-11 2003-11-27 Casio Computer Co Ltd Semiconductor device
JP2003258107A (ja) * 2002-02-28 2003-09-12 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP5214169B2 (ja) * 2007-05-17 2013-06-19 ルネサスエレクトロニクス株式会社 半導体装置
JP2009105300A (ja) * 2007-10-25 2009-05-14 Panasonic Corp 半導体装置及びその製造方法
JP2009111013A (ja) * 2007-10-26 2009-05-21 Rohm Co Ltd 半導体装置
ES2785075T3 (es) * 2009-07-30 2020-10-05 Qualcomm Inc Sistemas en paquetes
JP2011082301A (ja) 2009-10-06 2011-04-21 Sony Corp 配線基板、その製造方法および電子機器
JP2011114233A (ja) 2009-11-27 2011-06-09 Sony Corp 積層配線基板とその製造方法
KR101046394B1 (ko) * 2010-02-03 2011-07-05 주식회사 하이닉스반도체 스택 패키지
JPWO2014184988A1 (ja) * 2013-05-16 2017-02-23 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9437572B2 (en) * 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
JP6235901B2 (ja) * 2013-12-27 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置
US9613994B2 (en) * 2014-07-16 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitance device in a stacked scheme and methods of forming the same
US9536848B2 (en) * 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
US9704827B2 (en) * 2015-06-25 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond pad structure
US10811388B2 (en) * 2015-09-28 2020-10-20 Invensas Corporation Capacitive coupling in a direct-bonded interface for microelectronic devices
JP2018152419A (ja) * 2017-03-10 2018-09-27 東芝メモリ株式会社 半導体記憶装置
TW201838111A (zh) * 2017-03-30 2018-10-16 台灣積體電路製造股份有限公司 整合扇出型封裝系統之耦合電容裝置
CN107658317B (zh) * 2017-09-15 2019-01-01 长江存储科技有限责任公司 一种半导体装置及其制备方法
CN110379790A (zh) * 2019-07-25 2019-10-25 武汉新芯集成电路制造有限公司 一种晶圆结构及其制造方法、芯片结构
JP2021043012A (ja) * 2019-09-09 2021-03-18 キオクシア株式会社 検査装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004146814A (ja) * 2002-09-30 2004-05-20 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
CN105190865A (zh) * 2013-03-25 2015-12-23 旭化成微电子株式会社 半导体装置及半导体装置的制造方法
CN107615481A (zh) * 2015-05-18 2018-01-19 索尼公司 半导体装置和成像装置
CN109698209A (zh) * 2017-10-24 2019-04-30 三星电子株式会社 堆叠互补金属氧化物半导体图像传感器
JP2019114595A (ja) * 2017-12-21 2019-07-11 ソニーセミコンダクタソリューションズ株式会社 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024007379A1 (zh) * 2022-07-07 2024-01-11 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

Also Published As

Publication number Publication date
US11437324B2 (en) 2022-09-06
US11942431B2 (en) 2024-03-26
CN112530916B (zh) 2024-04-09
US20210082823A1 (en) 2021-03-18
TW202114150A (zh) 2021-04-01
JP2021048204A (ja) 2021-03-25
TWI765220B (zh) 2022-05-21
US20220367371A1 (en) 2022-11-17

Similar Documents

Publication Publication Date Title
US11114414B2 (en) Wafer structure with capacitive chip interconnection, method for manufacturing the same, and chip structure with capacitive chip interconnection
CN112530916B (zh) 半导体装置及其制造方法
US8234606B2 (en) Metal wiring structure for integration with through substrate vias
US10199375B2 (en) Storage device and capacitor
CN110047911B (zh) 一种半导体晶圆、键合结构及其键合方法
JP2009277719A (ja) 半導体装置及びその製造方法
CN102132406A (zh) 包含应力松弛间隙以提升芯片封装交互作用的稳定性的半导体设备
US8143698B2 (en) Semiconductor device
CN113410246B (zh) 半导体存储装置
TWI808338B (zh) 半導體裝置
CN113363233B (zh) 半导体装置及其制造方法
US11450611B2 (en) Semiconductor device and method of manufacturing the same
US10276476B1 (en) Semiconductor device and method of forming the same
CN115621230A (zh) 芯片封装方法及半导体封装结构
CN113410244B (zh) 半导体存储装置
US20180122757A1 (en) Bonding pad structure having island portions and method for manufacturing the same
CN112530933B (zh) 半导体装置
CN110739396B (zh) 一种芯片结构、晶圆结构及其制造方法
CN112750839B (zh) 半导体装置
US20240203832A1 (en) Semiconductor device and semiconductor device manufacturing method
JP7222481B2 (ja) 半導体装置
US6977805B2 (en) Capacitor element, semiconductor integrated circuit and method of manufacturing those
JP3779288B2 (ja) 半導体装置
CN115732458A (zh) 半导体装置及衬底
TW202224161A (zh) 半導體裝置及其製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant