CN1117655A - 电镀的焊接端子 - Google Patents

电镀的焊接端子 Download PDF

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CN1117655A
CN1117655A CN95105061A CN95105061A CN1117655A CN 1117655 A CN1117655 A CN 1117655A CN 95105061 A CN95105061 A CN 95105061A CN 95105061 A CN95105061 A CN 95105061A CN 1117655 A CN1117655 A CN 1117655A
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layer
crcu
solder
metal
terminal
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CN1126170C (zh
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亨利(Iii)阿特金森·奈
杰弗里·弗雷德里克·罗德
童洪明
保罗·安东尼·托它
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International Business Machines Corp
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Abstract

公开一种改进的焊接端子的工艺及结构。该改进的焊接端子是由底金属粘附层、在粘附层顶上的CrCu中间层、在CrCu层上面的焊料键合层以及焊料顶层构成。一种制作改进的端子金属的工艺包括:淀积粘附金属层、在该粘附层上的CrCu层、及焊料键合材料层,在其上选定位置形成焊料层,用焊料区作掩模刻蚀下面的各层。

Description

电镀的焊接端子
本发明一般涉及微电子封装中所用的焊接互连线,特别涉及一种改进的焊接端的金属化。
在微电子学中,互连线一词常被用来描述一种把半导体、电容器或激光器一类有源器件电连接到陶瓷基片或有机板的结构或方法。称为硬或半永久性的一种互连线使用低熔点合金焊料。这与插针和插孔一类可动连接大不相同。
倒扣芯片接合是互连线焊接领域内的一主要分支。按倒扣芯片连接工艺,用焊球或焊柱使硅片上相应的端子与陶瓷基片或有机板接合,在陶瓷基片或有机板与电路化的硅片之间建立电学的和结构上的连接。在下面通篇论述中,“基片”一词用来代表硅芯片、陶瓷基片或有机板。焊球的材料通常形成在器件或者在基片的金属化端子上,有时在器件和基片的金属化端子上。对微电子而言,焊接端子的制作是一步重要的制造工艺过程。
在焊接互连要求不严格,轮廓较大(μm级)的大批焊接的应用中,可以采用浸渍、网印或喷涂焊接。在要求严格(变化小于20%)的应用中,焊料的体积和组成需加仔细控制,焊接端子是通过金属掩模和抗蚀胶掩模蒸发焊料或通过抗蚀胶掩模电镀焊料制作的。一般,可把基片上的焊接端子看作由两部分制成,一是称为端子金属化的金属化层,余者为接合材料(通常是焊料)本体。因为铅、铬、钼、钨一类的互连金属不适合用作器件或基片上的布线,一般要求单独的端子金属化,这是由于它们不易被浸润,也不与焊料按可控方式起化学反应。美国专利3,633,076给出一种焊接互连线,其中列出焊接端子金属化的要求,如电导率,粘附力/机械稳定性,易淀积与光加工,加工中的可焊性和材料稳定性。美国专利3,633,076还给出在半导体上使用三层金属化,以满足这些要求。这些要求至今依然有效,只不过对超大规模集成器件而言,又出现一些新的附加条件。某些新的条件是数量极大的端子(因输入/输出数目增加)精确的端子布置,高机械稳定性(如应力与粘附力)以及低缺陷程度。例如,已发现由于端子金属化的应力导致金属化下面绝缘薄膜裂缝的形成(Bhat-tacharya等人的美国专利4,434,434)。美国专利4,434,434给出,分层的端子金属化可减少在其下面的脆性绝缘薄膜形成裂缝。Herdzik等人(在IBM Technical Discloure Bulletin,P1979,Vol.10,No.12,May 1968)论述了使用以Cr、Mo、W覆盖的Al,来防止当焊料回流时Al与焊料形成合金。Leonard及Revitz(在IBMTechnical Disclosure Bulletin,P.1121,Vol.13,No.5,Oct.1970)论述了使用氧化铬与调相Cr—Cu层配合作为用于焊接端子的阻挡层。Dalal和Jaspal(在IBM Technical Disdosure Bulletin,P.1005,Vol.20,No.3,Aug.1977)描述了通过蒸发共淀积Cr和Cu形成调相Cr—Cu层的工艺。该Cr—Cu调相层包括机械互锁的Cr和Cu颗粒,显示出对下面的Cr层和上面的钼与铜的中间金属层具有很好的粘附力。Gardner(美国专利No.4,840,302)给出了使用Cr—Ti合金代替单一的Cr或Ti,作为与其上形成端子的有机绝缘层的粘附层。美国专利4,840,302发明请求保护减少在有机绝缘层上形成焊接端子时的界面裂痕。
还有另一种专门关于制造焊接端子工艺的教导。Kawanobe等人的评论文章(“Solder Bump Fabricalion by ElectrochemicalMethod for Flip Chip Interconnection”,CH1671—7 IEEE,1981,PP.149—155)综述了几种替代的形成焊块和下层金属化的方法。美国专利No.5,162.257(授予Edward K.Yung)给出了制作焊块的工艺。在美国专利No.5,162,257工艺中,在最顶层是刻成图形的焊料屏障层(如铬)的基片上形成铺垫金属层(包括铜)(焊料屏障是使焊料熔化也不浸润的一种材料)。在基片上形成焊料聚集区,使焊料回流与未被焊料屏障层覆盖的铜起反应。接着用焊料和金属互化物层作刻蚀掩模,刻蚀掉焊料屏障层和其它金属化层。美国专利No.5,268,072(转让给本发明的授让人)给出了湿、干结合刻蚀方法形成分层的或边缘轮廓有台阶的三层金属化Cr/Cr—Cu/Cu。
上面评论的每个已有技术意在提供解决在焊料制作和使用上所遇到的特定问题的一种方法。但似乎没有一种办法普适各种不同的应用。这是因为,即使大多数互连端要求对所有使用是共同的,但还有对每种使用是独特的要求。而且十分明显,焊接端子的形成技术是不容易预测的,为确认金属化或工艺中的任何变化往往要求实验证明。本发明的主要目的在于达到更高的产生率,改进焊接端子的可靠性,同时开拓工艺,以低成本在大基片(200mm硅片)上形成更小的更大量的焊接端子。从下面在详细说明部分的具体论述更加明了许多先前的发明不能充分满足本发明的主要目的。
本发明的一个目的在于提供一种互连焊接端子结构及其改善产额和可靠性的制作工艺。
本发明的进一步的目的在于提供一种低成本的可用于大基片的制作工艺。
本发明的更深一层的目的在于改善工艺与包括由薄Al—Cu、Cu线制成的多层布线和薄钝化层的基片的兼容性。
公开一种改善焊接端子的工艺和结构。改善的焊接端子是由一底金属粘附层、在该粘附层顶上的CrCu层、在CrCu层上面的焊接层及焊料顶层组成的。该粘附层是TiW或TiN。制作改善的端子金属的工艺包括:淀积一粘附金属层,在该粘附层上的CrCu层及焊接材料层,在其上的选定区内形成焊料层,并用焊料区作掩模刻蚀下面的各层。
从下面以附图解释的本发明更具体的描述会更加明了本发明的目的、特性及优点。
图1显示采用倒扣互连的微电子组合件的视图。
图2表示图1所示的具有多个焊接端子的半导体芯片的扫描电子显微照片。
图3表示图2所示半导体芯片上焊接端子的剖面图。
图4A和4B显示两个采用焊接端子的不同基片构成的剖面图,并示出了在焊接端子蚀刻过程需要保护的基片区。
图5是解释本发明工艺步骤的流程图。
图1表示一种采用倒扣芯片互连的组合件(组件),其中的半导体芯片30,借助于多个焊块40与陶瓷基片10电连接和物理接合。焊块40的一端连到芯片30的金属端子上,另一端连到基片10的金属端子上。焊块40已被回熔,以便在芯片30和陶瓷基片10上的焊料和金属端子之间建立熔炼键合。一般,在接合之前,预制焊料作为芯片30或基片10或两者的整体部件。在另一些类型的互连中,基片上的端子是预焊的,并通过TAB(带自动键合)连线接合。在某些情况下,采用回熔焊接作为热连接,用以把芯片的背面固定到陶瓷基片上,并通过TAB或丝焊键合建立电连接。尽管本文没作具体解释,但这里所作的论述同样适用于陶瓷格点阵列、带状球格点阵列及类似的阵列。本文综合考虑在半导体芯片30上焊块的形成来解释本发明的特性,但应予理解对上述其它应用可作基本相同的论述。
图2表示半导体芯片30表面上的多个焊料端子或焊块50。焊块50的位置、数量及大小一般由芯片和陶瓷基片的设计要求、组件的可靠性及焊接端子工艺限制来确定。目前在VLSI压力封装中所用的互连总数大约是1000,预计还会增加。所以,要求单个端子焊盘的可靠性十分高。
图3表示芯片上的焊块的某些关键性部件,称为C4(受控可拆芯片连接)(见P.A.Totta and R.P.Sopher,IBM Journal Re-search and Development,May 1969,pp.226—238)。图3将被用于评论现有技术某些突出的特性,及强调本发明的关键实施方案。半导体芯片30这里包括至少一层布线60,它被一薄绝缘层70所绝缘和钝化。在绝缘层70形成一通到下层布线60的孔75或通路,对应于预定的焊块端子的位置。在现有技术中,层80是由近似1000的Cr制成,提供与绝缘层70的粘附性,同时通过孔75形成到层60的电连接。在图3中,孔75被表示成一通路,然而在许多应用中,它可用通过网印焙烧在陶瓷基片中的金属膏或通过电镀塑料或陶瓷板中的孔制成的导电接触(未图示)来代替。层90一般是5000—10000的铜或镍或其它合适的可焊材料,当焊料加热时与焊料反应形成熔炼键合。中间层85一般是1500的调相的Cr—Cu,形成于层80和90之间,若需要,提供层90和层80之间的粘附力。在层90上有时形成层100,由约1000的Au组成,为防止在淀积焊料层120之前的贮存和操作过程中Cu表面的氧化。层120,焊料,一般含有一种或一种以上的pb、Bi、Sb、Sn、In、Ag、Au。当加热熔化焊料(回熔)时,Cu层90与焊料层120的至少一种组分反应,形成金属间化合物(未图示),诸如CuSn、CuIn及CuSb等。Cu与焊料间的熔炼反应(称为浸润)将一部或整个Cu层90转变为金属互化物。该金属互化物的实际组分由在能量上有优势的化合物确定。元素的相图,例如Cu和Sn含有可形成金属互化物的信息。二元系相图在相图书中是现成的。当检修组件,使焊料经多次回熔时,Cu—Sn金属互化物(未图示)长厚,变得粗糙而不连续。有些金属互化物弥散到焊料中,被(Berry and Ames,IBM J.Res.Development,May1969,PP.286—296)称为“解消辅助散裂”。Berry和Ames观测到,“预防焊料去湿在很大程度上依赖于那些最终防止和抑制散裂的工艺因素。这些因素是在采用调相的Cr—Cu生产中选定的最佳参数”。保护层100在接合过程中完全耗尺,并形成金属间化合物,一般又弥散在焊块中。
特定层具体厚度的选择、各层顺序的安排及淀积和模式工艺的选取可按宽范围的先前论述过的要求,诸如工艺兼容性、膜的应力、层间粘附力等来确定。同时,从现有技术选出的模式工艺是有限的,而且强加许多额外的限制。
本发明使用下列工艺步骤的结合,诸如:淀积铺垫层、掩蔽和光刻、在选定面积附加焊料以及刻蚀铺垫层,以实现可扩展至大晶片小端子特性的低成本制造工艺。端子的厚度和刻蚀工艺对不同层是经选择和优化的,以改善产额和可靠性。另外,本发明的焊接端子的工艺和结构是经选择的,以确保各层和不同工艺间的兼容性。本发明所要克服的具体问题是当使用现有技术以上面的焊料轮廓作掩模刻蚀金属化层时所见的残留缺陷和产量低下。例如,美国专利No.5,268,072给出了电刻蚀CrCu合金属和Cu键合层。在本申请本体中所用的“CrCu层”一词包括含Cr和Cu原子的所有膜,不管它们是由合金靶淀积的,还是由两个分开的源以相位法共蒸发的。Cr-Cu合金一词按其定义包括调相的Cr—Cu层。按美国专利No.5,268,072的工艺焊料加到选定位置的金属端子上。使用焊块作掩模,电解刻蚀Cu和CrCu层。在美国专利No.5,268,072的工艺中对CrCu层的电解刻蚀也刻蚀了下面的Cu层。工艺的非均匀性和每次投料的变化往往导致在CrCu层完全刻蚀掉之前,部分刻蚀了Cr层。在电刻蚀CrCu层过程中作为电通路的Cr层变得不连续,因此妨碍了CrCu层的完全去除,并导致产量低下。全部电刻蚀工艺的可行性低下。
基于上面的论述,本发明者考虑到一种选择、制作金属端子的新的工艺/材料条件。采用图3描述如下:去除顶金属化层无用部位形成层85和90的选择刻蚀工艺不应刻蚀下面的粘附层80。这一要求可以通过开发一种新的刻蚀工艺或采用一种新的材料代替图3中的层80的Cr。然而,新材料的选取要求说明,该新的粘附层80与阻挡层85和焊接键合层90相结合可以满足先前论述的许多相互关联的要求。本发明者进一步考虑到好的生产工艺的另一要求,即,用于刻蚀图3粘附层80的工艺一定不能再刻蚀在基片30一些区域露出的布线层60。借助于图4A和4B,对这一点会有更深的理解。
图4A表示在基片200上的一通路接触孔215和一金属端子,包括一粘附层240、任选键合层260和可焊层280,以及一焊料层300。联系到先前的论述,层240可以是Cr,层260可以是CrCu,而层280可以是Cu或Ni。图4A还表示一故意的开孔216通至基片内隐埋的布线层210。孔216是一故意露出的接触,通过除倒扣芯片互连之外的技术,如丝焊、TAB等或探测在“切槽”区的器件,用于连接到布线层210。在图4A中还表示一个由缺陷218引起的不注意的孔,露出部分隐埋布线210。缺陷218可以是一针孔、一刻蚀或淀积缺陷。图4B与图4A类似,只是端子利用柱状接触215′代替了通路接触215。在柱状接触工艺中,采用金属淀积来填充接触孔。在故意孔的情况下,露柱状的表面216′,在缺陷218的情况下,形成有缺陷的连接218′。在某些半导体芯片中包括故意孔,可以灵活地使用不同内互连和与不同的基片一起使用。
在基片顶层存在这些故意孔和非故意孔的情况下,本发明者考虑到,金属化层240的选择用来去掉层240的无用部位的工艺必须是“兼容的”,即对层210是无反应的和无刻蚀的。否则,在制造环境中,去除层240的无用部位的刻蚀步骤可导致部分或全部腐蚀故意孔和缺陷孔内的布线210。部分腐蚀可引起可靠性下降,而完全腐蚀可导致产量下降。这种利害关系是现有技术没有顾及到的,也不能用现有技术解决。例如,美国专利No.5,162,257给出了用金属化层Cr,调相的Cr—Cu及Cu形成焊块,用氢氯酸基腐蚀剂(栏6,行24—26)刻蚀Cr—Cu和Cr层。众所周知,氢氯酸基腐蚀剂强烈腐蚀露出的Al表面,这使得该教导不易适合在Al布线的基片上大规模地制作焊接端子。本发明者已认识到,对于高产额的制作工艺,用于腐蚀图4A的金属端子粘附层240的工艺必须与(即不腐蚀)隐埋布线层210兼容。为了将下面的绝缘层裂纹所诱导的应力减至最小,调整刻蚀条件和化学物品不总是容易的,因为特定的腐蚀条件是控制刻蚀的金属化层的几何形状(递变截面构形)所要求的。
通过以流程图表示工艺步骤的图5,结合图3所示的剖面图,可以理解本发明的优选实施例。第一步505,包括在具有顶绝缘层70和接触区75的基片30上淀积一层或一层以上的铺垫金属化层。当在后一工艺步骤从上述的铺垫层去掉无用部位时,形成图3的层80和85。在最实际的情况下,基片30应有数个接触区75。在优选的工艺中,由一合金靶溅射TiW层,作为一铺垫层,在后一工艺步骤经选择刻蚀,形成图3的层80。TiW淀积后,接着由CrCu合金靶溅射淀积一CrCu层,从Cu靶溅射淀积Cu层,在后一工艺步骤选择刻蚀Cu和CrCu层,分别形成图3中层90和95。CrCu层也可以用其它工艺淀积,如由二元靶共溅射由两个蒸发源的共蒸发。不管使用什么工艺,所得之膜是晶粒互锁物理混合的Cr和Cu晶粒的混合物。在本申请中,可用TiN层作为TiW层的代替层。这是因为TiN类似TiW,对绝缘体的很好的粘附力,对微电子应用中所用的金属化又是很好的扩散阻挡层。用含氟—碳的物质等离子体可刻蚀TiN和TiW,而不蚀蚀Al、Cu、或Pb—Sm。当使用氟—碳等离子体来刻蚀时,在Pb—Sn层120上形成氟化的表面层是个严重问题,可能要求附加的处理步骤,以便在焊接互连过程之前或当中去掉氟化物。再有,采用氟—碳的反应离子刻蚀工艺要求严密的工艺控制和均匀性,因该工艺能刻蚀图3下面的绝缘层70。绝缘层70厚度损失太多,对许多应用是不可接受的。在优选工艺中,图3的绝缘层70是聚酰亚胺,其化学组分是PMDA—ODA(1,2,4,5—苯四酸二酐氧化双苯胺),但适合作微电子应用的绝缘层的任何化学组成的有机材料均可用作层70。此外,通过物理、热及PECVD工艺所淀积的二氧化硅、氮化硅及氮氧化硅一类的无机绝缘物也可用作层70。
TiW层80厚度可在250—2000的范围。在某些应用中,在淀积TiW之前,先剥蚀基片,以确保低电阻及高粘附力。溅射靶中钨的含量一般约为90%,但也可在60—90%,余量是Ti。CrCu层85的厚度在100—2000。CrCu层85的组分是Cr含量在20—80%,余量为Cu。在优选实施例中,TiW溅射靶含90%的W,而Cr-Cu溅射靶含体积相等的Cr和Cu。虽然溅射是优选工艺,图3中的层80和85,在腐蚀前自然就是铺垫层,但也可采用电镀、蒸发、CUD一类的其它工艺。
在淀积TiW和CrCu层后,两种工艺之一均可用来淀积铜。按其中的一种工艺510,通过抗蚀胶或金属掩模淀积,在CrCu层顶上形成有图形的Cu层。另一办法是通过淀积一层铺垫层并采用抗蚀掩模刻蚀,同样可获得有图形的Cu层。这种如步骤510中的Cu构图方法与流程图5的优选步骤515相比,其工艺步骤太多。按步骤515,最好用铜靶溅射淀积相应于图3中的层90的铜层作为铺垫层。铜的厚度在1000—2μm范围,依应用而定。在优选实施例中,铜的厚度采用4300。另一办法是采用以可焊性而著称的镍或钻层代替铜层,形成图3中的层90。在我们的实验中,采用一串联的带有多个靶的溅射系统MRC662,单一抽气,依次淀积TiW、CrCu和Cu层。接着,如工艺步骤520所示,形成带有与焊接端子位置相应的孔的绝缘掩模层。在优选实施例中,该掩模是由负性干膜抗蚀胶制成。也可使用其它掩模材料,诸如正性抗蚀胶、及聚合物、氧化硅、氟化物及其混合物一类的绝缘物。在优选工艺中,Pb—3Sn焊料合金是通过绝缘掩模层的孔电镀上的,基本上填平,如有要求,填过孔的体积。电镀工艺使用公知的电镀配方和电镀设备,还使用绝缘掩模层下面的铺垫金属化层TiW、CrCu和Cu,为电镀运行提供电通路。另一些所需的焊料组分,如易熔的Pb—Sn、Pb—In、Pb—In—Sn等可用工业上公知的工艺电镀。这样,在步骤520,按孔的位置将焊料选择加到基片上,形成图3的层120。在电镀形成焊料后,在步骤520,用湿或干腐蚀去掉掩模。在有机抗蚀胶的情况下,采用在O2中灰化去掉掩模。
在步骤525,从焊区之外的区域去掉铺垫键合层Cu、Ni或Co及中间层CrCu及底粘附层TiW或TiN或类似物的无用区,形成图3的各层90、85、80。在优选工艺中,首先按美国专利No.5,268,072(转给本发明的受让人)的教导,用硫酸钾电刻蚀Cu和Cr-Cu层。本发明者已发现,该优选实施例的TiW层80未被用来去掉露出区域中的Cu和CrCu层的电刻蚀工艺腐蚀。这就允许TiW铺垫层为电刻蚀(及某些过刻蚀)下面的层Cu和CrCu提供电流通路,形成层90和85,不一点残留物。在步骤525,在形成CrCu层85和Cu层90之后,接着如美国专利No.4,814,293的教导,通过H2O2缓冲混合液化学腐蚀TiW铺垫层。在优选工艺中,使用H2O2、EDTA和钝化剂的混合液。这种腐蚀剂选择去掉TiW,而明显地不腐蚀Cu、Al和CrCu层。
从而,已表示了以相互兼容和可靠方式用来形成本发明实施例的包括作为底粘附层的TiW或TiN 80、CrCu中间层85及Cu键合金90的多层金属化结构的可行的工艺步骤。然而,仍需确定各选择层相互间及与绝缘层间形成良好的界面。需要完全三层和整个互连的结构完善性的实验证明,以便最终肯定本发明的实用性。互连结构良好的机械完善性确保做到材料的良好选择及工艺的良好选择。确保焊接端子结构完善性的粘附性的可行技术是抗拉伸测试。在抗拉伸测试中,通过焊料互连将芯片与基片接合,如图1,再将芯片和基片机械拉开。当测试正常运行时,分离将发生在焊料互连的某一部分。若因焊料的延展形变使分离发生在焊料体块内,可以推断金属化层与芯片或基片上的绝缘层之间界面是完美无缺的。在金属化的某一层当中或从绝缘层表面分离,则指明结构完善性差。在测试前在非氧化气氛中让互连经受多次反复回熔(让焊料熔化)可使拉伸测试做得更带攻击性。
表1列出了互连经受30次回熔的拉伸测试的结果,其中的芯片端子是用本发明形成的,TiW、CrCu及Cu各具有不同的厚度。表1的结果包含以各种金属化层厚度组合进行拉伸测试的芯片实际数量、每种等级的芯片平均抗拉强度及表明界面已脱层的焊块数量。
表1               拉伸结果
TiW/Cr-Cu/Cu/pb-3Sn(30次循环回熔后)
  实验号 TiW      Cr-Cu        Cu                    测试的芯片数     拉力(磅) 焊料脱层数(每400焊盘)
    12345678 812       1187       3150812        562       3150625        875       4300437       1187       3725437        250       3725812       1500       4300437       1187       3725250       1500       2575     33333333     20.218.420.121.119.721.821.919.9     0850012000
对应于250的CrCu和562的CrCu都表明拉伸强度减弱。某些界面失效。因测试芯片数仅三片,实际价值尚不算明显。然而,我们可以推断,对较薄的CrCu在拉伸测试中有界面失效的趋势。这暗示在没有一定厚度的CrCu层的情况下,焊块将导致TiW反浸润,一种公知的氧化,自钝化膜。在测试前经受30次回熔的互连,给出的界面失效数目尚不坏。由此设想到TiW与CrCu层之间的粘附是完美无缺的,有限的失效或许是由于较薄的CrCu层经30次回熔而退化所致。应该指出对于阻止散裂,合金CrCu层似乎是等效于同相的CrCu层。这进一步提示,对于大多数应用,当回熔次数大约在10次以下,即使250CrCu中间层也是可接受的。然而,由于相同的原因,没有中间的CrCu层,5000量级的薄Cu层直接设在TiW上,可能导致界面的脱层,因为铜转变为Cu—Sn金属互化物,而金属互化物散裂到焊料体块中。所以,图3的中间层85起到一种独特的作用,尽管它很薄。结构联锁的Cu颗粒确保Cu—Sn金属互化物与一侧的CrCu层间的粘附力,而Cr颗粒和联锁的Cu—Sn颗粒确保与另一侧的TiW的良好粘附力。从实验研究(“Reli-ability improvements in Solder bump processing for flip chips”,M.Warrior,1990 IEEE,0589—5503 pp.460—469)推出同样的结论。Warrior的研究使用一由TiW和Cu电镀焊料的互连作金属化层,没有中间层。将互连与基片接合,并做拉伸测试。该研究在上述参考文献的第461页陈述“因粘附力主要依赖于良好的Cu—Ti结构键合,任何一点疏漏都是一种潜在的凸块脱落的失败。研究的做法是在Cu溅射前让TiW表面暴露于大气。这是由重复同样的失败原因而得出的…”。在Warrior的研究中,所用的铜层厚是约10000(参见文献第460页的图1),在接合过程中,互连经受一次焊料熔化循环。合理的结论是,在接合之后,仍保持着Cu—Ti界面。所以关切的界面是在Cu产与Ti—W层的富Ti表面之间,看来似乎很敏感。从这些论述及表1中的数据,对采用薄键合层的大多数微电子应用而言,如本发明所预见,使用没有中间层的TiW和Cu不会满足本发明提及的成品率和可靠性方面的要求。因而,本发明的在TiW层80和Cu(Ni)层90之间使用一薄的CrCu中间层85提供了一种重要的解决办法。CrCu经多次回熔仍作为中间层存在,并提供与下面的TiW层的良好粘附力,如测试结果所示。
根据前面的论述,如图3所示的金属端子可使用下列的任何材料:TiN、Ti/TiN、Ti/TiW和Ti/W以及类似的材料,形成粘附层80以及CrCu中间层85。然而,在刻蚀CrCu层85的工艺中不应刻蚀粘附层80,这暗示着任何含Cr或Cu的层不可能适合作层80。在叠层结构如Ti/W的情况下,Ti提供与基片的粘附力。另外根据对粘附力的机械学论述及键合层的有限作用,可以采用镍、钴一类的材料加添到键合层90的Cu中。在使用由Ti/W、Ti/TiW、Ti/TiN等制成的叠层结构的情况下,氟基等离子体可用于刻蚀这些层,形成层80;此外,湿式刻蚀技术是合用的,且优先于隐埋布线层60。
虽然根据单一优选实施例描述了本发明,但对本领域的技术人员,在不脱离本发明的前提下可以作出各式各样的替换及改形。所以,本发明意欲包含所有的落入所附权利要求范围内的这种替换。

Claims (21)

1.一种改进的基片上的焊接端子,含有至少一个导电部件并具有多个被绝缘物隔开的电接触区,该焊接端子包括:
一金属粘附层,可用一种优先于所说的导电部件的工艺刻蚀;
在上面的、与所说的粘附层接触的一CrCu合金层;
所说的刻蚀金属粘附层的工艺进一步优先于所说的CrCu合金层;
在上面的、与所说的CrCu层接触的一焊料键合金属层;以及
在上面的、与所说的焊料键合层接触的一焊料层。
2.如权利要求1的一种改进的焊接端子,其特征在于,所说的金属粘附层是选自实质上由TiN和TiW组成的集合。
3.如权利要求1的一种改进的焊接端子,其特征在于,所说的金属粘附层是由两层制成的,一Ti底层和一选自实质上由TiN和TiW及W组成的集合的顶层。
4.如权利要求1的一种改进的焊接端子,其特征在于,所说的金属粘附层的厚度在250—2000的范围内。
5.如权利要求1的一种改进的焊接端子,其特征在于,所说的金属粘附层最好为约1000A。
6.如权利要求1的一种改进的焊接端子,其特征在于,所说的顶绝缘层是选自实质上由聚酰亚胺、二氧化硅、氮化硅及氮氧化硅组成的集合。
7.如权利要求1的一种改进的焊接端子,其特征在于,所说的焊料是选自实质上由Pb—Sn、Pb—In及Pb—Si组成的集合。
8.如权利要求1的一种改进的焊接端子,其特征在于,所说的CrCu层的厚度大于250。
9.如权利要求1的一种改进的焊接端子,其特征在于,所说的CrCu层是由20—80%的铜制成的。
10.如权利要求1的一种改进的焊接端子,其特征在于,所说的焊料键合层是选自实质上由Cu、Co和Ni组成的集合。
11.如权利要求1的一种改进的焊接端子,其特征在于,所说的焊料键合层的厚度选在1000—2μm的范围。
12.一种在基片上制作改进的焊接端子的方法,该端子含有至少一个导电部件并具有多个被绝缘物隔开的电接触区,该方法包括:
淀积一粘附金属层;
在所说的粘附金属层上面并与之接触淀积一层CrCu合金;
所说的粘附金属层之特征在于可优先于所说的导电部件和所说的CrCu合金属被刻蚀;
在所说的CrCu层上面并与之接触淀积一层焊料可键合的金属;
在所说的焊料可键合层上面在选定位置有选择地形成焊料;
使用所说的焊料作掩模刻蚀所说的焊料可键合层和CrCu层,停在所说的粘附层;以及
采用一种工艺,优先于基片上的焊料、CrCu合金层、焊料键合层及导电部件刻蚀所说的金属粘附层。
13.一种如权利要求12的方法,其特征在于,所说的粘附金属层是选自实质上由TiW和TiN组成的集合。
14.一种如权利要求12的方法,其特征在于,所说的粘附金属层是由两层制成的,一底Ti层,及一选自实质上由TiN、TiW及W组成的集合的顶层。
15.一种如权利要求12的方法,其特征在于,所说的粘附金属层是由选自溅射、化学汽相淀积及电镀的一种工艺形成的。
16.一种如权利要求12的方法,其特征在于,所说的CrCu合金层是由含Cr和Cu的合金靶溅射而淀积的。
17.一种如权利要求12的方法,其特征在于,所说的CrCu合金层是由Cr靶和Cu靶共溅射而形成的。
18.一种如权利要求12的方法,其特征在于,所说的CrCu合金层是由一Cr源和一Cu源共蒸发而形成的。
19.一种如权利要求12的方法,其特征在于,所说的焊料是通过有孔的绝缘掩模层电镀而形成的。
20.一种如权利要求12的方法,其特征在于,所说CrCu合金层及焊料键合层是通过电刻蚀工艺刻蚀的。
21.一种如权利要求12的方法,其特征在于,所说的粘附层是通过采用湿式化学反应或一等离子体的工艺刻蚀的。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7040014B2 (en) 2003-01-21 2006-05-09 Tdk Corporation Method of producing a helical coil chip
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Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10501376A (ja) * 1995-03-20 1998-02-03 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 銀・アルミニウム結合層を用いてスラグに連結された半導体本体を含んで構成されるガラス中に封止された型の半導体装置
EP0815593B1 (en) * 1995-03-20 2001-12-12 Unitive International Limited Solder bump fabrication methods and structure including a titanium barrier layer
KR100327442B1 (ko) * 1995-07-14 2002-06-29 구본준, 론 위라하디락사 반도체소자의범프구조및형성방법
US5736456A (en) * 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5903058A (en) * 1996-07-17 1999-05-11 Micron Technology, Inc. Conductive bumps on die for flip chip application
KR100239695B1 (ko) * 1996-09-11 2000-01-15 김영환 칩 사이즈 반도체 패키지 및 그 제조 방법
US5902686A (en) * 1996-11-21 1999-05-11 Mcnc Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures
US5759910A (en) * 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US5956573A (en) * 1997-01-17 1999-09-21 International Business Machines Corporation Use of argon sputtering to modify surface properties by thin film deposition
US5904859A (en) * 1997-04-02 1999-05-18 Lucent Technologies Inc. Flip chip metallization
US5952716A (en) 1997-04-16 1999-09-14 International Business Machines Corporation Pin attach structure for an electronic package
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
KR100219806B1 (ko) * 1997-05-27 1999-09-01 윤종용 반도체장치의 플립 칩 실장형 솔더 범프의 제조방법, 이에 따라 제조되는 솔더범프 및 그 분석방법
US6082610A (en) * 1997-06-23 2000-07-04 Ford Motor Company Method of forming interconnections on electronic modules
DE19746893B4 (de) * 1997-10-23 2005-09-01 Siemens Ag Optoelektronisches Bauelement mit Wärmesenke im Sockelteil und Verfahren zur Herstellung
US6020636A (en) * 1997-10-24 2000-02-01 Eni Technologies, Inc. Kilowatt power transistor
US6015505A (en) * 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US6051879A (en) 1997-12-16 2000-04-18 Micron Technology, Inc. Electrical interconnection for attachment to a substrate
US6251528B1 (en) 1998-01-09 2001-06-26 International Business Machines Corporation Method to plate C4 to copper stud
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
JPH11340265A (ja) 1998-05-22 1999-12-10 Sony Corp 半導体装置及びその製造方法
JP2943805B1 (ja) * 1998-09-17 1999-08-30 日本電気株式会社 半導体装置及びその製造方法
MY139405A (en) * 1998-09-28 2009-09-30 Ibiden Co Ltd Printed circuit board and method for its production
SE512906C2 (sv) * 1998-10-02 2000-06-05 Ericsson Telefon Ab L M Förfarande vid lödning av ett halvledarchip samt RF-power transistor för genomförande därav
JP4564113B2 (ja) * 1998-11-30 2010-10-20 株式会社東芝 微粒子膜形成方法
US6248958B1 (en) 1998-11-30 2001-06-19 International Business Machines Corporation Resistivity control of CIC material
US6232212B1 (en) * 1999-02-23 2001-05-15 Lucent Technologies Flip chip bump bonding
US6133136A (en) * 1999-05-19 2000-10-17 International Business Machines Corporation Robust interconnect structure
US6332988B1 (en) 1999-06-02 2001-12-25 International Business Machines Corporation Rework process
US6544880B1 (en) * 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
US6335495B1 (en) 1999-06-29 2002-01-01 International Business Machines Corporation Patterning a layered chrome-copper structure disposed on a dielectric substrate
FR2799578B1 (fr) * 1999-10-08 2003-07-18 St Microelectronics Sa Procede de realisation de connexions electriques sur un boitier semi-conducteur et boitier semi-conducteur
KR100311975B1 (ko) * 1999-12-16 2001-10-17 윤종용 반도체소자 및 그 제조방법
EP1259103B1 (en) * 2000-02-25 2007-05-30 Ibiden Co., Ltd. Multilayer printed wiring board and method for producing multilayer printed wiring board
US6293457B1 (en) * 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
US6605534B1 (en) 2000-06-28 2003-08-12 International Business Machines Corporation Selective deposition of a conductive material
JP2002050647A (ja) * 2000-08-01 2002-02-15 Sharp Corp 半導体装置及びその製造方法
EP1321980A4 (en) * 2000-09-25 2007-04-04 Ibiden Co Ltd SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, MULTILAYER PRINTED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING MULTILAYER PRINTED CIRCUIT BOARD
TW490821B (en) * 2000-11-16 2002-06-11 Orient Semiconductor Elect Ltd Application of wire bonding technique on manufacture of wafer bump and wafer level chip scale package
US6462426B1 (en) * 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
US6539625B2 (en) 2001-01-11 2003-04-01 International Business Machines Corporation Chromium adhesion layer for copper vias in low-k technology
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6894399B2 (en) * 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US20020167804A1 (en) * 2001-05-14 2002-11-14 Intel Corporation Polymeric encapsulation material with fibrous filler for use in microelectronic circuit packaging
US7071024B2 (en) * 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
CN100444365C (zh) * 2001-05-24 2008-12-17 弗莱氏金属公司 热界面材料
US7187083B2 (en) * 2001-05-24 2007-03-06 Fry's Metals, Inc. Thermal interface material and solder preforms
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
KR20030058627A (ko) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 반도체 소자의 제조 방법
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6715663B2 (en) * 2002-01-16 2004-04-06 Intel Corporation Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method
KR100455678B1 (ko) * 2002-02-06 2004-11-06 마이크로스케일 주식회사 반도체 플립칩 패키지를 위한 솔더 범프 구조 및 그 제조방법
JP3829325B2 (ja) 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
US6622907B2 (en) * 2002-02-19 2003-09-23 International Business Machines Corporation Sacrificial seed layer process for forming C4 solder bumps
US20030219623A1 (en) * 2002-05-21 2003-11-27 Kao Cheng Heng Solder joints with low consumption rate of nickel layer
JP2003347742A (ja) * 2002-05-27 2003-12-05 Hitachi Ltd 多層回路基板とその製造法及び多層回路用基板並びに電子装置
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
TW558782B (en) * 2002-09-10 2003-10-21 Siliconware Precision Industries Co Ltd Fabrication method for strengthened flip-chip solder bump
US7098074B2 (en) * 2002-11-13 2006-08-29 Tessera, Inc. Microelectronic assemblies having low profile connections
US6951775B2 (en) * 2003-06-28 2005-10-04 International Business Machines Corporation Method for forming interconnects on thin wafers
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US7276801B2 (en) 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
US20050085062A1 (en) * 2003-10-15 2005-04-21 Semitool, Inc. Processes and tools for forming lead-free alloy solder precursors
US7144490B2 (en) * 2003-11-18 2006-12-05 International Business Machines Corporation Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer
US7261841B2 (en) * 2003-11-19 2007-08-28 E. I. Du Pont De Nemours And Company Thick film conductor case compositions for LTCC tape
KR100604334B1 (ko) * 2003-11-25 2006-08-08 (주)케이나인 플립칩 패키징 공정에서 접합력이 향상된 플립칩 접합 방법
US7541275B2 (en) * 2004-04-21 2009-06-02 Texas Instruments Incorporated Method for manufacturing an interconnect
US8067837B2 (en) * 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US7731812B2 (en) * 2004-10-19 2010-06-08 E.I. Du Pont De Nemours And Company Thick film conductor case compositions for LTCC tape
US7087521B2 (en) * 2004-11-19 2006-08-08 Intel Corporation Forming an intermediate layer in interconnect joints and structures formed thereby
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
EP1732116B1 (en) * 2005-06-08 2017-02-01 Imec Methods for bonding and micro-electronic devices produced according to such methods
US7622309B2 (en) * 2005-06-28 2009-11-24 Freescale Semiconductor, Inc. Mechanical integrity evaluation of low-k devices with bump shear
DE102005035772A1 (de) * 2005-07-29 2007-02-01 Advanced Micro Devices, Inc., Sunnyvale Technik zum effizienten Strukturieren einer Höckerunterseitenmetallisierungsschicht unter Anwendung eines Trockenätzprozesses
TW200709359A (en) * 2005-08-31 2007-03-01 Advanced Semiconductor Eng Wafer structure
JP2007157504A (ja) * 2005-12-05 2007-06-21 Matsushita Electric Works Ltd マイクロリレー
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
JP2008262953A (ja) * 2007-04-10 2008-10-30 Sharp Corp 半導体装置の製造方法
US8304909B2 (en) * 2007-12-19 2012-11-06 Intel Corporation IC solder reflow method and materials
US8169081B1 (en) 2007-12-27 2012-05-01 Volterra Semiconductor Corporation Conductive routings in integrated circuits using under bump metallization
US8410374B2 (en) * 2009-02-27 2013-04-02 Ibiden Co., Ltd. Printed wiring board
TWI445147B (zh) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng 半導體元件
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
KR101225844B1 (ko) * 2010-07-13 2013-01-23 플란제 에스이 스퍼터링용 로터리 타겟의 접합 조성물 및 이를 이용한 로터리 타겟의 접합방법
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
US8268716B2 (en) * 2010-09-30 2012-09-18 International Business Machines Corporation Creation of lead-free solder joint with intermetallics
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US20150262952A1 (en) * 2014-03-13 2015-09-17 Taiwan Semiconductor Manufacturing Co., Ltd Bump structure and method for forming the same
US20150345044A1 (en) * 2014-05-29 2015-12-03 National Chung Shan Institute Of Science And Technology Method of electroplating cobalt alloy to wiring surface
US9406629B2 (en) * 2014-10-15 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US9401328B2 (en) * 2014-12-22 2016-07-26 Stmicroelectronics S.R.L. Electric contact structure having a diffusion barrier for an electronic device and method for manufacturing the electric contact structure
CN107186373B (zh) * 2017-06-09 2019-05-10 华北水利水电大学 一种钛基多层膜钎料及其制备方法
US10797010B2 (en) * 2017-12-29 2020-10-06 Texas Instruments Incorporated Semiconductor package having a metal barrier
US11228124B1 (en) * 2021-01-04 2022-01-18 International Business Machines Corporation Connecting a component to a substrate by adhesion to an oxidized solder surface

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1283970B (de) * 1966-03-19 1968-11-28 Siemens Ag Metallischer Kontakt an einem Halbleiterbauelement
US4290079A (en) * 1979-06-29 1981-09-15 International Business Machines Corporation Improved solder interconnection between a semiconductor device and a supporting substrate
US4434434A (en) * 1981-03-30 1984-02-28 International Business Machines Corporation Solder mound formation on substrates
JPS58141877A (ja) * 1982-02-19 1983-08-23 Sumitomo Electric Ind Ltd 溶接・鑞接用電極
JPS59117135A (ja) * 1982-12-24 1984-07-06 Hitachi Ltd 半導体装置の製造方法
DE3523808C3 (de) * 1984-07-03 1995-05-04 Hitachi Ltd Verfahren zum Löten von Teilen einer elektronischen Anordnung aus unterschiedlichen Werkstoffen und dessen Verwendung
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device
JPS6373660A (ja) * 1986-09-17 1988-04-04 Fujitsu Ltd 半導体装置
US4840302A (en) * 1988-04-15 1989-06-20 International Business Machines Corporation Chromium-titanium alloy
KR940010510B1 (ko) * 1988-11-21 1994-10-24 세이꼬 엡슨 가부시끼가이샤 반도체 장치 제조 방법
EP0448276B1 (en) * 1990-03-23 1996-06-05 AT&T Corp. Integrated circuit interconnection
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips
US5518674A (en) * 1991-06-28 1996-05-21 Texas Instruments Incorporated Method of forming thin film flexible interconnect for infrared detectors
US5162257A (en) * 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method
JPH0629769A (ja) * 1992-07-09 1994-02-04 Murata Mfg Co Ltd チップ型電子部品
US5234149A (en) * 1992-08-28 1993-08-10 At&T Bell Laboratories Debondable metallic bonding method
US5268072A (en) * 1992-08-31 1993-12-07 International Business Machines Corporation Etching processes for avoiding edge stress in semiconductor chip solder bumps
US5264108A (en) * 1992-09-08 1993-11-23 The United States Of America As Represented By The United States Department Of Energy Laser patterning of laminated structures for electroplating

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7040014B2 (en) 2003-01-21 2006-05-09 Tdk Corporation Method of producing a helical coil chip
CN101501935B (zh) * 2006-07-19 2012-04-18 博格华纳公司 具有导线挤压限制器的端子焊接片
CN101645413B (zh) * 2008-08-04 2012-01-25 中芯国际集成电路制造(上海)有限公司 金属连线的制作方法
CN104245203A (zh) * 2012-03-05 2014-12-24 株式会社村田制作所 接合方法、电子装置的制造方法和电子部件
CN104245203B (zh) * 2012-03-05 2016-10-12 株式会社村田制作所 接合方法、电子装置的制造方法和电子部件
CN109396586A (zh) * 2018-12-13 2019-03-01 华北水利水电大学 一种环氧树脂器件与pcb印刷电路板基材的钎焊方法
CN109396586B (zh) * 2018-12-13 2020-09-01 华北水利水电大学 一种环氧树脂器件与pcb印刷电路板基材的钎焊方法

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US5503286A (en) 1996-04-02
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