CN111587474A - 高蚀刻选择性的非晶碳膜 - Google Patents
高蚀刻选择性的非晶碳膜 Download PDFInfo
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- CN111587474A CN111587474A CN201880084977.2A CN201880084977A CN111587474A CN 111587474 A CN111587474 A CN 111587474A CN 201880084977 A CN201880084977 A CN 201880084977A CN 111587474 A CN111587474 A CN 111587474A
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- Prior art keywords
- amorphous carbon
- carbon film
- dopant
- processing region
- film
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/042—Coating on selected surface areas, e.g. using masks using masks
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/26—Deposition of carbon only
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
- C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Abstract
在本文中描述的实施方式总的来说涉及集成电路的制造。更具体地,在本文中描述的实施方式提供了用于在基板上沉积非晶碳膜的技术。在一个实施方式中,提供了一种形成非晶碳膜的方法。方法包括在第一处理区域中的位于基座上的底层上沉积非晶碳膜。方法进一步包括在第二处理区域中将掺杂剂或惰性物质植入到非晶碳膜中。掺杂剂或惰性物质选自碳、硼、氮、硅、磷、氩、氦、氖、氪、氙或其组合。方法进一步包括图案化经掺杂的非晶碳膜。方法进一步包括蚀刻底层。
Description
背景技术
技术领域
在本文中描述的实施方式总的来说涉及集成电路的制造。更具体地,在本文中描述的实施方式提供了用于在基板上沉积非晶碳膜的技术。
相关技术的描述
集成电路已经发展成可在单个芯片上包括数百万个晶体管、电容器和电阻器的复杂装置。芯片设计的发展不断地涉及更快的电路和更大的电路密度。对具有更大电路密度的更快电路的需求对用于制造这种集成电路的材料提出了相应需求。特别地,随着集成电路部件的尺寸减小到次微米级,低电阻率的导电材料以及低介电常数的绝缘材料用于从这些部件获得合适的电性能。
对更大集成电路密度的需求也对在集成电路部件的制造中使用的工艺顺序提出了需求。例如,在使用常规光刻技术的工艺顺序中,在沉积在基板上的材料层的堆叠之上形成一层能量敏感抗蚀剂。将能量敏感抗蚀剂层暴露于图案的图像,以形成光刻胶掩模。此后,使用蚀刻工艺将掩模图案转移到堆叠的材料层中的一个或多个。选择在蚀刻工艺中使用的化学蚀刻剂以使堆叠的材料层具有比能量敏感抗蚀剂的掩模更大的蚀刻选择性。也就是说,化学蚀刻剂以比能量敏感抗蚀剂快得多的速率来蚀刻材料堆叠的一个或多个层。在抗蚀剂之上对堆叠的一个或多个材料层的蚀刻选择性防止能量敏感抗蚀剂在完成图案转移之前被消耗。
随着图案尺寸减小,能量敏感抗蚀剂的厚度相应地减小,以便控制图案分辨率。由于化学蚀刻剂的侵蚀,这种薄的抗蚀剂层可能不足以在图案转移工艺期间遮蔽下面的材料层。通常在能量敏感抗蚀剂层和下面的材料层之间使用称为硬掩模的中间层(例如,氮氧化硅、硅卡宾或碳膜),以促进图案转移,因为对化学蚀刻剂具有较大抵抗性。期望具有高蚀刻选择性和高沉积速率的硬掩模材料。随着临界尺寸(CD)减小,当前的硬掩模材料相对于下面的材料(例如,氧化物和氮化物)缺乏目标蚀刻选择性并且通常难以沉积。
因此,本领域存在有一种改进的硬掩模层和用于沉积改进的硬掩模层的方法的需求。
发明内容
在本文中描述的实施方式总的来说涉及集成电路的制造。更具体地,在本文中描述的实施方式提供了用于在基板上沉积非晶碳膜的技术。在一个实施方式中,提供了一种形成非晶碳膜的方法。方法包括在第一处理区域中的位于基座上的底层上沉积非晶碳膜。方法进一步包括通过在第二处理区域中将掺杂剂或惰性物质植入到非晶碳膜中来形成掺杂的非晶碳膜。掺杂剂或惰性物质选自碳、硼、氮、氮二聚物、硅、磷、氩、氦、氖、氪、氙或其组合。方法进一步包括图案化掺杂的非晶碳膜并蚀刻底层。
在另一个实施方式中,提供了一种形成非晶碳膜的方法。方法包括在第一处理区域中的位于基座上的底层上沉积非晶碳膜。方法进一步包括通过在第二处理区域中将掺杂剂植入到非晶碳膜中来形成掺杂的非晶碳膜。掺杂剂或惰性物质选自碳、硼、氮、氮二聚物硅、磷、氩、氦、氖、氪、氙或其组合。方法进一步包括图案化掺杂的非晶碳膜。方法进一步包括蚀刻底层,其中掺杂的非晶碳膜在633nm处具有从约2.1至约2.2的折射率。
在又一实施方式中,提供一种包括非晶碳膜的硬掩模层。非晶碳膜通过等离子体增强化学气相沉积工艺随后进行碳植入工艺而形成。掺杂剂或惰性物质选自碳、硼、氮、氮二聚物、硅、磷、氩、氦、氖、氪、氙或其组合。非晶碳膜在用于半导体应用的蚀刻工艺中用作硬掩模层。
附图说明
因此,以可详细地理解本公开内容的上述特征的方式,可通过参考实施方式获得对上面简要概述的实施方式的更具体的描述,其中一些实施方式被示出在附图中。然而,应注意到,附图仅示出了本公开内容的典型实施方式,且因此不应视为限制本公开内容的范围,因为本公开内容可允许其他等效的实施方式。
图1描绘了可用于实践在本文中描述的实施方式的设备的示意图;
图2描绘了根据本公开内容的一个或多个实施方式的用于在设置在基板上的膜堆叠上形成非晶碳硬掩模层的方法的工艺流程图;
图3A至图3H图描绘了基板结构的示意性剖视图,示出了根据本公开内容的一个或多个实施方式的硬掩模形成顺序;
图4描绘了根据本公开内容的一个或多个实施方式的用于在设置在基板上的膜堆叠上形成非晶碳硬掩模层的方法的工艺流程图;
图5A描绘了与使用现有技术形成的非晶碳膜相比,根据本公开内容的实施方式形成的非晶碳膜的平面内应变相对于膜应力(MPa)的曲线图;以及
图5B描绘了图5A的非晶碳膜的杨氏模量(GPa)相对于膜应力(MPa)的曲线图。
为促进理解,在可能的情况下,已使用相同的元件符号来表示附图中共有的相同元件。预期到,一个实施方式的元件和特征可有利地并入其他实施方式中而无需进一步叙述。
具体实施方式
以下的公开内容描述了用于在基板上沉积类金刚石碳膜的技术。某些细节在以下描述和图1至图5B中阐述,以提供对本公开内容的各种实施方式的透彻理解。描述通常与等离子体处理和离子植入相关联的已知结构和系统的其他细节未在以下的公开内容中阐述,以避免不必要地模糊对各种实施方式的描述。
附图中所示的许多细节、尺寸、角度和其他特征仅仅是对特定实施方式的说明。因此,在不背离本公开内容的精神或范围的情况下,其他实施方式可具有其他细节、部件、尺寸、角度和特征。另外,可在没有下面描述的若干细节的情况下实践本公开内容的进一步实施方式。
下面将参考PECVD沉积工艺和离子植入工艺来描述在本文中所述的实施方式,PECVD沉积工艺和离子植入工艺可使用任何合适的薄膜沉积和植入系统来执行。合适系统的示例包括可使用处理腔室的系统、PRECISION系统、系统、GTTM系统、XP PrecisionTM系统、SETM系统、处理腔室和MesaTM处理腔室,所有这些都可从加州圣克拉拉市的应用材料公司商购获得。离子植入工艺可通过束线或等离子体植入工具执行。用于执行植入工艺的示例性系统包括(例如)VARIANTRIDENT系统、3000XP系统、900XP系统、HCP系统、Trident CrionTM系统和PLAD系统,可从加州圣克拉拉市的应用材料公司获得。其他能够执行PECVD和/或离子植入工艺的工具也可适用于受益于在本文所述的实施方式。另外,可使用能够实现在本文中所述的PECVD和/或离子植入工艺的任何系统而得利。在本文中描述的设备描述是说明性的,且不应被理解或解释为限制在本文中描述的实施方式的范围。
缩小集成电路的物理限制导致了与平面晶片表面正交的集成电路的扩展,即,高深宽比(HAR),装置空间的三维利用。用于适应动态蚀刻选择性和越来越严格的制造公差的纳米制造策略已经导致了硬掩模(HM)材料库,诸如掺杂有硅、钛、钨或硼的碳膜;以及介电氧化硅-氮化物(ON/OP)膜。以结合方式使用,这些材料在蚀刻选择性和低到1X节点的图案化中提供了优势。非晶碳硬掩模材料的创新对于在下一代装置结构中实现高深宽比(HAR)基准是期望的。与金属和介电质溶液相反,非晶碳是可清洗的,相对于下面的ON/OP硬掩模膜提供高选择性。非晶碳硬掩模的另一个好处是非晶碳硬掩模的相应光学性质,其可调谐以提供对准的图案化特征的透明度,因此消除了对部分硬掩模开放工艺的需要。然而,目前用于非晶碳硬掩模的集成硬件和工艺相对于金属掺杂和介电质硬掩模对应物表现出相对差的机械性质。对于具有高sp3含量的膜而言,可看到当前一代纯碳膜(例如,纳米晶金刚石、超纳米晶金刚石、类金刚石碳和物理气相沉积碳)的最高蚀刻选择性,类似于金刚石的杂化。类金刚石碳硬掩模中长期存在的高明暗度(value)问题是由于sp3混种碳导致的>1GPa的压缩膜应力,由于平板印刷覆盖和静电吸附限制,这限制了图案化性能。
具有64x层堆叠应用和100:1深宽比的下一代3D NAND产品需要允许图案化同时抵抗变形并同时展示改进的平板印刷覆盖的薄膜。类金刚石碳膜将碳物质特定的蚀刻选择性和优异的结构完整性结合。这些类金刚石碳膜将只有在其机械性质(其预兆为杨氏模量)能够在减小的应力和平面内畸变(“IPD”)值下进一步改进时才能保持竞争力。
本公开内容的一些实施方式提供了使用现有硬件且对产量或实现成本的影响很小的工艺。本公开内容的一些实施方式解决了平板印刷覆盖的高明暗度问题、以及与差的杨氏模量(E)相关联的高应力。本公开内容的一些实施方式提供了通过调谐等离子体沉积机制而将非晶碳的模量增加约2倍(例如,从约64GPa增加到约138GPa)的一种独特工艺。通过离子植入实现关键膜性质的进一步改进,离子植入使非晶碳膜的杨氏模量增加额外30%(~180GPa),同时将压缩应力降低75%(从约-1200降低到约-300MPa)。此外,与当前一代的纯碳硬掩模膜相比,PECVD加上离子植入的组合提供了实现显著更低的平面内畸变(<3纳米覆盖误差)的非晶碳膜。
在改进非晶碳硬掩模膜的性能方面,本公开内容的第一方面定义了新的工艺窗口。这个新的工艺窗口的目标是尽管存在高应力(例如,约-1200GPa)但改进模量的低平面内畸变。不受理论的束缚,但据信这些改进是利用通过降低压力而增加等离子体的鞘尺寸和增加工艺间隔导致等离子体温度降低来实现的。尽管合成温度降低,但沉积速率显著降低证实了更高的鞘势和Bohm(玻姆)速度。这有利于更多地形成碳-碳键,同时降低膜中的氢含量。在一个实施方式中,沉积后在633nm处测量的消光系数值为0.72,表明更高的C=C,石墨特征。此外,降低等离子体的密度增加了平均自由路径、轰击能量并改进了晶片表面上的离子能量分布函数的均匀性。因为较弱的等离子体(通过轰击使非晶化最小化)导致的膜内特质示出杨氏模量(E)、硬度和密度的增加。不受理论束缚,但据信增加的平均自由路径导致针对平板印刷覆盖的较低平面内畸变(IPD)。
本公开内容的第二方面(在线离子植入)用于将非晶碳膜的应力分量降低高达约75%(例如,从约-1200降低到约-300MPa),进一步改进杨氏模量(例如,从约138改进到约177GPa)并使平面内畸变轮廓更中心对称。离子植入可在一定温度范围(例如,从约-100摄氏度至约500摄氏度)下执行。于此建立的是,降低非晶碳膜的离子植入温度使植入的掺杂剂的重排最小化-证实了植入的有益效果,诸如致密化、sp3强化和氢还原。不受理论束缚,但据信离子植入重新分布了局部应力并有助于将整个晶片应力减小到(例如)膜后沉积值的约25%。基于进入的晶片模量而发展用于植入的正确工艺方案,以在减小应力的同时最佳地强化模量,以绕过膜改善的饱和度的HVP。
与当前可取得的纯碳硬掩模膜相比,所得到的非晶碳膜示出30-50%的蚀刻选择性的改进,同时还匹配先前的覆盖要求。
在本公开内容的一些实施方式中,经由等离子体增强化学气相沉积将非晶碳膜沉积到裸硅覆盖晶片上。在一些实施方式中,碳前驱物为C3H6,其中等离子体轮廓和均匀性由氩气和氦气维持。这项工作的范围还包括使用C4H8、C2H6、C2H4、C2H2、CO2和CF4等。这个应用的高频RF为13.56MHz。单晶片硬件可在高达650摄氏度的温度下进行沉积,并使用气体盒、带有平面加热器边缘环配置的喷头组合,从中心到边缘保持等离子体稳定性。等离子体轮廓和与晶片表面的耦合可通过RF的分层而进一步调谐,以横向且垂直于晶片表面地分布。
在一些实施方式中,在单晶片处理工具中执行离子植入。热交换器使温度控制和冷植入技术的发展能够达到摄氏-100度。本公开内容中所示的产生高性能的物质是可清洗的离子,保持膜的纯碳特性。
图1是根据本公开内容的各种实施方式而配置的等离子体处理腔室100的示意性剖视图。作为示例,图1中的等离子体处理腔室100的实施方式是根据PECVD系统而描述的,但是任何其他等离子体处理腔室可落入实施方式的范围内,包括其他等离子体沉积腔室或等离子体蚀刻腔室。等离子体处理腔室100包括壁102、底部104和腔室盖124,它们一起包围基座105和处理区域146。等离子体处理腔室100进一步包括真空泵114、第一RF发生器151、第二RF发生器152、RF匹配器153、气源154、顶部RF电流调谐器155、底部RF电流调谐器157和系统控制器158,每个都在外部耦接到等离子体处理腔室100,如图所示。
壁102和底部104可包括导电材料,诸如铝或不锈钢。通过一个或多个壁102,可存在狭缝阀开口,所述狭缝阀开口被配置为促进将基板110插入到等离子体处理腔室100中以及将基板110从等离子体处理腔室100移除。配置成密封狭缝阀开口的狭缝阀可设置在等离子体处理腔室100的内侧或外侧中的任一侧。为清楚起见,图1中未示出狭缝阀或狭缝阀开口。
真空泵114耦接到等离子体处理腔室100且配置成调节其中的真空水平。如图所示,阀116可耦接在等离子体处理腔室100和真空泵114之间。真空泵114通过阀116在基板处理之前抽空等离子体处理腔室100,并且在处理期间从等离子体处理腔室100移除工艺气体。阀116可以是可调节的,以促进调节等离子体处理腔室100的抽空速率。通过阀116的抽空速率和来自气源154的进入气体流速来确定等离子体处理腔室100中的腔室压力和工艺气体驻留时间。
气源154经由穿过腔室盖124的管123而耦接到等离子体处理腔室100。管123流体地耦接到在背板106和气体分配喷头128之间的气室148,气体分配喷头128包括在腔室盖124中。在操作期间,从气源154引入到等离子体处理腔室100中的工艺气体填充气室148,并接着穿过形成在气体分配喷头128中的气体通道129,以均匀地进入处理区域146。在替代实施方式中,除了气体分配喷头128之外或代替气体分配喷头128,工艺气体可经由入口和/或喷嘴(未示出)而引入到处理区域146中,所述入口和/或喷嘴附接到(多个)壁102。
基座105可包括用于在由等离子体处理腔室100处理期间支撑基板的任何技术上可行的设备,诸如图1中的基板110。在一些实施方式中,基座105设置在轴112上,轴112配置成升高和降低基座105。在一个实施方式中,轴112和基座105可至少部分地由导电材料形成或含有导电材料,诸如钨、铜、钼、铝或不锈钢。替代地或另外地,基座105可至少部分地由陶瓷材料形成或含有陶瓷材料,诸如氧化铝(Al2O3)、氮化铝(AlN)、二氧化硅(SiO2)等。在等离子体处理腔室100是电容耦合等离子体腔室的实施方式中,基座105可配置成含有电极113。在这样的实施方式中,金属杆115或其他导体电耦合到电极113且配置成提供传送到等离子体处理腔室100的RF功率的接地路径的一部分。即,金属杆115使得传送到等离子体处理腔室100的RF功率能够通过电极113并离开等离子体处理腔室100以接地。
在一些实施方式中,电极113还配置成提供来自DC电源(未示出)的电偏压,以在等离子体处理期间能够将基板110静电夹持到基座105上。在这样的实施方式中,基座105通常包括主体,所述主体包括一种或多种陶瓷材料,诸如上述的陶瓷材料,或适用于静电卡盘的任何其他陶瓷材料。在这样的实施方式中,电极113可为网状物,诸如RF网状物,或由钼(Mo)、钨(W)或热膨胀系数基本上类似于陶瓷材料或包括在基座105的主体中的材料的热膨胀系数的其他材料所制成的多孔材料片。电极113和气体分配喷头128一起界定等离子体形成在其中的处理区域146的边界。例如,在处理期间,基座105和基板110可升高并定位在气体分配喷头128的下表面附近(例如,在10-30mm内),以形成至少部分地封闭的处理区域146。
第一RF发生器151是射频(RF)电源,配置成经由RF匹配器153向放电电极126提供第一RF频率的高频功率。类似地,第二RF发生器152是RF电源,配置成经由RF匹配器153向放电电极126以第二RF频率提供高频功率。在一些实施方式中,第一RF发生器151包括能够以高频(HF)(例如,约13.56MHz)产生RF电流的RF电源。替代地或另外地,第一RF发生器151包括能够产生VHF功率的VHF发生器,诸如在约20MHz到200MHz或更高的频率下的VHF功率。与之相比,第二RF发生器152包括能够以所谓的低频(LF)RF(例如,约350kHz)产生RF电流的RF电源。替代地或另外地,第二RF发生器152包括能够以在约1kHz至约1MHz之间的频率下产生RF功率的RF发生器。第一RF发生器151和第二RF发生器152配置成促进在放电电极126和基座105之间产生等离子体。
放电电极126可包括工艺气体分配元件,诸如气体分配喷头128(如图1所示)和/或气体注入喷嘴的阵列,工艺气体通过所述气体注入喷嘴的阵列被引入到处理区域146中。放电电极126(即气体分配喷头128)可基本上平行于基板110的表面取向,并且将等离子体源功率电容耦合到处理区域146中,处理区域146设置在基板110和气体分配喷头128之间。
RF匹配器153可为任何技术上可行的阻抗匹配设备,其耦接在第一RF发生器151与等离子体处理腔室100的供电电极(即,气体分配喷头128)之间。RF匹配器153也耦接在第二RF发生器152与等离子体处理腔室100的供电电极之间。RF匹配器153被配置成使负载阻抗(等离子体处理腔室100)与源或驱动源(第一RF发生器151、第二RF发生器152)的内部阻抗相匹配,以实现从第一RF发生器151和第二RF发生器152到等离子体处理腔室100的RF功率的最大传输。
形成壁102的一部分的是上隔离器107、调谐环108和下隔离器109。上隔离器107配置成电隔离调谐环108(由导电材料形成)与背板106,在一些实施方式中,背板106在操作期间以RF功率被供能。因此,上隔离器107位于背板106与调谐环108之间,并防止调谐环108经由背板106而以RF功率被供能。在一些实施方式中,上隔离器107配置为绕处理区域146同心地定位的陶瓷环或环形物(annulus)。类似地,下隔离器109配置为将调谐环108与壁102电隔离。壁102通常由导电材料形成,且因此可用作在处理期间传送到等离子体处理腔室100的一部分RF功率的接地路径。因此,下隔离器109使得调谐环108能够成为传送到等离子体处理腔室100的RF功率的与壁102的接地路径不同的接地路径的一部分。在一些实施方式中,上隔离器107配置成陶瓷环,或配置成包括绕处理区域146同心地定位的陶瓷环。
调谐环108设置在上隔离器107和下隔离器109之间,由导电材料形成,且邻近处理区域146设置。例如,在一些实施方式中,调谐环108由合适的金属形成,诸如铝、铜、钛或不锈钢。在一些实施方式中,调谐环108是在基板110的处理期间绕基座105和基板110同心地定位的金属环或环形物(annulus)。此外,调谐环108经由导体156并经由顶部RF电流调谐器155而电耦合到接地,如图所示。因此,调谐环108不是供电电极,且通常设置在处理区域146的外侧和周围。在一个示例中,调谐环108位于与基板110基本平行的平面中,且是用于在处理区域146中形成等离子体的RF能量的接地路径的一部分。结果,经由顶部RF电流调谐器155在气体分配喷头128和接地之间建立额外的RF接地路径141。因此,通过以特定频率改变顶部RF电流调谐器155的阻抗,在那个特定频率处的RF接地路径141的阻抗改变,引起在那个频率处耦合到调谐环108的RF场的变化。因此,处理区域146中的等离子体的形状可沿着+/-X和Y方向独立地被调制,用于与第一RF发生器151或第二RF发生器152相关联的RF频率。即,在处理区域146中形成的等离子体的形状、体积或均匀性可通过使用(例如)调谐环108而在基板110的表面上独立地调制,或使用电极113而垂直地在基板110和气体分配喷头128之间针对多个RF频率独立地调制。
系统控制器158配置成控制等离子体处理腔室100的部件和功能,诸如真空泵114、第一RF发生器151、第二RF发生器152、RF匹配器153、气源154、顶部RF电流调谐器155和底部RF电流调谐器157。这样,系统控制器158接收传感器输入,例如,来自顶部RF电流调谐器155和底部RF电流调谐器157的电压-电流输入,并传输用于等离子体处理腔室100的操作的控制输出。系统控制器158的功能可包括任何技术上可行的实现,包括经由软件、硬件和/或固件,且可在与等离子体处理腔室100相关联的多个单独的控制器之间划分。
不受理论束缚,但据信通过在等离子体增强沉积工艺期间将不同频率的RF功率输送到等离子体处理腔室的处理区域,可调节沉积膜的性质。例如,调节输送到处理区域146的低频RF等离子体功率和/或频率(即,以1kHz至1MHz的方式形成RF等离子体)可有利于调节一些沉积膜性质(诸如膜应力),而同时调节输送到处理区域146的高频RF等离子体功率和/或频率(即,以1MHz至200MHz的方式形成RF等离子体)可有利于调节其他沉积膜性质(诸如厚度均匀性)。根据本公开内容的各种实施方式,调谐设备能够在多个RF频率下独立控制在等离子体处理腔室100中的RF电流的流动。在一些实施方式中,在等离子体处理腔室100中的多个位置处采用这种调谐设备,即,顶部RF电流调谐器155和底部RF电流调谐器157。
如上所述,顶部RF电流调谐器155电耦合到调谐环108并且端接到接地,从而为等离子体处理腔室100提供可控的RF接地路径141。类似地,底部RF电流调谐器157电耦合到金属杆115并且端接到接地,从而为等离子体处理腔室100提供不同的可控RF接地路径142。如在本文所述,顶部RF电流调谐器155和底部RF电流调谐器157每个都配置成控制多个RF频率下的RF电流的流动到接地。因此,在调谐环108和金属杆115之间处于第一RF频率的RF电流的分布可独立于在调谐环108和金属杆115之间处于第二RF频率的RF电流的分布来被控制。
在电极113和放电电极126之间的处理区域146中形成等离子体180。在电极113的底表面和基座105的顶表面之间的距离或“间隔”由“X”表示。
其他沉积腔室也可受益于本公开内容,且上面列出的参数可根据用于形成非晶碳层的特定沉积腔室而变化。例如,其他沉积腔室可具有更大或更小的体积,需要比可从应用材料公司获得的沉积腔室所述的气体流速更大或更小的气体流速。在一个实施方式中,可使用可从加州圣克拉拉市的应用材料公司商购获得的XP PrecisionTM处理系统来沉积硼-碳膜。
掺杂剂或惰性物质掺入非晶碳膜中的原子百分比计算如下:(以cm-3计的掺杂剂浓度除以预期用于特定密度的C膜的每cm-3的C原子数。非晶碳膜可含有至少0.1、1或10原子百分比的掺杂剂或惰性物质。非晶碳膜可含有高达1、10或30原子百分比的掺杂剂或惰性物质。非晶碳膜可含有从约1至约30原子百分比的掺杂剂或惰性物质。非晶碳膜可含有从约10至约30原子百分比的掺杂剂或惰性物质。非晶碳膜可含有至少3、5或10原子百分比的氢。非晶碳膜可含有高达5、10或15原子百分比的氢。非晶碳膜可含有从约3至约15原子百分比的氢。
在掺杂剂是碳的一种实施方式中,碳掺入非晶碳膜中的原子百分比计算如下:((C/(H+C))%)。非晶碳膜可含有至少85、90或95原子百分比的碳。非晶碳膜可含有高达90、95或97原子百分比的碳。非晶碳膜可含有从约85至约97原子百分比的碳。非晶碳膜可含有从约90至约97原子百分比的碳。非晶碳膜可含有至少3、5或10原子百分比的氢。非晶碳膜可含有高达5、10或15原子百分比的氢。非晶碳膜可含有从约3至约15原子百分比的氢。
通常,以下的示例性沉积工艺参数可用于在本文所述的非晶碳膜沉积工艺的PECVD部分。工艺参数的范围可为从约100摄氏度到约700摄氏度(例如,在约300摄氏度至约700摄氏度之间)的晶片温度。腔室压力的范围可从约1托到约20托(例如,在约2托和约8托之间;或在约5托和约8托之间)的腔室压力。含烃气体的流速可为从约100sccm至约5000sccm(例如,在约100sccm和约2000sccm之间;或在约160sccm和约500sccm之间)。稀释气体的流速的范围可分别地为从约0sccm至约5000sccm(例如,从约2000sccm至约4080sccm)。惰性气体的流速的范围可分别地为从约0sccm至约10000sccm(例如,从约0sccm至约2000sccm;从约200sccm至约2000sccm)。RF功率可在1000瓦至3000瓦之间。在基板110的顶表面和气体分配喷头128之间的板间距可设定为在约200密耳至约1000密耳之间(例如,在约200密耳和约600密耳之间;在约300密耳至约1000密耳之间;或在约400密耳和约600密耳之间)。可沉积非晶碳膜以具有在约和约之间的厚度(例如,在约和约之间;或在约至约之间)。上述工艺参数为非晶碳膜提供了典型的沉积速率,其范围为约/分钟至约/分钟(例如,从约/分钟至约/分钟),且可在可从加州圣克拉拉市的应用材料公司获得的沉积腔室中的300mm基板上实现。
在植入之前沉积的非晶碳膜可具有大于1.9的折射率(n)(633nm),例如大约2.2(例如,从约2.1至约2.5)。例如,沉积的非晶碳膜可具有小于1.0的k值(k(在633nm处))(例如,从约0.6至约0.8)。沉积的非晶碳膜可具有从约50至约200GPa(例如,从约60至约140GPa;或从约100至约140GPa)的杨氏模量(GPa)。沉积的非晶碳膜可具有从约10GPa至约22GPa(例如,从约10GPa至约15GPa;或从约12GPa至约14GPa)的硬度(GPa)。沉积的非晶碳膜可具有从约-1300MPa至约0MPa(例如,从约-1300MPa至约-250MPa;从约-1250MPa至约-1000MPa)的应力(MPa)。沉积的非晶碳膜可具有从约1.7g/cc至约1.87g/cc(例如,从约1.74g/cc至约1.85g/cc)的密度(g/cc)。
在碳植入之后沉积的非晶碳膜可具有大于2.04的折射率(n)(633nm),例如大约2.2(例如,从约2.1至约2.2)。例如,沉积的非晶碳膜可具有小于1.0的k值(k(在633nm处))(例如,从约0.5至约0.8;从约0.6至约0.7)。植入后沉积的非晶碳膜可具有从约70至约200GPa(例如,从约120至约180GPa;或从约130至约170GPa)的杨氏模量(GPa)。植入后沉积的非晶碳膜可具有从约14GPa至约22GPa(例如,从约15GPa至约20GPa;或从约16GPa至约19GPa)的硬度(GPa)。植入后沉积的非晶碳膜可具有从约-600MPa至约0MPa(例如,从约-400MPa至约0Pa;从约-350MPa至约0MPa)的应力(MPa)。沉积的非晶碳膜可具有大于1.9g/cc,例如大约2.1g/cc(例如,从约1.95g/cc至约2.1g/cc)的密度(g/cc)。
图2描绘了根据本公开内容的一个或多个实施方式的用于在设置在基板上的膜堆叠上形成非晶碳硬掩模层的方法200的工艺流程图。图3A至图3H描绘了基板结构的示意性剖视图,示出了根据方法200的硬掩模形成顺序。尽管下面参考可在用于三维半导体装置的膜堆叠中制造楼梯状结构的膜堆叠上形成的硬掩模层来描述方法200,但是方法200还可用于在其他装置制造应用中得利。此外,还应理解图2中描绘的操作可同时地执行和/或以与图2中所示的顺序不同的顺序执行。
方法200通过将基板302定位到处理腔室(诸如图1中所示的等离子体处理腔室100)中而在操作210处开始。基板302可为图1中所示的基板110。基板302可为在其上形成的膜堆叠300的一部分。
在一个实施方式中,基板110的表面(如图1所示)基本上是平面的。替代地,基板110可具有图案化结构,例如,其中形成有沟槽、孔或通孔的表面。基板110还可具有基本平坦的表面,基本平坦的表面具有在其上或其中以目标高度形成的结构。虽然基板110被示出为单个主体,但是理解到基板110可含有在形成半导体装置中使用的一种或多种材料,诸如金属触点、沟槽隔离件、栅极、位线或任何其他互连特征。基板110可包括用于制造半导体装置的一个或多个金属层、一个或多个介电材料、半导体材料及其组合。例如,取决于应用,基板110可包括氧化物材料、氮化物材料、多晶硅材料等。在以存储器应用为目标的一个实施方式中,基板110可包括硅基板材料、氧化物材料和氮化物材料,其中夹有或不夹有多晶硅。
在另一实施方式中,基板110可包括沉积在基板110的表面上的多个交替的氧化物和氮化物材料(即,氧化物-氮化物-氧化物(ONO))(未示出)。在各种实施方式中,基板110可包括多个交替的氧化物和氮化物材料、一种或多种氧化物或氮化物材料、多晶硅或非晶硅材料、与非晶硅交替的氧化物、与多晶硅交替的氧化物、与掺杂硅交替的未掺杂硅、与掺杂多晶硅交替的未掺杂多晶硅或与掺杂的非晶硅交替的未掺杂的非晶硅。基板110可为在其上执行膜处理的任何基板或材料表面。例如,基板110可为诸如晶体硅、氧化硅、氮氧化硅、氮化硅、应变硅、硅锗、钨、氮化钛、掺杂或未掺杂的多晶硅、掺杂或未掺杂的硅晶片以及图案化或非图案化的晶片、绝缘体上硅(SOI)、碳掺杂的氧化硅、氮化硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石、低k介电质以及它们的组合之类的材料。
膜堆叠300包括基板302和底层304。如在本文中所使用的,底层304包括设置在非晶碳硬掩模下方的任何层。例如,非晶碳硬掩模306可直接设置在底层304上方,使得非晶碳硬掩模306和底层304彼此物理接触。在一个实施方式中,底层304包括单个层。在另一实施方式中,底层304包括介电质堆叠。
在操作220处,非晶碳硬掩模306形成在设置在基板302之上的底层304上,如图3B所示。通过在底层304之上毯式沉积工艺来沉积非晶碳硬掩模306。在一些实施方式中,根据图4的工艺流程图中描述的方法400来沉积非晶碳硬掩模306。可将非晶碳硬掩模306沉积到一厚度,所述厚度对应于底层304的后续蚀刻要求。在一个示例中,非晶碳硬掩模具有在约0.5μm和约1.5μm之间的厚度,诸如约1.0μm。
在操作230处,离子植入工艺用掺杂剂来掺杂非晶碳硬掩模306,以形成掺杂有掺杂剂的掺杂的非晶碳硬掩模312,如图3C所示。可使用任何合适的掺杂技术。在一个实施方式中,采用等离子体浸没离子植入技术来植入掺杂剂或惰性物质。在一个实施方式中,采用束线植入技术来植入掺杂剂或惰性物质。在一个实施方式中,可采用共形掺杂技术(诸如等离子体掺杂(PLAD)技术)来植入掺杂剂或惰性物质。
合适的离子物质可由各种前驱物材料产生,诸如含碳、硼、氮、硅、磷、氦、氩、氖、氪及氙的材料。在一个实施方式中,掺杂剂或惰性物质选自碳、硼、氮、硅、磷、氩、氦、氖、氪、氙或其组合。含碳前驱物气体的示例包括CH4。在一个实施方式中,各种前驱物材料由前驱物材料的组合产生,包括(例如)CH4/N2、CH4/He、N2/He、CH4/Ne、CH4/Ar、CH4/Ne、CH4/Kr、CH4/Xe。
在示意图中,离子310轰击非晶碳硬掩模306且通常穿透非晶碳硬掩模306,以形成植入有掺杂剂或惰性物质的掺杂非晶碳硬掩模312。离子310穿透非晶碳硬掩模306到各种深度,这取决于离子的类型和尺寸以及用于激励离子310的功率和偏压。离子310的物质可被订制以提供底层304的增加的蚀刻选择性。如此,植入的物质可为适于增强非晶碳硬掩模306的蚀刻选择性的任何单体或分子离子。
可通过束线或等离子体植入工具来执行离子植入工艺。用于执行植入工艺的示例性系统包括(例如)VARIANTrident系统、3000XP系统、900XP系统、HCP系统和PLAD系统,可从加州圣克拉拉市的应用材料公司获得。尽管关于上述系统进行了描述,但是预期到来自其他制造商的系统也可用于执行离子植入工艺。
在一个实施方式中,离子植入工艺将掺杂剂或惰性物质植入非晶碳硬掩模306中。掺杂剂或惰性物质选自碳、硼、氮、硅、磷、氩、氦、氖、氪、氙或其组合。在一个实施方式中,用于激励掺杂剂的植入能量在约1keV和约60keV之间(例如,在约5keV和约60keV之间;在约1keV和约15keV之间;在约10keV和约35keV之间;在约20keV和约30keV之间;或在约20keV和约25keV之间),取决于所用掺杂剂的类型、用作非晶碳硬掩模306的材料的类型及目标的植入深度。在一个实施方式中,离子剂量(离子/cm2)在约5x1013离子/cm2和约5x1017离子/cm2之间(例如,在约1x1015离子/cm2和约3x1017离子/cm2之间;在约1x1014离子/cm2和约5x1016离子/cm2之间;在约1x1014离子/cm2和约2x1016离子/cm2之间;在约1x1015离子/cm2和约1x1016离子/cm2之间;在约5x1015离子/cm2和约1x1016离子/cm2之间),取决于所用掺杂剂的类型、用作非晶碳硬掩模306的材料的类型和目标的植入深度。在使用PLAD植入技术的一个实施方式中,用于激励掺杂剂或惰性物质的植入能量在约1kV和约60kV之间(例如,在约5kV和约60kV之间;在约1kV和约15kV之间;在约10kV和约35kV之间;在约20kV和约30kV之间;或在约20kV和约25kV之间),离子剂量范围在约5x1013离子/cm2和约5x1017离子之间/cm2之间(例如,在约1x1015离子/cm2和约3x1017离子/cm2之间;在约1x1014离子/cm2和约5x1016离子/cm2之间;在约1x1014离子/cm2和约2x1016离子/cm2之间;在约1x1015离子/cm2和约1x1016离子/cm2之间;在约5x1015离子/cm2和约1x1016离子/cm2之间)。在掺杂剂是氦的一个实施方式中,用于激励掺杂剂的植入能量在约1kV至约15kV之间,离子剂量范围在约1x1015离子/cm2和约3x1017离子/cm2之间。在一个实施方式中,目标温度在约摄氏-100度和约500摄氏度之间(例如,在约摄氏-100度和约200摄氏度之间;在约摄氏-100度和约0摄氏度之间;在约摄氏-100度和约50摄氏度之间;在约0摄氏度和约50摄氏度之间;或在约50摄氏度和约400摄氏度之间。)
通常,在非晶碳硬掩模306打开之后,非晶碳硬掩模306的增加的硬度提供了底层304中的高深宽比结构的线弯曲减少。据信植入的离子310从非晶碳硬掩模306的悬空碳-氢键中提取残留的氢原子,并在非晶碳硬掩模306内形成碳化物结构。当与未掺杂的硬掩模相比时,碳化物结构表现出增加的硬度。另外,据信植入的离子310占据非晶碳硬掩模306内存在的间隙空隙,这导致非晶碳硬掩模306的密度增加。增加的密度进一步增加了非晶碳硬掩模306的机械完整性。
在一个实施方式中,在离子植入工艺之后,对膜堆叠300进行热处理。合适的离子植入后热处理技术包括UV处理、热退火和激光退火。掺杂的非晶碳硬掩模312的热处理进一步将植入的离子310结合到掺杂非晶碳硬掩模312的框架中。例如,植入的离子310可在掺杂非晶碳硬掩模312内重新分布,以形成更均匀的掺杂轮廓。据信热处理可增加在掺杂的非晶碳硬掩模312的非晶碳与植入的离子310之间的相互作用和键合。植入的离子310的重新分布和键合可用于进一步增加掺杂的非晶碳硬掩模312的硬度、密度和蚀刻选择性。在一种实施方式中,退火工艺在等离子体处理腔室中执行,诸如等离子体处理腔室100。在另一种实施方式中,退火工艺在单独的退火腔室中执行。
在操作240处,在掺杂有掺杂剂或惰性物质的掺杂的非晶碳硬掩模312之上形成图案化的光刻胶层320,如图3D所示。可利用能量源(诸如光能)从光掩模将特征或图案转移到光刻胶层320。在一个实施方式中,光刻胶层320是聚合物材料,且图案化工艺通过193纳米浸没式光刻工艺或其他类似的光刻工艺来执行。类似地,激光也可用于执行图案化工艺。
在操作250处,通过(例如)等离子体蚀刻工艺来打开掺杂的非晶碳硬掩模312,以形成图案化的掺杂的非晶碳硬掩模322,如图3E所示。等离子体蚀刻工艺可在与关于图3C描述的腔室类似的腔室中执行。
在操作260处,移除光刻胶层320,如图3F所示。可通过各种有利的光刻胶移除工艺来移除光刻胶层320。
在操作270处,蚀刻底层304,如图3G所示。底层304蚀刻可在等离子体处理腔室中进行,诸如关于图1B描述的腔室和系统。蚀刻剂(诸如碳氟化合物)移除底层304的暴露部分。蚀刻剂的活性物质基本上不与图案化的掺杂的非晶碳硬掩模322的材料(植入的离子310)反应。因此,蚀刻剂对于底层304材料具有选择性。蚀刻剂的合适示例包括CF4、CHF3、HBr、BCl3和Cl2等。可用惰性载气提供蚀刻剂。
在操作280处,移除图案化的掺杂的非晶碳硬掩模322。可通过任何有利的硬掩模移除工艺来移除图案化的掺杂的非晶碳硬掩模322。在一个示例中,利用氧等离子体来移除图案化的掺杂的非晶碳硬掩模322。所得的膜堆叠300包括底层304,底层304具有形成在其中的特征324(诸如高深宽比特征)。膜堆叠300可接着经受进一步处理以形成功能半导体装置。
图4是描绘根据在本文中描述的实施方式的用于沉积非晶碳膜的方法400的一个实施方式的工艺流程图。在一个实施方式中,方法400可用于沉积操作220的非晶碳膜。方法400在操作410处通过在处理腔室的处理区域中提供基板而开始。处理腔室可为图1中所示的等离子体处理腔室100。基板可为也在图1中示出的基板110,或图3A至图3H中所示的基板302。
在操作420处,使含烃气体混合物流到处理区域146中。含烃气体混合物可从气源154通过气体分配喷头128流到处理区域146中。气体混合物可包括至少一个烃源和/或含碳源。气体混合物可进一步包括惰性气体、稀释气体、含氮气体或其组合。烃源和/或含碳源可为任何液体或气体,但优选的前驱物在室温下将是蒸气,以简化材料计量、控制和输送到腔室所需的硬件。
在一个实施方式中,烃源是气态烃,诸如线性烃。在一个实施方式中,烃化合物具有通式CxHy,其中x具有在1和20之间的的范围,y具有在1和20之间的范围。在一个实施方式中,烃化合物为烷烃。合适的烃化合物包括(例如)甲烷(CH4)、乙炔(C2H2)、乙烯(C2H4)、乙烷(C2H6)、丙烯(C3H6)和丁烯(C4H8)、环丁烷(C4H8)和甲基环丙烷(C4H8)。合适的丁烯包括1-丁烯、2-丁烯和异丁烯。其他合适的含碳气体包括二氧化碳(CO2)和四氟化碳(CF4)。在一个示例中,由于形成更稳定的中间物质,因而C3H6是优选的,这允许更多的表面迁移率。
可将合适的稀释气体(诸如氦(He)、氩(Ar)、氢(H2)、氮(N2)、氨(NH3)或其组合等)加入到气体混合物中。Ar、He和N2用于控制非晶碳层的密度和沉积速率。在一些情况下,添加N2和/或NH3可用于控制非晶碳层的氢比例,如下所述。替代地,在沉积期间可不使用稀释气体。
含氮气体可与含烃气体混合物一起供应到等离子体处理腔室100中。合适的含氮化合物包括(例如)吡啶、脂族胺、胺、腈、氨和类似化合物。
惰性气体(诸如氩(Ar)和/或氦(He))可与含烃气体混合物一起供应到等离子体处理腔室100中。其他惰性气体(诸如氮(N2)和一氧化氮(NO))也可用于控制非晶碳层的密度和沉积速率。另外,可将各种其他工艺气体添加到气体混合物,以改变非晶碳材料的性质。在一个实施方式中,工艺气体可为反应性气体,诸如氢(H2)、氨(NH3)、氢(H2)和氮(N2)的混合物或其组合。加入H2和/或NH3可用于控制沉积的非晶碳层的氢比例(例如,碳与氢的比例)。存在于非晶碳膜中的氢比例提供对层性质(诸如反射率)的控制。
任选地,在操作430处,将处理区域中的压力稳定达预定的RF接通延迟时间段。预定义的RF接通延迟时间段是固定的时间延迟,其定义为在操作430中在将含烃气体混合物引入处理区域中与撞击或产生等离子体之间的时间段。可使用任何合适的固定时间延迟以达到目标条件。通常选择RF接通延迟时间段的长度,以使得含烃或含碳气体混合物在处理区域中不开始热分解或基本上热分解。
在操作440处,在处理区域中产生RF等离子体以沉积非晶碳膜,诸如非晶碳硬掩模306。等离子体可通过电容手段或电感手段来形成,且可通过将RF功率耦合到前驱物气体混合物中来进行激励。RF功率可为具有高频分量和低频分量的双频RF功率。RF功率通常以在约50W和约2500W之间(例如,在约2000W至约2500W之间)的功率水平施加,其可为全部高频RF功率(例如在约13.56MHz的频率下),或可为高频功率和低频功率(例如在约300kHz的频率下)的混合。对于大多数应用而言,将等离子体保持达一定时间段以沉积具有厚度在约至约之间的非晶碳层。含烃气体混合物的流动,达到非晶碳膜的目标厚度。操作440的工艺可与操作420和操作430的工艺同时执行、依序执行,或操作440的工艺可与操作420和操作430的工艺部分地重叠。
在本文中所述的任何PECVD实施方式中,在沉积非晶碳膜期间,腔室、晶片或两者可维持在约200摄氏度至约700摄氏度之间的温度(例如,在约400摄氏度至约700摄氏度之间;或在约500摄氏度至约700摄氏度之间)。腔室压力的范围可为从约1托到约10托的腔室压力(例如,在约2托和约8托之间;或在约4托和约8托之间)。在基座和气体分配喷头之间的距离(即,“间隔”)可设定为在约200密耳至约1000密耳之间(例如,在约200密耳和约600密耳之间;在约300密耳至约1000密耳之间;或在约400密耳和约600密耳之间)。
通过执行任选的吹扫/抽空工艺,可接着从处理区域移除任何过量的工艺气体和来自调节层的沉积的副产物。
图5A描绘了与使用现有技术所形成非晶碳膜(510、512和514)相比,根据本公开内容的实施方式所形成的非晶碳膜(520、522和530、532)的平面内畸变相对于膜应力(MPa)的曲线图500。注意到在碳掺杂剂植入之前描绘了根据本公开内容的实施方式所形成的非晶碳膜(520、522和530、532)。图5B描绘了图5A的非晶碳膜的杨氏模量(GPa)相对于膜应力(MPa)的曲线图550。如图5A至图5B所示,根据在本文所述的实施方式所形成的非晶碳膜(520、522和530、532)实现了尽管高应力(例如,-1200MPa)但低的平面内畸变和改进的模量。在本文中所述的后续碳掺杂剂植入工艺将压缩膜应力减小了大约4倍,同时将模量增加了大约1.4倍。
方法200和方法400对于在半导体装置制造工艺中的金属化工艺之前的前端产线工艺(FEOL)中使用的工艺是有用的。由于它们的高蚀刻选择性,通过方法200形成的非晶碳膜可在蚀刻工艺期间用作硬掩模层。合适的工艺包括栅极制造应用、触点结构应用、浅沟槽隔离(STI)工艺等。在使用非晶碳膜用作蚀刻停止层或用作用于不同工艺目的的不同膜的一些实施方式中,非晶碳膜的机械性质或光学性质也可被调节以满足特定的工艺需要。
因此,根据在本文中所述的实施方式,通过等离子体沉积工艺随后进行碳植入工艺来提供用于形成具有目标平面内畸变和具低应力的杨氏模量的高蚀刻选择性非晶碳膜的方法。方法有利地提供具有目标机械性质(诸如低应力和高杨氏模量)的非晶碳膜、碳-碳键合和氢结合的变化及高蚀刻选择性。本公开内容的实施方式进一步提供了一种使用现存硬件而对产量或实现成本几乎没有影响的工艺设计。本公开内容的一些实施方式提供了通过调谐等离子体沉积机制而将非晶碳膜的模量增加约2倍(例如,从约64GPa增加到约138GPa)的一种独特工艺。通过离子植入实现关键膜性能的进一步改进,所述离子植入使非晶碳膜的杨氏模量增加30%(例如,~180GPa),同时将压缩应力降低约75%(例如,从约-1200降低到约-300MPa)。此外,与当前一代的纯碳硬掩模膜相比,PECVD加上离子植入的组合提供实现了显著更低的平面内畸变(<3纳米覆盖误差)的非晶碳膜。与当前一代的元素上是纯的非晶碳硬掩模膜相比,在本文中所述的所得的膜已经证明蚀刻选择性提高了大约30-50%,同时还符合先前的覆盖要求。
当介绍本公开内容的元素或其示例性方面或(多个)实施方式时,冠词“一(a)”、“一(an)”、“所述(the)”和“所述(said)”旨在表示存在一个或多个元件。
术语“包括(comprising)”、“包括(including)”和「具有(having)」旨在是包括性的,并且意味着可能存在除所列元素之外的其他元素。
虽然前述内容针对本公开内容的实施方式,但是可在不背离本公开内容的基本范围的情况下设计本公开内容的其他和进一步的实施方式,且本公开内容的范围由所附的权利要求书所确定。
Claims (15)
1.一种形成非晶碳膜的方法,包括:
在第一处理区域中的位于基座上的底层上沉积非晶碳膜;
通过在第二处理区域中将掺杂剂或惰性物质植入到所述非晶碳膜中来形成掺杂的非晶碳膜,其中所述掺杂剂或惰性物质选自碳、硼、氮、硅、磷、氩、氦、氖、氪、氙或它们的组合;
图案化所述掺杂的非晶碳膜;以及
蚀刻所述底层。
2.如权利要求1所述的方法,其中所述底层包括单个层或介电堆叠。
3.如权利要求1所述的方法,其中在所述底层上沉积所述非晶碳膜包括:
使含烃气体混合物流到所述第一处理区域中;以及
在所述第一处理区域中产生RF等离子体,以在所述底层上形成所述非晶碳膜。
4.如权利要求3所述的方法,其中在被定位于所述第一处理区域中的气体分配喷头与所述基座之间的距离在约200密耳和约1000密耳之间。
5.如权利要求4所述的方法,其中所述第一处理区域内的压力在约4托和约8托之间。
6.如权利要求1所述的方法,其中用于激励所述掺杂剂或惰性物质的植入能量在约5keV和约60keV之间。
7.如权利要求6所述的方法,其中离子剂量在约5x1013离子/cm2和约5x1016离子/cm2之间。
8.如权利要求6所述的方法,其中在植入所述掺杂剂或惰性物质期间的目标温度在约-100摄氏度和约500摄氏度之间。
9.一种形成非晶碳膜的方法,包括:
在第一处理区域中的位于基座上的底层上沉积非晶碳膜;
通过在第二处理区域中将掺杂剂或惰性物质植入到所述非晶碳膜中来形成掺杂的非晶碳膜,其中所述掺杂剂或惰性物质选自碳、硼、氮、硅、磷、氩、氦、氖、氪、氙或它们的组合;
图案化所述掺杂的非晶碳膜;以及
蚀刻所述底层,其中所述掺杂的非晶碳膜在633nm处具有从约2.1至约2.2的折射率。
10.如权利要求9所述的方法,其中所述掺杂的非晶碳膜具有在633nm处小于1.0的k值。
11.如权利要求9所述的方法,其中所述掺杂的非晶碳膜具有从约70至约200GPa的杨氏模量(GPa)。
12.如权利要求11所述的方法,其中所述掺杂的非晶碳膜具有从约14GPa至约22GPa的硬度(GPa)。
13.如权利要求12所述的方法,其中所述掺杂的非晶碳膜具有从约-600MPa至约0MPa的应力(MPa)。
14.如权利要求13所述的方法,其中所述掺杂的非晶碳膜具有从约1.95g/cc至约2.1g/cc的密度(g/cc)。
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CN113594031A (zh) * | 2021-07-29 | 2021-11-02 | 上海华力微电子有限公司 | 半导体器件的制备方法 |
CN114735625A (zh) * | 2022-04-13 | 2022-07-12 | 浙江大学杭州国际科创中心 | 一种非晶碳膜加工用惰性物质植入设备 |
CN114735625B (zh) * | 2022-04-13 | 2024-04-05 | 浙江大学杭州国际科创中心 | 一种非晶碳膜加工用惰性物质植入设备 |
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KR102612989B1 (ko) | 2023-12-11 |
US12014927B2 (en) | 2024-06-18 |
TW202325879A (zh) | 2023-07-01 |
JP2021504967A (ja) | 2021-02-15 |
KR20200084365A (ko) | 2020-07-10 |
CN116171337A (zh) | 2023-05-26 |
JP7326275B2 (ja) | 2023-08-15 |
US11469107B2 (en) | 2022-10-11 |
JP2023535772A (ja) | 2023-08-21 |
SG11202005150YA (en) | 2020-06-29 |
US20190172714A1 (en) | 2019-06-06 |
TW202212601A (zh) | 2022-04-01 |
US20200357640A1 (en) | 2020-11-12 |
WO2019108376A1 (en) | 2019-06-06 |
TW201932635A (zh) | 2019-08-16 |
JP2023162196A (ja) | 2023-11-08 |
US20230041963A1 (en) | 2023-02-09 |
KR20230169487A (ko) | 2023-12-15 |
US20230029929A1 (en) | 2023-02-02 |
WO2022026257A1 (en) | 2022-02-03 |
KR20230043858A (ko) | 2023-03-31 |
TWI791678B (zh) | 2023-02-11 |
US10727059B2 (en) | 2020-07-28 |
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