CN111344866B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN111344866B
CN111344866B CN201880058819.XA CN201880058819A CN111344866B CN 111344866 B CN111344866 B CN 111344866B CN 201880058819 A CN201880058819 A CN 201880058819A CN 111344866 B CN111344866 B CN 111344866B
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CN111344866A (zh
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登尾正人
石子雅康
斋藤顺
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Denso Corp
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H10D12/01—Manufacture or treatment
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/154—Dispositions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

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CN201880058819.XA 2017-09-14 2018-09-13 半导体装置及其制造方法 Active CN111344866B (zh)

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JP2017-176776 2017-09-14
JP2017176776A JP6870546B2 (ja) 2017-09-14 2017-09-14 半導体装置およびその製造方法
PCT/JP2018/034065 WO2019054459A1 (ja) 2017-09-14 2018-09-13 半導体装置およびその製造方法

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CN111344866B true CN111344866B (zh) 2023-06-16

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US11450734B2 (en) 2019-06-17 2022-09-20 Fuji Electric Co., Ltd. Semiconductor device and fabrication method for semiconductor device
CN112349771A (zh) * 2020-09-30 2021-02-09 湖南大学 一种碳化硅器件埋层型终端结构及其制备方法
CA3197226A1 (en) * 2020-11-06 2022-05-12 David Craig Mcgowan Oxindoles and methods of use thereof
JP7647104B2 (ja) 2021-01-06 2025-03-18 富士電機株式会社 半導体装置
JP7647239B2 (ja) 2021-03-30 2025-03-18 富士電機株式会社 半導体装置
JP7687035B2 (ja) * 2021-04-23 2025-06-03 富士電機株式会社 半導体装置
JP7697255B2 (ja) * 2021-04-27 2025-06-24 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP7647452B2 (ja) * 2021-08-31 2025-03-18 株式会社デンソー 半導体装置およびその製造方法
JP2023056697A (ja) * 2021-10-08 2023-04-20 株式会社デンソー 半導体装置およびその製造方法
JP2023088816A (ja) * 2021-12-15 2023-06-27 富士電機株式会社 炭化珪素半導体装置
CN114335141A (zh) * 2021-12-20 2022-04-12 深圳基本半导体有限公司 一种复合场限环终端结构及制备方法
JP2023102946A (ja) * 2022-01-13 2023-07-26 富士電機株式会社 炭化珪素半導体装置
CN115472495B (zh) * 2022-07-21 2024-05-31 上海林众电子科技有限公司 一种功率芯片终结区的制备方法及功率芯片的制备方法
CN115498013B (zh) * 2022-07-21 2024-04-26 上海林众电子科技有限公司 一种功率芯片终结区的制备方法、终结区的结构及功率芯片
CN115020240B (zh) * 2022-08-03 2023-03-28 上海维安半导体有限公司 一种低压超结沟槽mos器件的制备方法及结构
JP2024060452A (ja) * 2022-10-19 2024-05-02 株式会社デンソー 半導体装置とその製造方法
WO2025028616A1 (ja) * 2023-08-03 2025-02-06 ローム株式会社 半導体装置
CN117790537B (zh) * 2023-12-28 2024-10-25 深圳平湖实验室 一种半导体器件、其制作方法及电子器件

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JP2000022176A (ja) * 1998-06-30 2000-01-21 Toshiba Corp 電力用半導体装置
JP2001144292A (ja) * 1999-11-17 2001-05-25 Denso Corp 炭化珪素半導体装置
JP2008004643A (ja) * 2006-06-20 2008-01-10 Toshiba Corp 半導体装置
CN101872790A (zh) * 2009-04-27 2010-10-27 得诣科技股份有限公司 具有外延式护环的肖特基二极管元件及其制作方法
JP2014170778A (ja) * 2013-03-01 2014-09-18 Sumitomo Electric Ind Ltd 炭化珪素半導体装置
CN104380471A (zh) * 2012-06-13 2015-02-25 株式会社电装 碳化硅半导体装置及其制造方法
JP2015076592A (ja) * 2013-10-11 2015-04-20 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
EP3012870A1 (en) * 2014-10-20 2016-04-27 ABB Technology AG Edge termination for high voltage semiconductor devices
WO2016194280A1 (ja) * 2015-05-29 2016-12-08 株式会社デンソー 半導体装置およびその製造方法

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JP5224289B2 (ja) * 2009-05-12 2013-07-03 三菱電機株式会社 半導体装置
JP6231396B2 (ja) * 2014-02-10 2017-11-15 トヨタ自動車株式会社 半導体装置及び半導体装置の製造方法
JP6428489B2 (ja) 2014-09-16 2018-11-28 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP6740759B2 (ja) * 2016-07-05 2020-08-19 株式会社デンソー 炭化珪素半導体装置およびその製造方法

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Publication number Priority date Publication date Assignee Title
JP2000022176A (ja) * 1998-06-30 2000-01-21 Toshiba Corp 電力用半導体装置
JP2001144292A (ja) * 1999-11-17 2001-05-25 Denso Corp 炭化珪素半導体装置
JP2008004643A (ja) * 2006-06-20 2008-01-10 Toshiba Corp 半導体装置
CN101872790A (zh) * 2009-04-27 2010-10-27 得诣科技股份有限公司 具有外延式护环的肖特基二极管元件及其制作方法
CN104380471A (zh) * 2012-06-13 2015-02-25 株式会社电装 碳化硅半导体装置及其制造方法
JP2014170778A (ja) * 2013-03-01 2014-09-18 Sumitomo Electric Ind Ltd 炭化珪素半導体装置
JP2015076592A (ja) * 2013-10-11 2015-04-20 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
EP3012870A1 (en) * 2014-10-20 2016-04-27 ABB Technology AG Edge termination for high voltage semiconductor devices
WO2016194280A1 (ja) * 2015-05-29 2016-12-08 株式会社デンソー 半導体装置およびその製造方法

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US20200227549A1 (en) 2020-07-16
US10964809B2 (en) 2021-03-30
JP2019054087A (ja) 2019-04-04
JP6870546B2 (ja) 2021-05-12
CN111344866A (zh) 2020-06-26

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