JP6870546B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP6870546B2
JP6870546B2 JP2017176776A JP2017176776A JP6870546B2 JP 6870546 B2 JP6870546 B2 JP 6870546B2 JP 2017176776 A JP2017176776 A JP 2017176776A JP 2017176776 A JP2017176776 A JP 2017176776A JP 6870546 B2 JP6870546 B2 JP 6870546B2
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JP2019054087A (ja
JP2019054087A5 (enExample
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正人 登尾
正人 登尾
石子 雅康
雅康 石子
順 斎藤
順 斎藤
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Denso Corp
Toyota Central R&D Labs Inc
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Toyota Central R&D Labs Inc
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Priority to JP2017176776A priority Critical patent/JP6870546B2/ja
Priority to CN201880058819.XA priority patent/CN111344866B/zh
Priority to PCT/JP2018/034065 priority patent/WO2019054459A1/ja
Publication of JP2019054087A publication Critical patent/JP2019054087A/ja
Publication of JP2019054087A5 publication Critical patent/JP2019054087A5/ja
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01Manufacture or treatment
    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • H10D12/441Vertical IGBTs
    • H10D12/461Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
    • H10D12/441Vertical IGBTs
    • H10D12/461Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/665Vertical DMOS [VDMOS] FETs having edge termination structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107Buried supplementary regions, e.g. buried guard rings 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126Top-view geometrical layouts of the regions or the junctions
    • H10D62/127Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152Source regions of DMOS transistors
    • H10D62/154Dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393Body regions of DMOS transistors or IGBTs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/252Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Electrodes Of Semiconductors (AREA)
JP2017176776A 2017-09-14 2017-09-14 半導体装置およびその製造方法 Active JP6870546B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2017176776A JP6870546B2 (ja) 2017-09-14 2017-09-14 半導体装置およびその製造方法
CN201880058819.XA CN111344866B (zh) 2017-09-14 2018-09-13 半导体装置及其制造方法
PCT/JP2018/034065 WO2019054459A1 (ja) 2017-09-14 2018-09-13 半導体装置およびその製造方法
US16/816,463 US10964809B2 (en) 2017-09-14 2020-03-12 Semiconductor device and manufacturing process therefor

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Application Number Priority Date Filing Date Title
JP2017176776A JP6870546B2 (ja) 2017-09-14 2017-09-14 半導体装置およびその製造方法

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JP2019054087A5 JP2019054087A5 (enExample) 2020-02-27
JP6870546B2 true JP6870546B2 (ja) 2021-05-12

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450734B2 (en) 2019-06-17 2022-09-20 Fuji Electric Co., Ltd. Semiconductor device and fabrication method for semiconductor device
CN112349771A (zh) * 2020-09-30 2021-02-09 湖南大学 一种碳化硅器件埋层型终端结构及其制备方法
CA3197226A1 (en) * 2020-11-06 2022-05-12 David Craig Mcgowan Oxindoles and methods of use thereof
JP7647104B2 (ja) 2021-01-06 2025-03-18 富士電機株式会社 半導体装置
JP7647239B2 (ja) 2021-03-30 2025-03-18 富士電機株式会社 半導体装置
JP7687035B2 (ja) * 2021-04-23 2025-06-03 富士電機株式会社 半導体装置
JP7697255B2 (ja) * 2021-04-27 2025-06-24 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP7647452B2 (ja) * 2021-08-31 2025-03-18 株式会社デンソー 半導体装置およびその製造方法
JP2023056697A (ja) * 2021-10-08 2023-04-20 株式会社デンソー 半導体装置およびその製造方法
JP2023088816A (ja) * 2021-12-15 2023-06-27 富士電機株式会社 炭化珪素半導体装置
CN114335141A (zh) * 2021-12-20 2022-04-12 深圳基本半导体有限公司 一种复合场限环终端结构及制备方法
JP2023102946A (ja) * 2022-01-13 2023-07-26 富士電機株式会社 炭化珪素半導体装置
CN115472495B (zh) * 2022-07-21 2024-05-31 上海林众电子科技有限公司 一种功率芯片终结区的制备方法及功率芯片的制备方法
CN115498013B (zh) * 2022-07-21 2024-04-26 上海林众电子科技有限公司 一种功率芯片终结区的制备方法、终结区的结构及功率芯片
CN115020240B (zh) * 2022-08-03 2023-03-28 上海维安半导体有限公司 一种低压超结沟槽mos器件的制备方法及结构
JP2024060452A (ja) * 2022-10-19 2024-05-02 株式会社デンソー 半導体装置とその製造方法
WO2025028616A1 (ja) * 2023-08-03 2025-02-06 ローム株式会社 半導体装置
CN117790537B (zh) * 2023-12-28 2024-10-25 深圳平湖实验室 一种半导体器件、其制作方法及电子器件

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000022176A (ja) * 1998-06-30 2000-01-21 Toshiba Corp 電力用半導体装置
JP4450122B2 (ja) * 1999-11-17 2010-04-14 株式会社デンソー 炭化珪素半導体装置
US7737469B2 (en) 2006-05-16 2010-06-15 Kabushiki Kaisha Toshiba Semiconductor device having superjunction structure formed of p-type and n-type pillar regions
JP5188037B2 (ja) * 2006-06-20 2013-04-24 株式会社東芝 半導体装置
CN101872790A (zh) * 2009-04-27 2010-10-27 得诣科技股份有限公司 具有外延式护环的肖特基二极管元件及其制作方法
JP5224289B2 (ja) * 2009-05-12 2013-07-03 三菱電機株式会社 半導体装置
JP5812029B2 (ja) * 2012-06-13 2015-11-11 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP6075120B2 (ja) * 2013-03-01 2017-02-08 住友電気工業株式会社 炭化珪素半導体装置
JP2015076592A (ja) * 2013-10-11 2015-04-20 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP6231396B2 (ja) * 2014-02-10 2017-11-15 トヨタ自動車株式会社 半導体装置及び半導体装置の製造方法
JP6428489B2 (ja) 2014-09-16 2018-11-28 株式会社デンソー 炭化珪素半導体装置およびその製造方法
EP3012870A1 (en) * 2014-10-20 2016-04-27 ABB Technology AG Edge termination for high voltage semiconductor devices
JP6409681B2 (ja) * 2015-05-29 2018-10-24 株式会社デンソー 半導体装置およびその製造方法
JP6740759B2 (ja) * 2016-07-05 2020-08-19 株式会社デンソー 炭化珪素半導体装置およびその製造方法

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WO2019054459A1 (ja) 2019-03-21
US20200227549A1 (en) 2020-07-16
US10964809B2 (en) 2021-03-30
JP2019054087A (ja) 2019-04-04
CN111344866A (zh) 2020-06-26
CN111344866B (zh) 2023-06-16

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