CN110178212A - 堆栈基板的处理 - Google Patents

堆栈基板的处理 Download PDF

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CN110178212A
CN110178212A CN201780083260.1A CN201780083260A CN110178212A CN 110178212 A CN110178212 A CN 110178212A CN 201780083260 A CN201780083260 A CN 201780083260A CN 110178212 A CN110178212 A CN 110178212A
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substrate
sacrificial layers
layer
residue
wiring layer
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CN110178212B (zh
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赛普里恩·艾米卡·乌佐
高桂莲
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Anglo Sai Bond Technology Co Ltd
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Abstract

代表性实施方案提供用于处理集成电路(IC)晶粒及相关装置以为堆栈及接合该些装置作准备的技术。该些所揭示技术提供在保护底层的同时将处理残余物自装置表面移除。一或多个牺牲层可在处理期间涂覆至该装置的一表面以保护该些底层。处理残余物附着至该些牺牲层而非该装置，且可与该些牺牲层一起被移除。

Description

堆栈基板的处理
相关申请案的交叉参考
本申请案依照35U.S.C.§119(e)(1)主张2017年12月19日申请的美国临时申请案第15/846,731号以及2016年12月28日申请的美国临时申请案第62/439,771号的权益，该案以全文引用的方式并入本文中。
技术领域
以下描述是关于集成电路(「IC」)的处理。更明确而言，以下描述是关于将处理残余物自晶粒、晶圆及其他基板的表面移除。
背景技术
对于诸如整合式芯片及晶粒的微电子组件的更紧凑实体配置的需要随着携带型电子装置的快速发展、物联网的扩展、纳米级整合、次波长光学整合等等已变得愈发强烈。仅借助于实例，装置通常被称作整合具有大功率数据处理器的蜂巢式电话、内存及诸如全球定位系统接收器的辅助装置、电子摄影机及局域网络连接件以及高分辨率显示器及相关联的图像处理芯片的功能的「智能电话」。这些装置可提供诸如完全因特网连接、娱乐(包括全分辨率视讯、导航、电子银行等)的性能，所有均在口袋大小的装置中。复杂的携带型装置需要将众多芯片及晶粒封装至较小空间中。
微电子组件常常包含诸如砷化硅或砷化镓的半导体材料的薄平板。芯片及晶粒通常经设置为个别预封装单元。在一些单元设计中，将晶粒安装至基板或芯片载体，随后将该基板或芯片载体安装于电路面板(诸如，印刷电路板(PCB))上。晶粒可经设置于便于在制造期间及在将晶粒安装于外部基板上期间对晶粒的处置的封装中。举例而言，许多晶粒经设置于适合于表面安装的封装中。此通用类型的众多封装经提议用于各种应用。最常见地，这些封装包括介电质组件，其通常被称作具有形成为介电质上的经镀覆或经蚀刻金属结构的端子的「芯片载体」。通常借由诸如沿晶粒载体延伸的薄迹线的导电特征及借由在晶粒的接触件与端子或迹线的接触件之间延伸的精细引线或电线将端子连接至晶粒的接触件(例如，接合垫)。在表面安装操作中，可将封装置放至电路板上，以使得封装上的每一端子与电路板上的对应接触垫对准。将焊料或其他接合材料设置于端子与接触垫之间。可借由加热装配件以便熔化或「回焊」焊料或以其他方式活化接合材料来将封装永久地接合在适当的位置。
通常被称作「芯片级封装」的某些封装占据等于或仅略大于并入于封装中的装置的面积的电路板的面积。这种比例是有利的，因为其降低装配件的整体大小且准许在基板上的各种装置之间使用短互连件，此随后限制装置之间的信号传播时间且因此便于以高速操作装配件。
半导体晶粒亦可经设置于「堆栈」配置中，举例而言，其中一个晶粒设置于载体上，且另一晶粒安装在第一晶粒的上方。这些配置可允许将多个不同晶粒安装于电路板上的单个覆盖面积内，且可进一步借由在晶粒之间设置短互连件来便于高速操作。通常，此互连距离可仅略大于晶粒自身的厚度。对于将在晶粒封装的堆栈内达成的互连，用于机械及电气连接的互连结构可设置于每一晶粒封装(除了最顶封装)以外的两侧(例如，面)上。此已(例如)借由在安装有晶粒的基板的两侧上设置接触垫或焊盘来得以实现，该些衬垫借由导电通孔或类似者经过基板连接。堆栈芯片配置及互连结构的实例提供于美国专利申请公开案第2010/0232129号中，该公开案揭示内容以引用的方式并入本文中。
然而，晶粒或装置的表面彼此紧密接触或邻近的一些堆栈配置对于堆栈芯片的一个或两个表面上粒子或污染物(例如，大于.5纳米)的存在是敏感的。举例而言，自处理步骤剩余的粒子可产生堆栈芯片之间的不良接合区域。对于处理或处置而言，晶粒及基板的暂时接合可能尤其是有问题的，这是因为暂时载体及基板的移除可留下接合层残余物。
来自暂时接合层的残余物(其可由高温聚合物组成)可具有不同厚度(例如，厚度可介于50纳米至30微米之范围内)在基板表面上不连续。电浆灰化可用以移除薄残余物，但即使较长的氧电浆灰化步骤(例如，历时40分钟)仍可能不会移除最厚残余物，且在许多情况下，可氧化导电互连层(例如，铜互连层)。在此等状况下，高温(例如，50℃以上)湿式制程有时用以移除厚残余物；然而，该制程可并不与其他晶粒层或材料兼容。举例而言，高温湿式制程可劣化经抛光金属层的平滑度，从而降低装置良率。
发明内容
代表性实施方案提供用于处理集成电路(integrated circuit；IC)晶粒及相关装置以为堆栈及接合该些装置作准备的技术。经处理装置可留下表面残余物，从而不利地影响接合。所揭示技术在保护底层的同时改良自装置表面的残余物移除。一或多个牺牲层可在处理期间涂覆至该装置的一表面以保护该些底层。处理残余物附着至该些牺牲层而非该装置，且可与该些牺牲层一起被移除。
在各种实施中，实例制程包括湿式蚀刻装置的表面以移除牺牲层及残余物。在一些具体实例中，多个牺牲层中的一或多个在不同处理阶段被移除以在处理阶段期间保护底层。在一些实例中，选择性蚀刻剂(湿式蚀刻剂)可用于移除一或多个牺牲层及残余物而不损害装置的表面或损害装置的表面上的金属互连结构。
参考电气及电子组件及变化的载体论述各种实施及配置。虽然提及特定组件(亦即，晶圆、集成电路(IC)芯片晶粒等)，但此并非意欲为限制性，且为了易于论述及说明方便。参考晶圆、晶粒或其类似物论述的技术及装置适用于任一类型或数目的电气组件、电路(例如，集成电路(IC)、混合电路、ASIC、内存装置、处理器等)、组件的群组、封装的组件、结构(例如，晶圆、面板、板、PCB等)及类似的，其可经耦接以彼此介接，与外部电路、系统、载体及类似物介接。该些不同组件、电路、群组、封装、结构及类似者中的每一个可通常被称作「微电子组件」。为简单起见，该些组件另外将在本文中被称作「晶粒」或「基板」。
使用图形流程图说明所揭示制程。描述所揭示制程所按的次序并非意欲解释为限制性，且任何数目个所描述制程区块可按任何次序组合以实施制程或替代制程。另外，可在不脱离本文中所描述主题的精神及范畴的情况下自制程删除个别区块。另外，在不脱离本文中所描述主题的范畴情况下，所揭示制程可在任何合适的制造或处理装置或系统，以及任一硬件、软件、固件或其一组合中实施。
在下文使用多个实例来更详细地解释实施方案。尽管在此处且在下文论述各种实施方案及实例，但其他实施方案及实例可借由组合个别实施方案及实例的特征及组件而来成为可能。
附图说明
参考附图阐述实施方式。在图式中，参考数字的最左侧数字识别首次出现该参考数字图。在不同图中使用同一参考数字指示类似或相同对象。
对此论述，在图式中所说明的装置及系统展示为具有大量组件。如本文中所描述，装置及/或系统的各种实施方案可包括更少组件且保持在本发明的范畴内。替代地，装置及/或系统的其他实施方案可包括额外组件，或所描述组件的各种组合，且保持在本发明的范畴内。
图1为说明实例晶粒进程列的经示意性说明的流程图。
图2及图3展示根据第一具体实例的说明实例晶粒进程列的经示意性说明之流程图。
图4及图5展示根据第二具体实例的说明实例晶粒进程列的经示意性说明的流程图。
具体实施方式
概述
揭示了用于处理集成电路(IC)晶粒及相关装置以为堆栈及接合该些装置作准备的技术的各种具体实例。经历处理的装置可自制程步骤留下表面残余物，从而不利地影响接合。所揭示技术在保护底层的同时改良自装置表面的残余物移除。
在各种具体实例中，使用所揭示技术可简化用于最小容限堆栈及接合技术的堆栈制程，减少晶粒制造及处理成本并改良利润率，减少暂时接合操作的缺陷，允许较高堆栈装置良率，消除关键制程缺陷，且可减少晶粒的处置以最小化粒子产生。使用不需黏着剂的表面至表面直接接合技术(诸如)及/或混合式接合(诸如「直接接合互连」)(两者可自Ziptronix公司、Xperi技术公司获得(例如参看美国专利第6,864,585号及第7,485,968号，该些专利全文并入本文中))来堆栈及接合晶粒可尤其有益，其可归因于对于极平坦接口的需要而对粒子及污染物敏感。相对绝缘体、半导体及/或导体层之间的粒子的移除改良表面的平坦度，及相应地改良接合两个表面的能力。
举例而言，在图1处展示以图形方式说明的流程图，其说明实例晶粒进程列100。在区块(A)处，制程开始于借由使用暂时接合层106将一处置基板104接合至包括一或多个装置(装置未图标)的基板102而制备基板装配件。基板102的配线层108由金属(诸如铜等)组成，且借由接合层106接触。在各种实例中，接合层106由高温聚合物、环氧树脂、聚酰亚胺、丙烯酸或其类似物组成以确保处置基板104在处理期间保持接合至装置102。
在区块(B)处，基板102的背侧的一部分是使用一或多种技术(例如，研磨、化学机械抛光/平坦化(chemical mechanical polishing/planarizing；CMP)、反应性离子蚀刻(reactive-ion etching；RIE)等)而移除至所要尺寸。变薄基板102的背侧可经进一步处理以(例如)形成互连配线层、被动组件层或所关注的其他结构或特征。在区块(C)处，具有一或多个装置的基板102附着至切割薄片110以用于单一化。处置基板104现在在「顶侧」，以准备将其移除。
在区块(D)处，处置基板104可借由研磨、蚀刻、抛光、滑落或借由暂时接合黏着层106的光学劣化等而移除。在区块(E)处，移除暂时接合层106。如在区块(E)处所示，移除制程通常留下某一残余物112。残余物112可具有不同厚度(例如，厚度可介于5纳米至30微米或甚至更高范围内)。电浆灰化可用以移除薄残余物112，但即使较长的氧电浆灰化步骤(例如，历时40分钟)仍可能不会移除最厚残余物112，且在许多情况下，可氧化配线层108(例如，铜互连层108)。较长灰化时间亦可使外露配线层108的表面变粗糙，此可降低接合装置良率。在一些状况下，高温(例如，50℃以上)湿式蚀刻制程用以移除厚残余物112；然而，该制程可并不与其他晶粒层或材料兼容。举例而言，高温湿式制程可溶解配线层108的导电金属表面部分，因此使金属配线层108劣化，移除比所需要更多的金属且留下粗糙表面构形(topography)。在一些低容限接合方法(诸如及「直接接合互连」)中，需要(例如，配线层108的)金属构形具有小于10纳米方差以用于成功接合。
在区块(F)处，基板102经单一化成晶粒114。如所示，残余物112可保持于晶粒114上，从而潜在地导致不良接合，及减少产品良率。
实例实施方案
在各种实施方案中，一或多个保护层可在接合载体或处置基板至敏感层之前涂覆至敏感装置层。保护(牺牲)层的移除亦移除在移除接合层时留下的任何残余物。在各种具体实例中，可使用不损害基础敏感绝缘及导电层的室温或接近室温制程移除保护层。
举例而言，图2及图3展示根据第一具体实例的说明实例晶粒进程列200以图形方式说明的流程图。如图2中在区块(A)处所示，在施加暂时黏着剂106及处置基板104之前，薄无机保护层202形成(例如，旋涂)于基板102的配线层108上。在各种具体实例中，保护层202可包含以下各者中的一或多种：二氧化硅(SiO2)、掺杂硼的二氧化硅(亦即，B-SiO2)、掺杂磷的二氧化硅(亦即，P-SiO2)或其类似物。在其他具体实例中，保护层202可包含借由较低温度电浆增强式化学气相沉积(plasma enhanced chemical vapor deposition；PECVD)、原子层沉积(atomic layer deposition；ALD)、电浆增强原子层沉积(plasma enhancedatomic layer deposition；PEALD)或类似方法涂布的非化学计量介电质材料(非装置质量介电质材料)。保护层202可在一些具体实例中小于50纳米厚(在其他具体实例中，更厚或更薄)。作为制程的部分，取决于涂布制程的性质，保护层202可在低于100℃温度下在惰性气体或真空中历时大致30分钟固化。在各种其他实施方案中，固化温度及时间以及周围环境可变化。在一些状况下，保护层202可随后在添加黏着层106之前用电浆辐射处理。
在区块(B)处，包括一或多个装置(装置未图标)的基板102是使用暂时黏着剂106接合至处置基板104，如上文所描述。在实例制程200中，结合层106接触保护(牺牲)层202而非接触金属配线层108。以此方式，敏感金属配线层108受到保护而免于黏着剂106及其残余物112的影响。在区块(C)处，基板102根据所意欲的应用的需要而减少且根据需要被进一步处理。在区块(D)处，减少的基板102附着至切割薄片110，其中处置基板104在顶侧。
在区块(E)处，处置基板104被移除，且在区块(F)处，暂时结合层106被移除，从而留下残余物112。在此实例制程200中，残余物112留在保护层202而非金属配线层108上。在一些其他具体实例中，不合需要的残余物112可为来自切割薄片或研磨薄片黏着剂的残余物。不管不合需要的残余物112的来源，利用基板102的装置以不合需要的残余物112与保护牺牲层202接触的此序列而形成。
参考图3，制程200继续。为了连续性及易于论述，再次在图3中说明区块(F)。作为可选制程步骤，在区块(F)处残余物112可持续小于例如10分钟暴露在氧电浆中以移除较薄残余物112。在具体实例中，电浆暴露亦可增加亲水性且使所涂布无机保护层202中的接合变弱，且使得保护层202及残余物112更易于自基板102除去。在区块(G)处，基板102经单一化成晶粒114。如在区块(G)处所示，残余物112可在单一化之后保持(或另外累积)于晶粒114上、保护层202上。
在区块(H)处，举例而言，具有小于2％及较佳地小于0.2％的氟化物离子浓度的湿式稀释蚀刻剂302(例如，缓冲氧化物蚀刻剂(buffered oxide etchant；BHF)、氢氟酸(hydrofluoric acid；HF)、糖化稀释(glycated dilute)BFH或HF或其类似者)经喷射至晶粒114上以分解并移除无机保护层202。在一些具体实例中，较佳地蚀刻剂302包括错合剂(complexing agent)以抑制在保护层202下方的配线层108中的金属的蚀刻。错合剂可包含例如具有三唑部分的错合剂或其类似物，其中导电金属为铜。湿式蚀刻剂302可借由自旋制程(如所说明)、另一分批制程或其类似者而视需要历时预选持续时间来涂覆。错合剂可在后续清除操作中用合适的溶剂(例如含有醇的溶剂)移除。
在区块(I)处，经单一化晶粒114经展示不含残余物112。保护层202的移除亦自晶粒114的表面移除残余物112而不使晶粒114的配线层108劣化。在具体实例中，如在区块(J)及区块(K)处所示，一或多个额外无机(或有机，在替代具体实例中)保护层304展示为先前已被添加至基板102的第二(相对)表面。举例而言，在各种实施中，额外保护层304可视情况被添加至基板102的第二表面以在各种制程期间保护基板102。保护层304可在将基板102定位至切割薄片上之前被添加，例如(参看区块(D))。在此具体实例中，保护层304可保护基板102的第二表面以免受与切割薄片相关联的残余物或黏着剂影响，或可便于自基板102的第二表面清除此类残余物。在区块(J)处，基板102经展示为经单一化成晶粒114且在区块(K)处基板102展示为完整。
根据各种具体实例，在图4及图5处展示另一实例晶粒进程列400。在具体实例中，两个或大于两个保护层202及402在黏着剂106之前经涂覆至金属配线层108。在具体实例中，配线层108受有机保护层402(诸如有机光阻或其类似者)保护，且有机保护层402在将处置基板104接合至基板102之前受无机保护(牺牲)层202保护，如上文所论述。在具体实例中，额外保护层(诸如保护层402)的使用允许在外露层被处理的同时底层(诸如配线层108)受到保护。举例而言，额外有机保护层402允许使用化学品及/或可对配线层108有害(例如，腐蚀、粗糙化、干涸)的技术来移除保护层202。
参考图4，在区块(A)处，包括一或多个装置(装置未图标)的基板102最初在配线层108上涂布有薄(例如，旋涂)有机保护层402，继之以较薄无机保护层202(例如，SiO2、B-SiO2、p-SiO2及类似物)涂布，如上文所描述。
在区块(B)处，基板102是使用暂时接合106而接合至处置基板104，如上文所描述。另外，在此实例中，结合层106接触保护(牺牲)层202而非接触金属配线层108或有机层402。在区块(C)处，基板102视需要而减少，且在区块(D)处，减少基板102附着至切割薄片110，其中处置基板104在顶侧。
在区块(E)处，处置基板104被移除，且在区块(F)处，暂时结合层106被移除，从而大体留下残余物112。另外，在此实例中，残余物112留在保护层202而非金属配线层108或有机层402上。
参考图5，制程400继续。为了连续性及易于论述在图5中再现区块(F)。视情况，在区块(F)处，残余物112可例如持续小于10分钟暴露在氧电浆中以移除较薄残余物112层及亦增加亲水性并使涂布无机保护层202中的接合变弱。此可使得保护层202及残余物112更易于自基板102除去。在区块(G)处，基板102视情况经单一化成晶粒114。如所示，残余物112可保持于晶粒114上，保持于保护层202上。在区块(H)处，湿式稀释蚀刻剂302(例如，缓冲氧化物蚀刻剂(BHF)、氢氟酸(HF)或其类似物)喷射至晶粒114上以分解及移除无机保护层202。湿式蚀刻剂302可借由自旋制程或其类似物而视需要历时预选持续时间来涂覆。有机保护层402保持在晶粒114上。
在区块(I)处，单一化晶粒114经展示实质上不含残余物112。保护层202的移除亦自晶粒114的表面移除残余物112而至少部分归因于配线层108上的有机保护层402不使配线层108劣化。在具体实例中，如在区块(J)及区块(K)处所示，一或多个额外无机或有机保护层304经展示为先前已被添加至基板102的第二(相对)表面。举例而言，在各种实施中，额外保护层304可视情况被添加至基板102的第二表面以在各种制程期间保护基板102。保护层304可在将基板102定位至切割薄片上之前被添加，例如(参看区块(D))。在此具体实例中，保护层304可保护基板102的第二表面免受与切割薄片相关联的残余物或黏着剂影响，或可便于自基板102的第二表面清除此类残余物。在区块(J)处，基板102经展示为经单一化成晶粒114且在区块(K)处基板102展示为完整。
在一个具体实例中，在例如如图1中在区块(E)处、图3中在区块(F)处及图5中在区块(F)处所描绘移除暂时接合层106之后，不合需要的残余物112可在单一化步骤之前借由移除层202而移除。换言之，基板102可在具有或不具有保护层202的情况下经单一化。举例而言，基板102可在单一化步骤之前用保护层(诸如层202)涂布，以在单一化期间防止来自机械切割(例如，锯割)的切割碎片黏着至配线层108，并允许切割碎片连同保护层202一起被移除。
在各种具体实例中，其他保护层组合(及任何数目个保护层)可用于保护底层免受制程步骤的影响。举例而言，每一保护层可以化学方式工程化以被选择性地移除，同时在被移除的保护层下方的层保护底层(诸如配线层108)。有机层可为疏水性或亲水性以充当所使用溶剂的亲和性。举例而言，两层组合可包括两个光阻层、一个疏水层及一个无机层，或其类似的。三个或三个以上保护层的组合亦可以类似于每一层用以保护下部层以免于处理的负面影响的方式而使用。一般而言，确保配线层108不会因金属移除或构形的粗糙而劣化一或多个保护层的目标。在各种具体实例中，在湿洗步骤之后，经处理基板或晶粒可在接合至另一清洁介电质表面之前经进一步处理。
结论
尽管已以特定针对于结构特征及/或方法行动的语言描述本发明的实施方案，但应理解，实施方案不一定限于所描述特定特征或行动。确切而言，将特定特征及行动揭示为实施实例装置及技术的代表性形式。
本文的每项权利要求构成单独具体实例，且组合不同权利要求的具体实例及/或不同具体实例在本发明的范畴内，且一般熟习此项技术者在查阅本发明之后将显而易见。

Claims (20)

1.一种形成微电子装配件的方法，其包含：
提供具有外露的导电配线层的基板；
用一或多个保护牺牲层涂布该导电配线层；
使用暂时接合层将处置基板接合至该一或多个保护牺牲层；
在该处置基板接合至该基板的同时处理该基板；
移除该处置基板；
移除该暂时接合层；
将该基板、该一或多个保护牺牲层及该暂时接合层的残余物暴露在湿式蚀刻剂中维持预选的持续时间，该湿式蚀刻剂分解该些保护牺牲层中的一或多个；及
自该导电配线层中清洗掉该些保护牺牲层中的一或多者及该残余物。
2.如权利要求1所述的方法，其进一步包含在将该基板、该一或多个保护牺牲层及该残余物暴露在该湿式蚀刻剂中之前，将该基板、该一或多个保护牺牲层及该残余物暴露在氧电浆辐射中维持预选的持续时间以修改该一或多个保护牺牲层的湿气吸收特性。
3.如权利要求1所述的方法，其进一步包含用有机或无机保护层涂布该基板的与该导电配线层相对的表面。
4.如权利要求1所述的方法，其中该处理包括在该处置基板接合至该基板的同时自该基板的与该导电配线层相对的表面移除该基板的一部分。
5.如权利要求1所述的方法，其中该些保护牺牲层中的一或多个包含无机二氧化硅(SiO2)、掺杂硼的二氧化硅(B-SiO2)或掺杂磷的二氧化硅(P-SiO2)材料。
6.如权利要求1所述的方法，其中该一或多个保护牺牲层包含在该导电配线层上的有机保护层及在该有机保护层上的无机保护层，该有机保护层适用于保护该导电配线层以免因该无机保护层及该残余物的移除而劣化。
7.如权利要求1所述的方法，其中该湿式蚀刻剂包含缓冲氧化物蚀刻剂(BHF)或氢氟酸(HF)。
8.如权利要求1所述的方法，其中该湿式蚀刻剂包含适用于抑制该导电配线层的溶解的错合剂。
9.如权利要求1所述的方法，其中该些保护牺牲层中的该一或多个是使用旋涂、电浆物理气相沉积(PVD)或使用电泳制程来涂覆。
10.如权利要求1所述的方法，其中该基板在移除该牺牲保护层之前经单一化。
11.如权利要求1所述的方法，其中该基板在移除该牺牲保护层之后经单一化。
12.如权利要求1所述的方法，其中该导电配线层不会因暴露在该湿式蚀刻剂中而劣化、粗糙化或腐蚀。
13.一种形成微电子装配件的方法，其包含：
提供具有外露配线层的基板；
用一或多个保护牺牲层涂布该配线层；
处理该基板；
将该基板、该一或多个保护牺牲层及该处理的残余物暴露在湿式蚀刻剂中维持预选的持续时间，该湿式蚀刻剂分解该些保护牺牲层中的一或多个；及
自该配线层中清洗掉该些保护牺牲层中的一或多个及该残余物。
14.如权利要求13所述的方法，其中处理该基板进一步包含：
使用暂时接合层将暂时基板接合至该一或多个保护牺牲层；
在该暂时基板接合至该一或多个保护牺牲层的同时处理该基板；及
移除该暂时基板及该暂时接合层。
15.如权利要求13所述的方法，其进一步包含借由移除该一或多个保护牺牲层而移除该处理的残余物。
16.如权利要求13所述的方法，其进一步包含用该湿式蚀刻剂移除该处理的残余物而不劣化、粗糙化或腐蚀该配线层。
17.如权利要求13所述的方法，其进一步包含移除该处理的残余物而不将该配线层暴露在该湿式蚀刻剂中。
18.如权利要求13所述的方法，其进一步包含在移除该些保护牺牲层中的一或多个之前单一化该基板。
19.一种形成微电子装配件的方法，其包含：
提供具有外露的导电配线层的基板；
用一或多个保护牺牲层涂布该导电配线层；
使用暂时接合层将处置基板接合至该一或多个保护牺牲层；
在该处置基板接合至该基板的同时处理该基板；
移除该处置基板；
移除该暂时接合层；
将该基板、该一或多个保护牺牲层及该暂时接合层的残余物暴露在氧电浆辐射中维持预选的持续时间以修改该些保护牺牲层中的一或多个的湿气吸收特性；
将该基板、该一或多个保护牺牲层及该残余物暴露在湿式蚀刻剂中维持预选的持续时间，该湿式蚀刻剂分解该些保护牺牲层中的一或多个；及
自该导电配线层中清洗掉该些保护牺牲层中的一或多个及该残余物。
20.如权利要求19所述的方法，其进一步包含在保护下方的底层的同时选择性地移除该保护牺牲层。
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