CN109844943B - 改善散热及电磁波屏蔽功能的层压石墨的膜上芯片型半导体封装 - Google Patents
改善散热及电磁波屏蔽功能的层压石墨的膜上芯片型半导体封装 Download PDFInfo
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Abstract
本发明涉及一种膜上芯片型半导体封装及包括其的显示设备,所述膜上芯片型半导体封装包括:集成电路芯片;印制电路板层及石墨层,所述集成电路芯片直接或通过贴装器件连接到所述印制电路板层的一面上,所述石墨层层压在所述印制电路板层的相反一面上。
Description
技术领域
本发明涉及一种作为驱动显示设备、显示器的主要部件的层压石墨的膜上芯片型半导体封装。
本申请要求于2017年8月21日向韩国专利局提交的韩国专利申请号为10-2017-0105442的优先权,其所有内容均包括在本说明书中。
背景技术
近年来,随着对大分辨率显示器的关注度高涨,在操作驱动集成电路,尤其,在操作显示器驱动集成电路芯片(Display Driver Integrated circuit Chip)时,随着发热量增加,温度上升到操作范围以上,由此影响显示器的画质,或者阻碍显示器的正常操作,或者因高温而损坏,因此还会缩短寿命。
针对所述大分辨率显示器,到目前为止试图以其他方式实现散热效果,但其效果逐渐到达瓶颈,因此需要更具创新性的方式。
并且,在以智能手机为代表的移动电话以及性能高度化的电视(TV)及计算机中,相应模块中的射频(RF)相关模块所产生的电磁干扰(electromagnetic interference,EMI)或在高速操作的集成电路芯片中产生的电磁波干扰影响到驱动集成电路,从而在液晶面板或有机发光二极管(OLED)面板中产生噪音,或者经常出现变色问题,并且,相比于以前,液晶显示器(LCD)画面非常大,画面频率变得非常高速化,因此,由于细微的电磁波干扰的影响,可能在画面上产生很大的噪点。
并且,液晶显示器驱动集成电路相比较于以前,特性变高度化而以高速和高频率操作,因此发生由驱动集成电路自身产生的EMI影响显示器的画质或者影响其他集成电路芯片的情况。
因此,需要一种屏蔽技术,以保护显示器驱动集成电路免受电磁波干扰,或者保护其他集成电路芯片免受显示器驱动集成电路中产生的电磁波干扰。
发明内容
(一)要解决的技术问题
本发明是为了改善并解决在操作大分辨率显示器的驱动集成电路芯片时产生的散热问题及电磁波干扰问题而提出的,并且其目的在于提供一种能够对驱动集成电路芯片中产生的热有效进行散热的膜上芯片型半导体封装及包括其的显示设备。
(二)技术方案
本发明提供一种膜上芯片型半导体封装,包括:集成电路芯片;印制电路板层;及石墨层,所述集成电路芯片直接或通过贴装器件连接到所述印制电路板层的一面,所述石墨层层压在所述印制电路板层的相反一面上。
并且,本发明提供一种显示设备,包括:所述膜上芯片型半导体封装;基板;及显示器面板。
(三)有益效果
本发明的膜上芯片型半导体封装及包括其的显示设备可以将影响显示器的操作及画质的集成电路芯片的热向外部方向散发,从而使其影响最小化。
并且,通过防止集成电路芯片的温度过高来使操作稳定在最佳状态,显示器的画质也保持在最佳状态,并且,减少由于驱动集成电路芯片的温度过高而导致的损坏,增加驱动集成电路芯片的寿命,从而也能够延长显示器的寿命。
具体地,石墨层压在印制电路板,因此不仅将电路部件所产生的热向相反一面方向快速散发的效果优异,而且由于石墨本身的导电特性,电磁波干扰屏蔽效果优异,使得显示器驱动集成电路芯片的功能不会劣化而保持恒定,并且,也能够防止其他集成电路芯片的功能的劣化。
因此,持续保持显示器的画质的同时,增加驱动集成电路芯片的寿命,从而还能够延长显示器的寿命。
并且,本发明的一个实施例的膜上芯片型半导体封装在键合操作时,即使石墨已被层压,通过改善膜的相反一侧的视觉外观性,在石墨层方向上也能够用肉眼确认膜的相反一侧的外引线键合垫,从而在与膜上芯片型半导体封装和显示器基板等的粘合工艺时,能够改善粘合的准确度及粘合的强度。
附图说明
图1是示出印制电路板层202的基材部103方向的一面上层压有石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图2是集成电路芯片101直接或通过贴装器件109连接到所述印制电路板层202的一面的结构的膜上芯片型半导体封装的上部方向的平面图。
图3是层压有石墨层的膜上芯片型半导体封装的下部方向的平面图。
图4是示出在基材部103的一面上设有电路图案层102的一般的印制电路板层202的图。
图5是示出在如图4所示的印制电路板层202的基材部103方向的一面上,将石墨粉末302设置在粘合层104上之后,利用轧辊301向电路图案层102及基材部103两个方向施压,从而将石墨层106层压在印制电路板层202的一面上的工艺的图。
图6是示出在如图4所示的印制电路板层202的基材部103方向的一面上,将石墨膜401设置在粘合层104上之后,利用轧辊301向电路图案层102及基材部103两个方向施压,从而将石墨层106层压在印制电路板层202的一面上的工艺的图。
图7是示出在印制电路板层202的基材部103方向的一面上层压有石墨层106的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图8是示出在印制电路板层202的基材部103方向的一面上依次层压有粘合层104和石墨层106的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图9是示出在印制电路板层202的基材部103方向的一面上层压有石墨层106,在石墨层106的基材部103的相反方向的一面上依次层叠粘合层107和保护膜层108的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图10是示出在印制电路板层202的基材部103方向的一面上依次层压粘合层104和石墨层106,在石墨层106的基材部103的相反方向的一面上依次层叠粘合层107和保护膜层108的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图11是在印制电路板层202的基材部103方向的一面上层叠粘合层104、保护膜层105,在所述保护膜层105的所述基材部103方向的一面上层压有石墨层106的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图12是图8的印制电路板层202的基材部103方向的一面上依次层压有粘合层104和石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图13是图9的印制电路板层202的基材部103方向的一面上层压有石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图14是示出图10的印制电路板层202的基材部103方向的一面上依次层压有粘合层104和石墨层106,石墨层106的基材部103的相反方向的一面上依次层叠粘合层107和保护膜层108的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图15是示出图11的印制电路板层202的基材部103方向的一面上层叠粘合层104、保护膜层105,所述保护膜层105的所述基材部103方向的一面上层压有石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图16是在印制电路板层202的一面上直接或通过贴装器件109连接的集成电路芯片101和外引线键合垫204以与所述集成电路芯片的长度方向垂直的方向设置的膜上芯片型半导体封装的上部方向的平面图。
图17是所述外引线键合垫204以与集成电路芯片101的长度方向垂直的方向设置,所述石墨层106在除了设置所述外引线键合垫的所述印制电路板层202的面积的另一面的面积中,隔开两个以上而层压的膜上芯片型半导体封装的层压石墨层的下部方向的平面图。
图18是在印制电路板层202的石墨层隔开两个以上而层压的一面上直接或通过贴装器件109连接的集成电路芯片101和外引线键合垫204以与所述集成电路芯片的长度方向垂直的方向设置的膜上芯片型半导体封装的上部方向的平面图。
具体实施方式
下面,参照附图对本发明的膜上芯片型半导体封装及其制造方法的实施例进行详细说明,以使本发明所属技术领域的普通技术人员能够容易实施。
下面,参照附图对本发明的膜上芯片型半导体封装及其制造方法进行说明。
下面,通过实施例说明本发明的结构及特性,但是,所述实施例仅仅例示本发明,而并不限定本发明。
下面,参照图1说明膜上芯片型半导体封装的结构。
本发明的膜上芯片型半导体封装包括:集成电路芯片101;印制电路板层202;及石墨层106。
所述集成电路芯片101直接或通过贴装器件109连接到所述印制电路板层202的一面。所述贴装器件109只要是对所述印制电路板层202的电路与所述集成电路芯片101进行电性连接,就不做限制,所述贴装器件具体可以为凸块,其材质可以是金、铜、镍或其组合。
本发明的一个实施例中,所述印制电路板层202可以包括电路图案层102和基材部103。所述电路图案层102可以是与所述集成电路芯片101组成电路的图案,只要是组成电路的物质,并不做限制,其材质可以是金、铜、镍或其组合。所述基材部103只要是绝缘材质,则对其不做限制,所述基材部103可以是软性薄膜,可以是结构通过板可视的透明薄膜,具体地,可以是聚酰亚胺薄膜。
本发明的一个实施例中,所述印制电路板层202的厚度可以是25μm至50μm。当厚度小于25μm时,抗弯曲或撕裂的强度下降,当厚度超过50μm时,柔软性下降,从而可能导致弯曲性变差。
本发明的一个实施例中,所述集成电路芯片101与所述印制电路板层202之间的所述贴装器件109的暴露面积可以用填料110来填埋。对于所述填料110,只要能够抑制由于所述贴装器件109被暴露在空气而导致的氧化,则不做限制,所述填料具体可以是液体树脂、环氧树脂。
图2是集成电路芯片101直接或通过贴装器件109连接到所述印制电路板层202的一面上的结构的膜上芯片型半导体封装的上部方向的平面图。
本发明的一个实施例中,所述集成电路芯片101可以是显示器驱动集成电路芯片(Display Driver Integrated Circut chip,DDI chip)。
所述石墨层106层压在印制电路板层202的相反一面上。
图3是层压有石墨层的膜上芯片型半导体封装的下部方向的平面图。
本发明的一个实施例中,所述石墨层106可以是碳化的高分子膜或由石墨粉末形成的膜。
图4是示出基材部103的一面上设有电路图案层102的一般的印制电路板层202的图。
图5是示出在如图4所示的印制电路板层202的基材部103方向的一面上,将石墨粉末302设置在粘合层104上之后,利用轧辊301向图案层102及基材部103两个方向施压,从而将石墨层106层压在印制电路板层202的一面上的工艺的图。
图6是示出在如图4所示的印制电路板层202的基材部103方向的一面上,将石墨膜401设置在粘合层104上之后,利用轧辊301向电路图案层102及基材部103两个方向施压,从而将石墨106层压在印制电路板层202的一面上的工艺的图。
本发明的一个实施例中,所述石墨膜401可以是人造石墨,具体可以为碳化的高分子膜。
本发明的一个实施例中,所述高分子膜可以是聚酰亚胺膜。
本发明的一个实施方式中,所述碳化是实施包括碳化步骤和石墨步骤的热处理方法。
本发明的一个实施方式中,所述碳化步骤包括将聚酰亚胺膜导入具有第一温度区间的第一加热器内,从而使所述高分子膜碳化并转变为碳质膜的步骤。
本发明的一个实施方式中,所述第一温度区间是500±50℃至1000℃的依次上升的区间。
本发明的一个实施方式中,所述石墨步骤包括将所述碳质膜导入具有作为温度线性上升的区间的第二温度区间的第二加热器内,并转变为石墨膜的步骤。
本发明的一个实施方式中,所述第二加热器的长度为4000mm至6000mm。
本发明的一个实施方式中,所述第二温度区间为1000℃至2800℃的依次上升的区间。
本发明的一个实施方式中,所述第二温度区间包括1000℃至1500℃的第2-1温度区间、1500℃至2200℃的第2-2温度区间及2200℃至2800℃的第2-3温度区间。
本发明的一个实施方式中,所述石墨步骤包括在所述第2-1温度区间内,以0.33mm/秒至1.33mm/秒,横向移动所述碳质膜,并使所述第二加热器的内部温度每分钟上升1℃至5℃的同时,对所述碳质膜进行热处理1至4小时的步骤。
本发明的一个实施例中,所述石墨层106的厚度可以为5μm至40μm。当厚度小于5μm时,散热效果下降,当厚度超过40μm时,散热效果同样下降。
本发明的一个实施例中,在所述石墨层106与所述印制电路板层202之间还可以包括粘合层104、107。
本发明的一个实施例中,所述粘合层104、107可以是在施加压力时显现或强化粘合活性的压敏粘合剂(Pressure sensitive adhesive,PAS),具体可以是丙烯酸类粘合剂或聚酰亚胺、聚对苯二甲酸乙二醇酯、双面胶。
本发明的一个实施例中,所述粘合层104、107可以包括导电颗粒。
本发明的一个实施例中,所述粘合层104、107的厚度可以是3.5μm至5μm。
图7是示出在印制电路板层202的基材部103方向的一面上层压有石墨层106的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图8是示出在印制电路板层202的基材部103方向的一面上依次层压有粘合层104和石墨层106的膜上芯片型半导体封装的制造工艺过程中膜剖面的一个例子的图。
本发明的一个实施例中,在所述石墨层106的一面上还可以包括保护膜层108。
本发明的一个实施例中,所述保护膜层108可以层叠在所述石墨层106的印制电路板层202的基材部103方向的一面上。
本发明的一个实施例中,所述保护膜层108可以是绝缘膜,具体可以为聚酯类树脂膜,并且可以包括聚对苯二甲酸乙二醇酯(PET)、聚对苯二甲酸丁二醇酯(PBT)、聚对苯二甲酸丙二醇酯(PTET)、聚对苯二甲酸环己酯(PCHT)及聚萘二甲酸乙二醇酯(PEN)或其组合。
本发明的一个实施例中,所述保护膜层108的厚度可以为1.5μm至3.0μm。
图9是示出在印制电路板层202的基材部103方向的一面上层压石墨层106,在石墨层的基材部103的相反方向的一面上依次层叠粘合层107和保护膜层108的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图10是示出在印制电路板层202的基材部103方向的一面上依次层压有粘合层104和石墨层106,在石墨层106的基材部103的相反方向的一面上依次层叠粘合层107和保护膜层108的膜上芯片型半导体封装的制造工艺中的膜剖面的一个例子的图。
本发明的一个实施例中,所述保护膜层108可以层叠在所述石墨层106的印制电路板层202的基材部103的相反方向的一面上。
图11是示出在印制电路板层202的基材部103方向的一面上层叠有粘合层104、保护膜层105,在所述保护膜层105的所述基材部103方向的一面上层压有石墨层106的膜上芯片型半导体封装的制造工艺过程中的膜剖面的一个例子的图。
图1是示出图7的印制电路板层202的基材部103方向的一面上层压有石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图12是图8的印制电路板层202的基材部103方向的一面上依次层压有粘合层104和石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图13是图9的印制电路板层202的基材部103方向的一面上层压石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
图14是示出图10的印制电路板层202的基材部103方向的一面上依次层压粘合层104和石墨层106,石墨层106的基材部103的相反方向的一面上依次层叠粘合层107和保护膜层108的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
本发明的一个实施例中,所述保护膜层108可以层叠在所述石墨层106的印制电路板层202的基材部103的相反方向的一面上。
图15是示出图11的印制电路板层202的基材部103方向的一面上层叠有粘合层104、保护膜层105,所述保护膜层105的所述基材部103方向的一面上层压有石墨层106的膜中,在印制电路板层202的电路图案层102方向的一面上设置贴装器件109,并在间隙中填充填料110之后,层叠集成电路芯片101的膜上芯片型半导体封装的剖面的一个例子的图。
本发明的一个实施例中,在所述印制电路板层202的一面上还可以包括外引线键合垫(Outer Lead Bonder pad)204。
所述外引线键合垫204只要是电性连接所述印制电路板层202的电路与显示器面板,则不做限制,所述外引线键合垫的材质可以是金、铜、镍或其组合。
本发明的一个实施例中,所述外引线键合垫204可以以垂直于所述集成电路芯片的长度方向的方向设置。
图16是在印制电路板层202的一面上直接或通过贴装器件109连接的集成电路芯片101和外引线键合垫204以垂直于所述集成电路芯片的长度方向的方向设置的膜上芯片型半导体封装的上部方向的平面图。
本发明的一个实施例中,所述石墨层106可以层压在除了设置有所述外引线键合垫的所述印制电路板层202面积的相反一面的面积上。对这种结构的膜上芯片型半导体封装来说,改善了设置在印制电路板层202的外引线键合垫204在层压有石墨层203的方向上的视觉外观性,从而在石墨层203方向上也可以通过肉眼确认外引线键合垫204,因此改善视觉外观性,并且外引线键合工艺(Outer Lead Bonding process,OLB process)时改善粘合的准确度及粘合的强度。
本发明的一个实施例中,所述石墨层106可以是由两个以上隔开而层压。此时,在石墨层203方向上也区分集成电路芯片的个别单位区域,从而外引线键合工艺(Outer LeadBondig process,OLB process)时改善粘合的准确度及粘合的强度。
图17是所述外引线键合垫204以与集成电路芯片101的长度方向垂直的方向设置,所述石墨层106在除了设置所述外引线键合垫的所述印制电路板层202的面积的相反一面的面积上,由两个以上隔开而层压的膜上芯片型半导体封装的层压有石墨层的下部方向的平面图。
图18是印制电路板层202的石墨层由两个以上隔开而层压的一面上直接或通过贴装器件109连接的集成电路芯片101和外引线键合垫204以与所述集成电路芯片的长度方向垂直的方向设置的膜上芯片型半导体封装的上部方向的平面图。
本发明的一个实施例中,所述集成电路芯片101可以以与所述印制电路板层202的长度方向垂直的方向设置。
本发明的一个实施例中,印制电路板层202和石墨层106分别在以膜形态卷绕辊的状态下,两面被两个轧辊301施压,并可以通过卷对卷(roll to roll)/(reel to reel)工艺进行第一次层压。此时,轧辊的压力可以是3~30kg。并且,在石墨层106的一面上,承载膜(carrier film)可以通过卷对卷供应并层叠,第一次层压膜可以以印制电路板层202/石墨层106/承载膜层(未示出)或印制电路板层202/粘合层104/石墨层106/承载膜层(未示出)的顺序层叠。
本发明的一个实施例中,所述第一次层压膜和粘合层104、107分别在以膜的形态卷绕辊的状态下,两面被两个轧辊301施压,并可以通过卷对卷(roll to roll)/(reel toreel)工艺进行第二次层压。此时,轧辊的压力可以是3~20kg。并且,在石墨层106的一面上,离型膜(release film)可以通过卷对卷供应并层叠,第二次层压膜可以以印制电路板层202/粘合层104/石墨层106/粘合层107/离型膜层(未示出)或印制电路板层202/粘合层107/石墨层106/离型膜层(未示出)的顺序层叠。
本发明的一个实施例中,所述第二次层压膜和保护膜层105、108分别在以膜形态卷绕辊的状态下,两面被两个轧辊301施压,并可以通过卷对卷(roll to roll)/(reel toreel)工艺进行第二次层压。此时,轧辊的压力可以是3~20kg,轧辊的温度可以是70~90℃。并且,第三次层压膜可以以印制电路板层202/粘合层104/石墨层106/粘合层107/保护膜层108或印制电路板层202/粘合层107/石墨层106/保护膜层108的顺序层叠。
下面,对包括所述膜上芯片型半导体封装、基板及显示器面板的显示设备进行说明。
本发明的一个实施例中,所述基板可以与所述膜上芯片型半导体封装的外引线键合垫204电性连接。
本发明的一个实施例中,所述基板还包括外引线键合垫(未示出),并可以与所述膜上芯片型半导体封装的外引线键合垫204电性连接。
本发明的一个实施例中,所述基板还包括外引线键合垫(未示出),并且可以与所述膜上芯片型半导体封装的外引线键合垫204电性连接。此时,在所述基板的外引线键合垫(未示出)与所述膜上芯片型半导体封装的外引线键合垫204之间还可以包括异方性导电胶膜(Anisotropic Conductive Film,ACF)层。所述基板的外引线键合垫(未示出)/所述各向异性导电膜/所述膜上芯片型半导体封装的外引线键合垫204可以依次设置后通过外引线键合工艺(OLB process)层叠。
本发明的一个实施例中,显示器面板可以是液晶显示器或发光元件显示器,其结构模块可以包括通常使用的显示器面板的模块。
所述膜上芯片型半导体封装与所述基板及所述显示器面板电性连接,可以根据集成电路芯片的驱动信号,通过电信号驱动并控制显示器面板的相应像素。
以上说明应被理解为优选实施例的示例,而不是限定发明的范围。因此本发明应该由权利要求书和权利要求书的等同物来确定而不是由以上说明的内容来确定。
附图标记说明
101:驱动集成电路芯片
102:印制电路板层的电路图案层
103:印制电路板层的基材部
104、107:粘合层
105、108:保护膜层
106、203:石墨层
109:贴装器件
110:填料
202:印制电路板层
301:轧辊
302:石墨粉末
401:石墨膜
Claims (8)
1.一种膜上芯片型半导体封装,包括:
集成电路芯片;
印制电路板层;
石墨层;以及
外引线键合垫,位于所述印制电路板层的一面,
所述集成电路芯片直接或通过贴装器件连接到所述印制电路板层的一面上,所述石墨层层压在所述印制电路板层的相反一面上,
所述外引线键合垫以与所述集成电路芯片的长度方向垂直的方向设置,
所述石墨层层压在除了设置有所述外引线键合垫的所述印制电路板层面积的相反一面的面积上,
所述集成电路芯片为显示器驱动集成电路芯片。
2.根据权利要求1所述的膜上芯片型半导体封装,在所述石墨层与所述印制电路板层之间还包括粘合层。
3.根据权利要求1所述的膜上芯片型半导体封装,在所述石墨层的一面上还包括保护薄膜层。
4.根据权利要求1所述的膜上芯片型半导体封装,其中,
所述石墨层的厚度为5μm至40μm。
5.根据权利要求1所述的膜上芯片型半导体封装,其中,
所述石墨层为碳化的高分子膜或由石墨粉末形成的膜。
6.根据权利要求1所述的膜上芯片型半导体封装,其中,
所述石墨层层压在所述印制电路板层的两面上。
7.根据权利要求1所述的膜上芯片型半导体封装,其中,
所述集成电路芯片以与所述印制电路板层的长度方向垂直的方向设置。
8.一种显示设备,包括:
根据权利要求1至7中任一项所述的膜上芯片型半导体封装;
基板;及
显示器面板。
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