CN102760704A - 薄膜覆晶型半导体封装 - Google Patents

薄膜覆晶型半导体封装 Download PDF

Info

Publication number
CN102760704A
CN102760704A CN2011103345880A CN201110334588A CN102760704A CN 102760704 A CN102760704 A CN 102760704A CN 2011103345880 A CN2011103345880 A CN 2011103345880A CN 201110334588 A CN201110334588 A CN 201110334588A CN 102760704 A CN102760704 A CN 102760704A
Authority
CN
China
Prior art keywords
film
membrane
semiconductor package
layer
flip chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103345880A
Other languages
English (en)
Other versions
CN102760704B (zh
Inventor
金都永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Megna Zhixin Hybrid Signal Co.,Ltd.
Original Assignee
MagnaChip Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MagnaChip Semiconductor Ltd filed Critical MagnaChip Semiconductor Ltd
Publication of CN102760704A publication Critical patent/CN102760704A/zh
Application granted granted Critical
Publication of CN102760704B publication Critical patent/CN102760704B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明提供一种薄膜覆晶型半导体封装，这种半导体封装可以得到驱动集成电路芯片的高散热效果且可防止引线断裂，且本发明的薄膜覆晶型半导体封装包括：膜；多个引线，形成于所述膜上的；芯片，粘贴于所述多个引线上的末端上；底部填充胶层，充填所述芯片与多个引线之间的空间；石墨类散热层，粘贴于所述膜的下部面上。所述石墨类散热层的厚度可形成为140μm以下的超薄型。同时，所述散热层由于使用了石墨，因而柔韧性和张力较优异，因此可广泛地应用于柔韧性的产品群中。

Description

薄膜覆晶型半导体封装
技术领域
本发明涉及半导体封装，尤其涉及芯片粘贴于膜上的薄膜覆晶型(ChipOn Film)半导体封装。
背景技术
随着液晶显示装置(LCD，Liquid Crystal Display)等的显示装置为了扩大市场领域，推进低价化、大型化以及高性能化，需要在较小的区域内布置越来越多的像素。由于这种状况，随着控制各像素的驱动集成电路(Driver IC)的引线间距在显示装置内渐渐变得微细化，封装方法也开发为各种各样。
显示装置领域中主要应用的封装方法有带状媒介封装(TCP，Tape CarrierPackage)、玻璃覆晶封装(COG，Chip On Glass)以及薄膜覆晶封装(COF，Chip On Film)等。这种方法可看作为无线(Wireless)工艺方法。为了谋求降低微细间距化而带来的工程造价以及提高产量，自1990年代末开始，薄膜覆晶封装(COF)技术在封装市场中所占的比例逐渐呈增加态势。
薄膜覆晶封装技术是与通信设备的轻薄短小化趋势一起，在显示器驱动集成电路中为了应对这种趋势而开发出的一种新形态的封装。在薄膜覆晶封装(COF)技术中，为了实现具有高分辨率的显示装置，电视机(TV)及监视器的驱动频率从60Hz增加为120Hz的同时，使得驱动集成电路的驱动负荷上升，由此，集成电路的放热问题呈严重的态势。
用于解决如上所述的放热问题的方法曾由韩国专利授权号10-0771890号(申请人：三星电子)申请。
图1为示出现有技术提供的薄膜覆晶型半导体封装的图。
参照图1，在薄膜覆晶型半导体封装中，作为显示器用驱动芯片的驱动集成电路芯片103通过粘结层(未图示)而粘贴在具有柔软性的膜101上。多个引线102相互分离地设置于膜101上，且多个引线102的内部末端设置成集中于中央。
末端的局部被暴露的多个引线102的上部面上粘贴有驱动集成电路芯片103，粘贴有驱动集成电路芯片103的周边充填有底部填充胶层107，以将驱动集成电路芯片103稳定地固定于膜101上。符号106示出的是凸点(bump)。
另外，散热片104通过粘结层(未图示)粘贴于膜101的下部面上。散热片104用于将因驱动集成电路芯片103工作而产生的热量通过底部填充胶层107和引线102朝下侧方向传递之后朝外侧散热，该散热片104可由铝等金属类构成。
如上所述，由现有技术的金属类构成的散热层104形成为200μm左右厚，尤其，如果是金属类的散热层，则需要另外使用绝缘胶带105，因此存在难以减小厚度的问题。并且，如果利用了所述金属类的散热层105的厚度变厚，则具有发生例如膜101上的引线断裂(lead broken)的损坏的问题。
发明内容
本发明是为了解决上述的现有技术的问题而提出的，其目的在于提供能够得到驱动集成电路芯片的高散热效果和防止引线断裂的具备包含有石墨材料层的散热层的薄膜覆晶型半导体封装。
本申请的发明为了解决上述问题而提供薄膜覆晶型半导体封装，包括：膜；多个引线，形成于所述膜的一侧面部；芯片，粘贴于所述多个引线上的末端上；底部填充胶层，充填所述芯片与多个引线之间的空间；以及散热层，粘贴于所述膜的另一面部。所述散热层包括：石墨材料层；保护层，形成于石墨材料层的一侧面，以防止所述材料层暴露到外部；以及粘结层，以用于将散热层粘贴到所述膜的另一面部。
所述石墨材料层包括石墨膜，其中所述石墨膜可通过对高分子膜以及经碳化的高分子膜进行石墨化而制得。
其中，所述高分子膜可以为聚酰亚胺。
并且，所述石墨膜为由石墨薄膜多层叠置而成的多层结构。并且，所述石墨膜为叠置有100层至300层所述石墨薄膜的多层结构。
在所述薄膜覆晶型半导体封装中，所述石墨材料层的厚度为20μm至60μm。所述保护层具有绝缘性。
所述保护层包括从由聚对苯二甲酸乙二醇酯、聚对苯二甲酸丁二醇酯、聚对苯二甲酸丙二醇酯、聚环乙烯对苯二酸酯以及聚萘二甲酸乙二醇酯组成的群中所选择的一个以上。
所述保护层的厚度为10μm至40μm。所述粘结层的厚度为10μm至40μm。所述散热层的厚度为60μm至140μm。
特征在于，所述芯片为驱动集成电路芯片(driver IC chip)。
所述膜为聚酰亚胺。
并且，所述石墨材料层为石墨高分子经相互交联(cross-link)而成的聚合物链结构。
本申请的发明的薄膜覆晶型半导体封装，由于将石墨应用到散热层，从而相比金属材料的散热层，具有散热层的厚度薄且散热效率高的优点。并且，由于所述石墨的张力(Tensile force)较优异，因此具备应用石墨的散热层的本申请的发明的薄膜覆晶型半导体封装，可广泛地应用于不能应用现有的金属材料散热层的、柔韧(flexible)及可伸长性形态的产品群中。最后，本申请的发明的半导体封装所使用的散热层具有缓冲驱动集成电路芯片与膜之间的热间隙(Temperature Gap)的传导(Spread)效果，且起到抑制温度变化所引起的膜的收缩膨胀的作用，从而具有减少引线断裂的效果。
附图说明
图1为示出现有技术提供的薄膜覆晶型半导体封装的示意图；
图2为示出本申请的发明的一实施例提供的薄膜覆晶型半导体封装的示意图；
图3为示出石墨片的截面的扫描电镜(SEM)照片；
图4为本申请的发明的一实施例提供的散热层的放大图；
图5示出的是本申请的发明的一实施例提供的使用最上部金属垫(topmetal pad)的薄膜覆晶型半导体封装，其放大示出了图2的圆圈部分；
图6为示出本申请的发明的又一实施例提供的薄膜覆晶型半导体封装的示意图。
符号说明：201为膜，202为引线，203为驱动集成电路芯片，204为散热层，204a为石墨材料层，204b为保护层，204c为粘结层，205为凸点，206为底部填充胶层，207为阻焊膜，220为凸点下金属化层(under bumpmetallization，UBM)，221为钝化层，222为防反射涂层(Anti-reflective coatinglayer，ARC layer)，223为最上部金属垫(top metal pad)，224为势垒金属(barriermetal)，225为最上部通孔，226为下方金属(under)，227为接触插头，228为硅衬底。
具体实施方式
以下，参照示出本发明的最优选实施例的附图进行说明，以使本发明所属技术领域的具有通常知识的技术人员能够容易地实施本发明的技术思想。
图2为简单地示出本申请的发明的一实施形态提供的薄膜覆晶型(COFTYPE)半导体封装的示意图。
参照图2，所述薄膜覆晶型半导体封装包括：膜201；形成于所述膜201的一侧面上的多个引线202；用于驱动显示器的驱动集成电路芯片203；连接所述引线202和集成电路芯片203的凸点205；粘贴于所述膜的另一侧面上的散热层204。在此，驱动集成电路(IC)可包括薄膜晶体管液晶显示器(TFT-LCD)、超扭曲向列型液晶显示器(STN-LCD)、铁电性液晶器件(FLCD)、胆固醇液晶显示器(Ch-LCD)或发光二极管(LED)、等离子显示器(PDP)、有机发光显示器。并且，可粘贴有包括驱动集成电路的芯片。
首先，膜201是为了形成驱动集成电路而提供的，该膜201包括绝缘层(未图示)。优选地，所述膜201用具有柔软性的聚酰亚胺(Polyimide，PI)作为材料。所述引线202用铜(Cu)作为材料。所述膜201和所述引线202形成为例如在聚酰亚胺(PI)膜上镀覆铜的两层结构，该结构适合高柔软性和细间距(fine pitch)。形成于所述膜201上的铜引线202起到将驱动芯片的电气特性传递到作为外部输出装置的面板的作用。所述膜201形成为10μm至60μm的厚度，所述铜引线202形成为3μm至20μm的厚度。为了保护铜引线可蒸镀阻焊膜(solder resist)207。若没有阻焊膜207，则铜会直接暴露于外部空气中而被氧化，使电阻增加。并且，在不能用阻焊膜207保护的区域的铜表面上涂布有锡(Tin)。
所述引线202和驱动集成电路芯片203通过凸点205而接触。所述凸点205由金(Au)或铜(Cu)或镍(Ni)构成，或者由这些物质中的两个组合而成的材料构成。
参照图5，为了连接驱动集成电路芯片203和凸点205而使用与驱动集成电路芯片203连接的最上部金属垫223。最上部金属垫223将成为焊盘(bonding pad)。最上部金属垫223的下部形成有执行驱动集成电路功能的半导体元件，驱动集成电路与最上部金属垫223之间可形成有最上部通孔(topvia)225。执行驱动集成电路功能的半导体元件可形成于垫的下部或垫的侧面。若形成于垫的下部，则具有减小整个芯片面积的效果。
所述装置最上部金属垫223暴露在用作保护膜的钝化层(passivationlayer)221之间。为了防止水分朝芯片内部渗透而需要保护膜。在此，钝化层221通过包含氮化硅膜(silicon nitride)或者氧化硅膜(silicon oxide)或者这些物质的组合而构成。最上部金属垫223可从铝金属或铜金属、铝-铜合金中选择一个而使用。若使用铝金属，则可在铝金属的下部使用势垒金属(barriermetal)224以及在铝金属的上部使用防反射涂层(Anti-reflective coating layer，ARC layer)222，且可使用钛(Ti)、氮化钛(TiN)、钛钨(TiW)等。例如，可从Ti/Al/TiN、Ti/TiN/Al/TiN、Ti/TiN/Al/Ti/TiN、TiN/Al/TiN、Ti/Al/TiW或者Ti/TiN/Al/TiW等组合中选择而使用。其中，Ti/Al/TiN或Ti/TiN/Al/TiN结构在防止裂开和散热方面效果更佳，因此可使用该结构。在本发明中，优选为使用Ti/TiN/Al/TiN。
为了提高所述凸点205与所述金属垫223之间的粘贴力，在形成凸点之前形成凸点下金属化层(under bump metallization，UBM)220。UBM 220可由钛钨(TiW)和金(Au)构成。优选地，在钛钨(TiW)膜上再形成金种子层(seed layer)。金起到金凸点的种子层作用。如果是铜凸点，则可形成铜种子层。钛钨和金种子层和可通过溅射(sputtering)方式蒸镀。
从图5可以确认，去除位于与Al垫接触的凸点之间的用作防反射涂布层222的氮化钛(TiN)，并在其上蒸镀TiW/Au。这是因为，如果残留有TiN，则有可能使粘贴力降低。钝化层221的开放(open)只要去除TiN即可。位于钝化层221下方的防反射涂布层222将被留存。
并且，为了电气连接形成于硅衬底228上的驱动集成电路芯片203与最上部金属垫223，可进一步形成有下方金属226和接触插头227。驱动集成电路芯片203可形成有阱(well)(未图示)、栅极绝缘膜(未图示)、栅极(未图示)、源极及漏极(未图示)、浅沟槽隔离膜(shallow trench isolation，STI)和深沟槽隔离膜(Deep trench isolation，DTI)等场氧化膜(field oxidation)。
为了使随后将要形成的石墨材料层所带来的散热效果最大化，凸点结构以及UBM中所使用的物质非常重要。本发明中，在铝垫表面上形成TiW/Au种子层/Au凸点结构或者Tiw/Cu种子层/Cu凸点或者Tiw/Au种子层/Cu凸点或者Tiw/Cu种子层/Au凸点的结构在最大化散热效果方面属于较适合的物质。特别是，使用为凸点以及凸点下金属化层物质的金(Au)或铜(Cu)物质具有较佳的导热率，因此当具备石墨材料层时，对于在驱动芯片上所产生的热量可获得更高的散热效果。
本发明中，为了使驱动集成电路的散热效果最大化，可使用Ti/TiN/Al/TiW/Au凸点/聚酰亚胺/石墨散热层或者Ti/TiN/Al/TiW/Cu凸点/聚酰亚胺/石墨散热层。
再次参照图2，多个所述引线202的上部面上粘贴有驱动集成电路芯片203，粘贴有驱动集成电路芯片203的周边充填有底部填充胶层206，以将驱动集成电路芯片203稳定地固定于膜201上。即，底部填充胶层206充填驱动集成电路芯片203与多个引线202之间的空间。底部填充胶层206例如可使用液体树脂(Liquid resin)。
散热层204利用粘结层204c作为媒介而粘贴于所述膜201的下部面上。
所述散热层204用于将由于驱动集成电路芯片203的工作而产生的热量通过底部填充胶层206和引线202朝下侧方向传递之后朝外侧散热。
本申请的发明的所述散热层204包括石墨材料层204a、保护层204b以及粘结层204c。
所述石墨材料层204a的材料包括石墨。所述石墨通过如下过程而获得，即，将作为石墨的原料的焦炭粉碎成预定厚度以下的粉末的过程；对被粉碎的焦炭添加结合剂的过程；成型的过程；成型之后加热至1000℃，以使碳化而形成碳块的过程；对被碳化的所述碳块加热至3000℃，以减小大小和体积。
或者，石墨膜可将高分子膜以及/或经碳化的高分子膜作为原料使用而制得。该方法包括对高分子膜以600℃至1800℃温度进行碳化之后，在2000℃至3000℃温度下进行石墨化的过程。杂质通过石墨化过程而被去除，仅留存有纯的碳元素成分。所述高分子膜可以为人造纤维(rayon)类、沥青(pitch)类、聚丙烯腈(polyacrylonitrile)类、聚酰亚胺(PI)类、聚酰胺(polyamide，PA)、聚偏二氯乙烯(polyvinylidene chloride)类、聚全氟醇类或者酚类(phenol)纤维，或者为这些物质中的两种以上物质。优选地，所述高分子膜使用聚酰亚胺类高分子膜。聚酰亚胺膜具有如下优点，即，能够获得通过选择所期望的原料单体(monomer)而具备各种结构和特性的膜。
据此，参照图3，作为原料使用经碳化的高分子膜而获得的石墨具有高分子结构相互交联(cross-link)的聚合物链结构。或者，所述石墨膜可以为微细的石墨薄膜被叠置数十层至数百层的多层结构。优选地，所述石墨薄膜可以通过叠置100至300层石墨薄膜而构成(参照图3及图4)。通过叠置的效果，可形成膜的柔软性和弹性。
为了最大化降温效果，所述石墨材料层204a的厚度为20μm至60μm。所述石墨材料层204a的厚度优选为25μm至40μm。
图3为示出通过使用经碳化的高分子膜而得到石墨膜的截面的SEM照片，所述膜的截面呈多个微细的石墨薄膜被层层叠置的形状。所述薄膜的表面具有曲折，并不平坦。因此，从SEM照片中可以确认，所述石墨薄膜与薄膜之间有可能存在空的空间，该空间将赋予石墨膜柔软性。并且，多个石墨薄膜相对膜201以水平方向叠置，因此具有能够朝水平或平面方向(horizontalor planar direction)快速地扩散由LCD驱动芯片产生的热量，以分散热量的特性。并且，作为原料使用了经碳化的高分子膜，因此聚合物链以水平以及垂直方向相互交联，因此将具备作为高分子固有特性的一定的弹性。
所述散热层204包括保护层204b。所述保护层204b起到绝缘层的作用和防止石墨材料层204c暴露到外部的保护作用。具体来讲，防止在石墨材料层204a上产生刮痕(scratch)以及/或异物(particle)。如果没有保护层，则石墨材料层将会朝外部暴露，从而有可能在此处产生刮痕，且由石墨构成的导电性粒子贴附到半导体元件(LCD驱动芯片)或衬底上。此时，有可能引发短路等问题。因此，为了最大化绝缘效果以及防止刮伤、防止产生导电性物质的异物以及散热效果，优选为在石墨材料层204a上形成保护层204b。
优选地，所述保护层204b包括具有绝缘性的聚酯(polyester)类树脂，以起到绝缘层的作用。所述聚酯类树脂包括诸如聚对苯二甲酸乙二醇酯(PET)、聚对苯二甲酸丁二醇酯(PBT)、聚对苯二甲酸丙二醇酯(PTT)、聚环乙烯对苯二酸酯(PCT)以及聚萘二甲酸乙二醇酯(PEN)等物质，但并不局限于此。
为了使所述保护层204b的绝缘效果以及防止刮伤、防止产生导电性物质的异物以及散热效果最大化，所述保护层204b的厚度设置为10μm至40μm的厚度，优选为30μm。若小于10μm或大于40μm，则有可能阻碍所述石墨材料层204a的优异的热传导性的发挥，且在石墨材料层204a的粘结性以及长期可靠性方面可能存在问题。
所述粘结层204c优选为使用压感胶粘剂(pressure sensitive adhesive)。所述胶粘剂可以是包含有导热性粒子的胶粘剂。优选地，所述胶粘剂可使用丙烯酸类胶粘剂或聚酰亚胺、聚对苯二甲酸乙二醇酯(PET)、双面胶带等。为了使整个散热效果最大化以及使粘结性较佳，本申请的发明提供的粘结层204c的厚度可以为10μm至40μm。当粘结层204c的厚度在所述范围内时，还具有热传导性优异的一面。粘结层204c的厚度优选为20μm以下，更优选为15μm以下。若所述粘结层204c形成为小于10μm或大于40μm，则有可能在散热层204的粘结性以及长期可靠性方面存在问题。
本申请的发明的一实施例提供的散热层204可由石墨材料层/聚对苯二甲酸乙二醇酯(PET)/粘结层或者石墨材料层/聚萘二甲酸乙二醇酯(PEN)/粘结层构成。由于如上述构成的散热层204由导热性及降温效率高的石墨材料层204a所起到的散热效果和由PET或PEN的保护层204b所起到的防止产生导电性物质的异物以及保护效果叠加在一起，因此相比现有的散热层具有优异的导热率、散热效果以及可靠度。
本申请的发明提供的散热层204具有约60μm至140μm的厚度，优选为具有65μm至80μm的厚度。当散热层204由金属类构成时，为了获得所期望的散热效果，需要使散热层204的厚度大约为200μm以上。但是，本申请的发明的散热层204由于包括以石墨为基本材料的石墨材料层204b，因此散热层204的厚度大约为40μm至140μm，从而相比以金属材料为基本材料的散热层更薄。但是，具有降温效率优异的散热效果。
并且，包含于石墨材料层204b的石墨膜，由于石墨的微细薄膜之间的层间余裕空间，从而使散热层204的柔软性高。因此，可以在没有另外改造等变更的情况下以卷形物(Roll)的形态供应给层压(Laminating)设备。即，可通过卷对卷(reel to reel)方式进行层压作业，容易地将散热层204粘贴到膜上。
并且，包含有石墨材料层204b的散热层204由于其张力(Tensile force)较优异，因此可广泛地应用于在金属类的散热层上没有体现的柔韧(flexible)及可伸长性形态的产品群中。
例如，可以以散热为目的而使用于车辆用电装部件、LED、荧光灯等，而且可以应用于由于驱动集成电路芯片、温度控制器、中央处理装置、存储器、其他电子产品的薄膜形态而不能安装散热器(heat sink)的产品中。并且，可以使用为在柔性印刷电路板(Flexible PCB)上需要绝缘性的散热层，而且可应用为作为驱动集成电路芯片和各种半导体产品群以及加热器(Heatblock)等的散热器的代用品。
并且，由多张微细薄膜形态的石墨叠置而成的石墨散热层由于具有疏水性，因此可看作几乎不吸收水。并且，本申请的发明的特征在于石墨材料层204a、保护层204b以及粘结层204c被设置成一列。在制造方法的容易性方面优选为设置成一列。或者，设置成保护层204b和粘结层204c的两末端相比于石墨材料层204a的长度足够长且相互接触，由此可在其内侧设置石墨材料层204a(参照图6)。即，石墨材料层204a的末端被保护层204b和粘结层204c包裹。这样做的目的在于不让石墨材料层朝外侧暴露。或者，可设置成仅使石墨材料层204a的末端的至少一部分被保护层204b和粘结层204c覆盖或包裹。由此，可降低石墨材料层204a受到外部冲击而发生脱离或翘起或脱附的现象。并且，本申请的发明提供的散热层204可以呈四边形形状或各边角进行倒圆(rounding)处理的四边形形状。
[实施例一]
分别制造具备铝材料的散热层的半导体封装(比较例)和具备包含有石墨材料层的散热层的半导体封装(实施例一及实施例二)之后，测定了导热率和降温效率，并在下面[表一]中进行了整理。在此，最初温度和最终温度为在薄膜201上测定的温度。即，在聚酰亚胺上测定温度变化。在此，降温效率是指以最初温度为基准，针对从最初温度至最终温度的差值的变化率。
[表一]
Figure BSA00000602074900091
从所述[表一]中可以确认，实施例一和实施例二相比比较例，可得出散热层的厚度薄且导热率和降温效率优异。材料层的厚度从25μm设置成40μm时，降温效率从34％增大到38％。因此，可构成由所述石墨材料层/保护层构成的散热层。通过使用两种层，使导热性及降温效率高的石墨材料层所起到的防热效果和使用保护层而起到的防止产生导电性物质的异物以及保护效果叠加在一起，因此相比现有的散热层薄，但是得到了更好的防热效果。
并且，相比于铝材料的散热层，本发明的防热层其柔软性优异，因此应用范围非常广。
需要注意的是，虽然本发明的技术思想根据所述优选实施例而进行了具体的说明，但是上述实施例只是为了对其进行说明的，并不是为了对其进行限定的。并且，本发明的技术领域的通常的技术人员应当理解，在本发明的技术思想范围内可以有多种实施例。

Claims (14)

1.一种薄膜覆晶型半导体封装，其特征在于，包括：
膜；
多个引线，形成于所述膜的一侧面部；
芯片，粘贴于所述多个引线上的末端上；
底部填充胶层，充填所述芯片与多个引线之间的空间；以及
散热层，粘贴于所述膜的另一面部，
其中，所述散热层包括：石墨材料层；保护层，形成于石墨材料层的一侧面，以防止所述石墨材料层暴露到外部；以及粘结层，以用于将散热层粘贴到所述膜的另一面部。
2.如权利要求1所述的薄膜覆晶型半导体封装，其特征在于，所述石墨材料层包括石墨膜，其中所述石墨膜通过对高分子膜以及经碳化的高分子膜进行石墨化而制得。
3.如权利要求2所述的薄膜覆晶型半导体封装，其特征在于，所述高分子膜为聚酰亚胺。
4.如权利要求2所述的薄膜覆晶型半导体封装，其特征在于，所述石墨膜为由石墨薄膜多层叠置而成的多层结构。
5.如权利要求4所述的薄膜覆晶型半导体封装，其特征在于，所述石墨膜为叠置有100层至300层所述石墨薄膜的多层结构。
6.如权利要求1至5中任一项所述的薄膜覆晶型半导体封装，其特征在于，所述石墨材料层的厚度为20μm至60μm。
7.如权利要求1所述的薄膜覆晶型半导体封装，其特征在于，所述保护层具有绝缘性。
8.如权利要求1或7所述的薄膜覆晶型半导体封装，其特征在于，所述保护层包括从由聚对苯二甲酸乙二醇酯、聚对苯二甲酸丁二醇酯、聚对苯二甲酸丙二醇酯、聚环乙烯对苯二酸酯以及聚萘二甲酸乙二醇酯组成的群中所选择的一个以上。
9.如权利要求1或7所述的薄膜覆晶型半导体封装，其特征在于，所述保护层的厚度为10μm至40μm。
10.如权利要求1所述的薄膜覆晶型半导体封装，其特征在于，所述粘结层的厚度为10μm至40μm。
11.如权利要求1所述的薄膜覆晶型半导体封装，其特征在于，所述散热层的厚度为60μm至140μm。
12.如权利要求1所述的薄膜覆晶型半导体封装，其特征在于，所述芯片为驱动集成电路芯片。
13.如权利要求1所述的薄膜覆晶型半导体封装，其特征在于，所述膜为聚酰亚胺。
14.如权利要求1所述的薄膜覆晶型半导体封装，其特征在于，所述石墨材料层为石墨高分子经相互交联而成的聚合物链结构。
CN201110334588.0A 2011-04-28 2011-10-26 薄膜覆晶型半导体封装 Active CN102760704B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020110040319A KR20120122266A (ko) 2011-04-28 2011-04-28 칩온필름형 반도체 패키지
KR10-2011-0040319 2011-04-28

Publications (2)

Publication Number Publication Date
CN102760704A true CN102760704A (zh) 2012-10-31
CN102760704B CN102760704B (zh) 2016-05-18

Family

ID=47055101

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110334588.0A Active CN102760704B (zh) 2011-04-28 2011-10-26 薄膜覆晶型半导体封装

Country Status (3)

Country Link
US (1) US9070680B2 (zh)
KR (1) KR20120122266A (zh)
CN (1) CN102760704B (zh)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839898A (zh) * 2012-11-20 2014-06-04 瑞鼎科技股份有限公司 封装结构及其制造方法
CN103889196A (zh) * 2014-04-11 2014-06-25 江苏悦达新材料科技有限公司 一种高导热人工石墨膜的制备方法
WO2014206003A1 (zh) * 2013-06-26 2014-12-31 合肥京东方光电科技有限公司 一种灯条、背光模组和显示装置
CN104505347A (zh) * 2014-12-04 2015-04-08 江苏长电科技股份有限公司 一种在塑封过程中贴装石墨烯散热薄膜的方法
CN108573930A (zh) * 2017-03-07 2018-09-25 联咏科技股份有限公司 薄膜倒装封装及薄膜倒装封装的制造方法
CN109844944A (zh) * 2017-08-21 2019-06-04 金学模 改善视觉外观性及加工性的层压石墨的膜上芯片型半导体封装
US10643921B2 (en) 2017-03-07 2020-05-05 Novatek Microelectronics Corp. Chip on film package
CN111403362A (zh) * 2020-03-27 2020-07-10 Tcl华星光电技术有限公司 覆晶薄膜封装方法、封装结构、显示装置、电子设备
CN111508910A (zh) * 2020-04-21 2020-08-07 颀中科技（苏州）有限公司 一种覆晶封装结构及封装方法
CN113889500A (zh) * 2020-07-01 2022-01-04 三星显示有限公司 显示装置、显示装置的返工方法及分离显示装置的设备

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8643155B2 (en) * 2011-06-09 2014-02-04 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid crystal display and chip on film thereof
US8803333B2 (en) * 2012-05-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
KR101702041B1 (ko) * 2015-05-12 2017-02-13 주식회사 넥시아 디바이스 평판 디스플레이 드라이버 칩 및 이를 구비하는 기판 구조체
WO2017087969A1 (en) * 2015-11-19 2017-05-26 Boyd Corporation Densified foam for thermal insulation in electronic devices
JP6531033B2 (ja) * 2015-11-24 2019-06-12 株式会社ジャパンディスプレイ 表示装置
US11075186B2 (en) 2017-02-09 2021-07-27 Advanced Semiconductor Engineering, Inc. Semiconductor package
KR102440889B1 (ko) * 2017-10-26 2022-09-05 주식회사 엘엑스세미콘 칩온필름 패키지
US10937713B2 (en) * 2018-06-12 2021-03-02 Novatek Microelectronics Corp. Chip on film package
US11581261B2 (en) * 2018-06-12 2023-02-14 Novatek Microelectronics Corp. Chip on film package
KR20200013185A (ko) 2018-07-26 2020-02-06 매그나칩 반도체 유한회사 반도체 패키지 제조 방법
CN209845575U (zh) * 2018-08-29 2019-12-24 惠科股份有限公司 一种显示面板和显示装置
CN111171746B (zh) * 2020-01-03 2022-02-08 京东方科技集团股份有限公司 防静电散热胶带及其制备方法和显示装置及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724290A2 (en) * 1995-01-25 1996-07-31 International Business Machines Corporation Electronic package
CN1420558A (zh) * 2001-11-21 2003-05-28 信越化学工业株式会社 一种散热结构
US6940141B2 (en) * 2002-08-29 2005-09-06 Micron Technology, Inc. Flip-chip image sensor packages and methods of fabrication
CN1835214A (zh) * 2005-03-18 2006-09-20 夏普株式会社 半导体器件及其制造方法
JP3939317B2 (ja) * 2004-06-29 2007-07-04 北川工業株式会社 熱伝導材及びその製造方法
CN101924082A (zh) * 2009-06-16 2010-12-22 东部高科股份有限公司 热释放半导体封装

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI317991B (en) * 2003-12-19 2009-12-01 Advanced Semiconductor Eng Semiconductor package with flip chip on leadframe
KR100771890B1 (ko) 2006-07-20 2007-11-01 삼성전자주식회사 씨오에프(ｃｏｆ)형 반도체 패키지
KR101189255B1 (ko) * 2009-10-30 2012-10-09 매그나칩 반도체 유한회사 칩온필름형 반도체 패키지
US8564954B2 (en) * 2010-06-15 2013-10-22 Chipmos Technologies Inc. Thermally enhanced electronic package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724290A2 (en) * 1995-01-25 1996-07-31 International Business Machines Corporation Electronic package
CN1420558A (zh) * 2001-11-21 2003-05-28 信越化学工业株式会社 一种散热结构
US6940141B2 (en) * 2002-08-29 2005-09-06 Micron Technology, Inc. Flip-chip image sensor packages and methods of fabrication
JP3939317B2 (ja) * 2004-06-29 2007-07-04 北川工業株式会社 熱伝導材及びその製造方法
CN1835214A (zh) * 2005-03-18 2006-09-20 夏普株式会社 半导体器件及其制造方法
CN101924082A (zh) * 2009-06-16 2010-12-22 东部高科股份有限公司 热释放半导体封装

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839898A (zh) * 2012-11-20 2014-06-04 瑞鼎科技股份有限公司 封装结构及其制造方法
TWI495061B (zh) * 2012-11-20 2015-08-01 Raydium Semiconductor Corp 封裝結構製造方法
CN103839898B (zh) * 2012-11-20 2016-04-06 瑞鼎科技股份有限公司 封装结构及其制造方法
WO2014206003A1 (zh) * 2013-06-26 2014-12-31 合肥京东方光电科技有限公司 一种灯条、背光模组和显示装置
CN103889196B (zh) * 2014-04-11 2016-06-22 江苏悦达新材料科技有限公司 一种高导热人工石墨膜的制备方法
CN103889196A (zh) * 2014-04-11 2014-06-25 江苏悦达新材料科技有限公司 一种高导热人工石墨膜的制备方法
CN104505347A (zh) * 2014-12-04 2015-04-08 江苏长电科技股份有限公司 一种在塑封过程中贴装石墨烯散热薄膜的方法
CN104505347B (zh) * 2014-12-04 2017-05-24 江苏长电科技股份有限公司 一种在塑封过程中贴装石墨烯散热薄膜的方法
CN108573930A (zh) * 2017-03-07 2018-09-25 联咏科技股份有限公司 薄膜倒装封装及薄膜倒装封装的制造方法
CN111276446B (zh) * 2017-03-07 2022-05-24 联咏科技股份有限公司 薄膜倒装封装及薄膜倒装封装的制造方法
CN111276446A (zh) * 2017-03-07 2020-06-12 联咏科技股份有限公司 薄膜倒装封装及薄膜倒装封装的制造方法
CN108573930B (zh) * 2017-03-07 2020-05-01 联咏科技股份有限公司 薄膜倒装封装及薄膜倒装封装的制造方法
US10643921B2 (en) 2017-03-07 2020-05-05 Novatek Microelectronics Corp. Chip on film package
CN109844943A (zh) * 2017-08-21 2019-06-04 金学模 改善散热及电磁波屏蔽功能的层压石墨的膜上芯片型半导体封装
CN109844944A (zh) * 2017-08-21 2019-06-04 金学模 改善视觉外观性及加工性的层压石墨的膜上芯片型半导体封装
TWI781215B (zh) * 2017-08-21 2022-10-21 金學模 改善散熱及電磁波屏蔽功能的層壓石墨的膜上晶片型半導體封裝
CN109844943B (zh) * 2017-08-21 2024-01-30 金学模 改善散热及电磁波屏蔽功能的层压石墨的膜上芯片型半导体封装
CN109844944B (zh) * 2017-08-21 2024-02-02 金学模 改善视觉外观性及加工性的层压石墨的膜上芯片型半导体封装
CN111403362A (zh) * 2020-03-27 2020-07-10 Tcl华星光电技术有限公司 覆晶薄膜封装方法、封装结构、显示装置、电子设备
CN111508910A (zh) * 2020-04-21 2020-08-07 颀中科技（苏州）有限公司 一种覆晶封装结构及封装方法
CN113889500A (zh) * 2020-07-01 2022-01-04 三星显示有限公司 显示装置、显示装置的返工方法及分离显示装置的设备

Also Published As

Publication number Publication date
CN102760704B (zh) 2016-05-18
US9070680B2 (en) 2015-06-30
KR20120122266A (ko) 2012-11-07
US20120273928A1 (en) 2012-11-01

Similar Documents

Publication Publication Date Title
CN102760704A (zh) 薄膜覆晶型半导体封装
US9307676B2 (en) Thermally enhanced electronic package
US9117401B2 (en) Organic light emitting diode display
CN105848882B (zh) 散热性优异的金属封装材料、其制备方法及用所述金属封装材料来封装的柔性电子器件
CN107482041A (zh) 柔性显示面板与柔性显示装置
TWI781215B (zh) 改善散熱及電磁波屏蔽功能的層壓石墨的膜上晶片型半導體封裝
US20160076829A1 (en) Heat dissipating sheet
US10772207B2 (en) Flexible semiconductor package and method for fabricating the same
CN106816547B (zh) 有机发光显示装置及其制造方法
KR102026561B1 (ko) 칩온필름형 반도체 패키지
WO2021103352A1 (zh) 一种显示装置
US20100244243A1 (en) Semiconductor device
TW201640631A (zh) Ｃｏｆ型半導體封裝及液晶顯示裝置
US20240170435A1 (en) Anisotropic conductive film with carbon-based conductive regions and related semiconductor device assemblies and methods
US20070232726A1 (en) Anisotropic conductive adhesive material and display panel unit having the same
KR101893248B1 (ko) 이방 도전성 필름 및 이를 이용한 접속 구조체
US20140027169A1 (en) Anisotropic conductive film
US20130277850A1 (en) Electronic device
TWI276212B (en) Electric connecting pad structure
US20230178686A1 (en) Semiconductor light-emitting element and display device including same
TWI271838B (en) Chip heat dissipation package structure
TW201039422A (en) Semiconductor device having at least one bump without overlapping specific pad or directly contacting specific pad

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20240424

Address after: Han Guozhongqingbeidao

Patentee after: Megna Zhixin Hybrid Signal Co.,Ltd.

Country or region after: Republic of Korea

Address before: Xiangting Cave, Xingde District, Chungbuk Kiangju City, South Korea

Patentee before: Magnachip Semiconductor, Ltd.

Country or region before: Republic of Korea

TR01 Transfer of patent right