TWI781215B - 改善散熱及電磁波屏蔽功能的層壓石墨的膜上晶片型半導體封裝 - Google Patents
改善散熱及電磁波屏蔽功能的層壓石墨的膜上晶片型半導體封裝 Download PDFInfo
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Abstract
本發明涉及一種膜上晶片型半導體封裝及包括其的顯示設備,所述膜上晶片型半導體封裝包括:積體電路晶片、印製電路板層及石墨層,所述積體電路晶片直接或藉由貼裝元件連接到所述印製電路板層的一面上,所述石墨層層壓在所述印製電路板層的相反一面上。
Description
本發明涉及一種作為驅動顯示設備、顯示器的主要部件的層壓石墨的膜上晶片型半導體封裝。
本申請主張於2017年8月21日向韓國專利局提交的韓國專利申請號為10-2017-0105442的優先權,其所有內容均包括在本說明書中。
近年來,隨著對大分辨率顯示器的關注度高漲,在操作驅動積體電路,尤其,在操作顯示器驅動積體電路晶片(Display Driver Integrated Circuit chip,DDI Chip)時,隨著發熱量增加,溫度上升到操作範圍以上,由此影響顯示器的畫質,或者阻礙顯示器的正常操作,或者因高溫而損壞,因此還會縮短壽命。針對所述大分辨率顯示器,到目前為止試圖以其他方式實現散熱效果,但其效果逐漸到達瓶頸,因此需要更具創新性的方式。
並且,在以智慧型手機為代表的移動電話以及性能高度化的電視(TV)及計算機中,相應模組中的射頻(RF)相關模組所產生的電磁干擾(electromagnetic interference,EMI)或在高速操作的積體電路晶片中產生的電磁波干擾影響到驅動積體電路,從而在液晶面板或有機發光二極體(OLED)面板中產
生噪音,或者經常出現變色問題,並且,相比於以前,液晶顯示器(LCD)畫面非常大,畫面頻率變得非常高速化,因此,由於細微的電磁波干擾的影響,可能在畫面上產生很大的噪點。
並且,液晶顯示器驅動積體電路相比較於以前,特性變高度化而以高速和高頻率操作,因此發生由驅動積體電路自身產生的EMI影響顯示器的畫質或者影響其他積體電路晶片的情況。
因此,需要一種屏蔽技術,以保護顯示器驅動積體電路免受電磁波干擾,或者保護其他積體電路晶片免受顯示器驅動積體電路中產生的電磁波干擾。
本發明是為了改善並解決在操作大分辨率顯示器的驅動積體電路晶片時產生的散熱問題及電磁波干擾問題而提出的,並且其目的在於提供一種能夠對驅動積體電路晶片中產生的熱有效進行散熱的膜上晶片型半導體封裝及包括其的顯示設備。
本發明提供一種膜上晶片型半導體封裝,其包括:積體電路晶片、印製電路板層以及石墨層,所述積體電路晶片直接或藉由貼裝元件連接到所述印製電路板層的一面,所述石墨層層壓在所述印製電路板層的相反一面上。
並且,本發明提供一種顯示設備,其包括:所述膜上晶片型半導體封裝、基板以及顯示器面板。
本發明的膜上晶片型半導體封裝及包括其的顯示設備可以將影響顯示器的操作及畫質的積體電路晶片的熱向外部方向散發,從而使其影響最小化。
並且,藉由防止積體電路晶片的溫度過高來使操作穩定在最佳狀態,顯示器的畫質也保持在最佳狀態,並且,減少由於驅動積體電路晶片的溫度過高而導致的損壞,增加驅動積體電路晶片的壽命,從而也能夠延長顯示器的壽命。
具體地,石墨層壓在印製電路板,因此不僅將電路部件所產生的熱向相反一面方向快速散發的效果優異,而且由於石墨本身的導電特性,電磁波干擾屏蔽效果優異,使得顯示器驅動積體電路晶片的功能不會劣化而保持恒定,並且,也能夠防止其他積體電路晶片的功能的劣化。
因此,持續保持顯示器的畫質的同時,增加驅動積體電路晶片的壽命,從而還能夠延長顯示器的壽命。
並且,本發明的一個實施例的膜上晶片型半導體封裝在鍵合(bonding)操作時,即使石墨已被層壓,藉由改善膜的相反一側的視覺外觀性,在石墨層方向上也能夠用肉眼確認膜的相反一側的外引腳接合墊,從而在與膜上晶片型半導體封裝和顯示器基板等的黏合技術時,能夠改善黏合的準確度及黏合的強度。
101:積體電路晶片
102:電路圖案層
103:基材部
104、107:黏合層
105、108:保護膜層
106、203:石墨層
109:貼裝元件
110:填料
202:印製電路板層
204:外引腳接合墊
301:軋輥
302:石墨粉末
401:石墨膜
第1圖是示出印製電路板層202的基材部103方向的一面上層壓有石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置
貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
第2圖是積體電路晶片101直接或藉由貼裝元件109連接到所述印製電路板層202的一面的結構的膜上晶片型半導體封裝的上部方向的平面圖。
第3圖是層壓有石墨層的膜上晶片型半導體封裝的下部方向的平面圖。
第4圖是示出在基材部103的一面上設有電路圖案層102的一般的印製電路板層202的圖。
第5圖是示出在如第4圖所示的印製電路板層202的基材部103方向的一面上,將石墨粉末302設置在黏合層104上之後,利用軋輥301向電路圖案層102及基材部103兩個方向施壓,從而將石墨層106層壓在印製電路板層202的一面上的技術的圖。
第6圖是示出在如第4圖所示的印製電路板層202的基材部103方向的一面上,將石墨膜401設置在黏合層104上之後,利用軋輥301向電路圖案層102及基材部103兩個方向施壓,從而將石墨層106層壓在印製電路板層202的一面上的技術的圖。
第7圖是示出在印製電路板層202的基材部103方向的一面上層壓有石墨層106的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第8圖是示出在印製電路板層202的基材部103方向的一面上依次層壓有黏合層104和石墨層106的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第9圖是示出在印製電路板層202的基材部103方向的一面上層壓有石墨層106,在石墨層106的基材部103的相反方向的一面上依次層疊黏合層107和保護膜層108的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第10圖是示出在印製電路板層202的基材部103方向的一面上依次層壓黏合層104和石墨層106,在石墨層106的基材部103的相反方向的一面上依次層疊黏合層107和保護膜層108的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第11圖是在印製電路板層202的基材部103方向的一面上層疊黏合層104、保護膜層105,在所述保護膜層105的所述基材部103方向的一面上層壓有石墨層106的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第12圖是第8圖的印製電路板層202的基材部103方向的一面上依次層壓有黏合層104和石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
第13圖是第9圖的印製電路板層202的基材部103方向的一面上層壓有石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
第14圖是示出第10圖的印製電路板層202的基材部103方向的一面上依次層壓有黏合層104和石墨層106,石墨層106的基材部103的相反方
向的一面上依次層疊黏合層107和保護膜層108的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
在本發明的一個實施例中,所述保護膜層108可以層疊在所述石墨層106的印製電路板層202的基材部103的相反方向的一面上。
第15圖是示出第11圖的印製電路板層202的基材部103方向的一面上層疊黏合層104、保護膜層105,所述保護膜層105的所述基材部103方向的一面上層壓有石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
第16圖是在印製電路板層202的一面上直接或藉由貼裝元件109連接的積體電路晶片101和外引腳接合墊204以與所述積體電路的長度方向垂直的方向設置的膜上晶片型半導體封裝的上部方向的平面圖。
第17圖是所述外引腳接合墊204以與積體電路晶片101的長度方向垂直的方向設置,所述石墨層106在除了設置所述外引腳接合墊204的所述印製電路板層202的面積的另一面的面積中,隔開兩個以上而層壓的膜上晶片型半導體封裝的層壓石墨層的下部方向的平面圖。
第18圖是在印製電路板層202的石墨層隔開兩個以上而層壓的一面上直接或藉由貼裝元件109連接的積體電路晶片101和外引腳接合墊204以與所述積體電路的長度方向垂直的方向設置的膜上晶片型半導體封裝的上部方向的平面圖。
下面,參照圖式對本發明的膜上晶片型半導體封裝及其製造方法的實施例進行詳細說明,以使本發明所屬技術領域的通常技術人員能夠容易實施。
下面,參照圖式對本發明的膜上晶片型半導體封裝及其製造方法進行說明。
下面,藉由實施例說明本發明的結構及特性,但是,所述實施例僅僅例示本發明,而並不限定本發明。
下面,參照第1圖說明膜上晶片型半導體封裝的結構。
本發明的膜上晶片型半導體封裝包括:積體電路晶片101;印製電路板層202;及石墨層106。
所述積體電路晶片101直接或藉由貼裝元件109連接到所述印製電路板層202的一面。所述貼裝元件109只要是對所述印製電路板層202的電路與所述積體電路晶片101進行電性連接,就不做限制,所述貼裝元件具體可以為凸塊(bump),其材質可以是金、銅、鎳或其組合。
本發明的一個實施例中,所述印製電路板層202可以包括電路圖案層102和基材部103。所述電路圖案層102可以是與所述積體電路晶片101組成電路的圖案,只要是組成電路的物質,並不做限制,其材質可以是金、銅、鎳或其組合。
本發明的一個實施例中,所述印製電路板層202的厚度可以是25μm至50μm。當厚度小於25μm時,抗彎曲或撕裂的強度下降,當厚度超過50μm時,柔軟性下降,從而可能導致彎曲性變差。
本發明的一個實施例中,所述積體電路晶片101與所述印製電路板層202之間的所述貼裝元件109的暴露面積可以用填料110來填埋。對於所述填料110,只要能夠抑制由於所述貼裝元件109被暴露在空氣而導致的氧化,則不做限制,所述填料具體可以是液體樹脂、環氧樹脂。
第2圖是積體電路晶片101直接或藉由貼裝元件109連接到所述印製電路板層202的一面上的結構的膜上晶片型半導體封裝的上部方向的平面圖。
本發明的一個實施例中,所述積體電路晶片101可以是顯示器驅動積體電路晶片(Display Driver Integrated Circut chip,DDI chip)。
所述石墨層106層壓在印製電路板層202的相反一面上。
第3圖是層壓有石墨層203的膜上晶片型半導體封裝的下部方向的平面圖。
本發明的一個實施例中,所述石墨層106可以是碳化的高分子膜或由石墨粉末302形成的膜。
第4圖是示出基材部103的一面上設有電路圖案層102的一般的印製電路板層202的圖。
第5圖是示出在如第4圖所示的印製電路板層202的基材部103方向的一面上,將石墨粉末302設置在黏合層104上之後,利用軋輥301向圖案層102及基材部103兩個方向施壓,從而將石墨層106層壓在印製電路板層202的一面上的技術的圖。
第6圖是示出在如第4圖所示的印製電路板層202的基材部103方向的一面上,將石墨膜401設置在黏合層104上之後,利用軋輥301向電路圖
案層102及基材部103兩個方向施壓,從而將石墨層106壓在印製電路板層202的一面上的技術的圖。
本發明的一個實施例中,所述石墨膜401可以是人造石墨,具體可以為碳化的高分子膜。
本發明的一個實施例中,所述高分子膜可以是聚醯亞胺膜。
本發明的一個實施方式中,所述碳化是實施包括碳化步驟和石墨步驟的熱處理方法。
本發明的一個實施方式中,所述碳化步驟包括將聚醯亞胺膜導入具有第一溫度區間的第一加熱器內,從而使所述高分子膜碳化並轉變為碳質膜的步驟。
本發明的一個實施方式中,所述第一溫度區間是500±50℃至1000℃的依次上升的區間。
本發明的一個實施方式中,所述石墨步驟包括將所述碳質膜導入具有作為溫度線性上升的區間的第二溫度區間的第二加熱器內,並轉變為石墨膜的步驟。
本發明的一個實施方式中,所述第二加熱器的長度為4000mm至6000mm。
本發明的一個實施方式中,所述第二溫度區間為1000℃至2800℃的依次上升的區間。
本發明的一個實施方式中,所述第二溫度區間包括1000℃至1500℃的第2-1溫度區間、1500℃至2200℃的第2-2溫度區間及2200℃至2800℃的第2-3溫度區間。
本發明的一個實施方式中,所述石墨步驟包括在所述第2-1溫度區間內,以0.33mm/秒至1.33mm/秒,橫向移動所述碳質膜,並使所述第二加熱器的內部溫度每分鐘上升1℃至5℃的同時,對所述碳質膜進行熱處理1至4小時的步驟。
本發明的一個實施例中,所述石墨層106的厚度可以為5μm至40μm。當厚度小於5μm時,散熱效果下降,當厚度超過40μm時,散熱效果同樣下降。
本發明的一個實施例中,在所述石墨層106與所述印製電路板層202之間還可以包括黏合層104、107。
本發明的一個實施例中,所述黏合層104、107可以是在施加壓力時顯現或強化黏合活性的壓敏黏合劑(Pressure sensitive adhesive,PAS),具體可以是丙烯酸類黏合劑或聚醯亞胺、聚對苯二甲酸乙二醇酯、雙面膠。
本發明的一個實施例中,所述黏合層104、107可以包括導電顆粒。
本發明的一個實施例中,所述黏合層104、107的厚度可以是3.5μm至5μm。
第7圖是示出在印製電路板層202的基材部103方向的一面上層壓有石墨層106的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第8圖是示出在印製電路板層202的基材部103方向的一面上依次層壓有黏合層104和石墨層106的膜上晶片型半導體封裝的製造技術過程中膜剖面的一個例子的圖。
本發明的一個實施例中,在所述石墨層106的一面上進一步可以包括保護膜層108。
本發明的一個實施例中,所述保護膜層108可以層疊在所述石墨層106的印製電路板層202的基材部103方向的一面上。
本發明的一個實施例中,所述保護膜層108可以是絕緣膜,具體可以為聚酯類樹脂膜,並且可以包括聚對苯二甲酸乙二醇酯(PET)、聚對苯二甲酸丁二醇酯(PBT)、聚對苯二甲酸丙二醇酯(PTET)、聚對苯二甲酸環己酯(PCHT)及聚萘二甲酸乙二醇酯(PEN)或其組合。
本發明的一個實施例中,所述保護膜層108的厚度可以為1.5μm至3.0μm。
第9圖是示出在印製電路板層202的基材部103方向的一面上層壓石墨層106,在石墨層106的基材部103的相反方向的一面上依次層疊黏合層107和保護膜層108的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第10圖是示出在印製電路板層202的基材部103方向的一面上依次層壓有黏合層104和石墨層106,在石墨層106的基材部103的相反方向的一面上依次層疊黏合層107和保護膜層108的膜上晶片型半導體封裝的製造技術中的膜剖面的一個例子的圖。
本發明的一個實施例中,所述保護膜層108可以層疊在所述石墨層106的印製電路板層202的基材部103的相反方向的一面上。
第11圖是示出在印製電路板層202的基材部103方向的一面上層疊有黏合層104、保護膜層105,在所述保護膜層105的所述基材部103方向
的一面上層壓有石墨層106的膜上晶片型半導體封裝的製造技術過程中的膜剖面的一個例子的圖。
第1圖是示出第7圖的印製電路板層202的基材部103方向的一面上層壓有石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
第12圖是第8圖的印製電路板層202的基材部103方向的一面上依次層壓有黏合層104和石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
第13圖是第9圖的印製電路板層202的基材部103方向的一面上層壓石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
第14圖是示出第10圖的印製電路板層202的基材部103方向的一面上依次層壓黏合層104和石墨層106,石墨層106的基材部103的相反方向的一面上依次層疊黏合層107和保護膜層108的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
本發明的一個實施例中,所述保護膜層108可以層疊在所述石墨層106的印製電路板層202的基材部103的相反方向的一面上。
第15圖是示出第11圖的印製電路板層202的基材部103方向的一面上層疊有黏合層104、保護膜層105,所述保護膜層105的所述基材部103方向的一面上層壓有石墨層106的膜中,在印製電路板層202的電路圖案層102方向的一面上設置貼裝元件109,並在間隙中填充填料110之後,層疊積體電路晶片101的膜上晶片型半導體封裝的剖面的一個例子的圖。
本發明的一個實施例中,在所述印製電路板層202的一面上還可以包括外引腳接合墊(Outer Lead Bonder pad)204。
所述外引腳接合墊204只要是電性連接所述印製電路板層202的電路與顯示器面板,則不做限制,所述外引腳接合墊的材質可以是金、銅、鎳或其組合。
本發明的一個實施例中,所述外引腳接合墊204可以以垂直於所述積體電路的長度方向的方向設置。
第16圖是在印製電路板層202的一面上直接或藉由貼裝元件109連接的積體電路晶片101和外引腳接合墊204以垂直於所述積體電路的長度方向的方向設置的膜上晶片型半導體封裝的上部方向的平面圖。
本發明的一個實施例中,所述石墨層106可以層壓在除了設置有所述外引腳接合墊的所述印製電路板層202面積的相反一面的面積上。對這種結構的膜上晶片型半導體封裝來說,改善了設置在印製電路板層202的外引腳接合墊204在層壓有石墨層203的方向上的視覺外觀性,從而在石墨層203方向上也可以藉由肉眼確認外引腳接合墊204,因此改善視覺外觀性,並且外引腳接合技術(Outer Lead Bonding process,OLB process)時改善黏合的準確度及黏合的強度。
本發明的一個實施例中,所述石墨層106可以是由兩個以上隔開而層壓。此時,在石墨層203方向上也區分積體電路晶片的個別單位區域,從而外引腳接合技術(Outer Lead Bondig process,OLB process)時改善黏合的準確度及黏合的強度。
第17圖是所述外引腳接合墊204以與積體電路晶片101的長度方向垂直的方向設置,所述石墨層106在除了設置所述外引腳接合墊的所述印製電路板層202的面積的相反一面的面積上,由兩個以上隔開而層壓的膜上晶片型半導體封裝的層壓有石墨層的下部方向的平面圖。
第18圖是印製電路板層202的石墨層由兩個以上隔開而層壓的一面上直接或藉由貼裝元件109連接的積體電路晶片101和外引腳接合墊204以與所述積體電路的長度方向垂直的方向設置的膜上晶片型半導體封裝的上部方向的平面圖。
本發明的一個實施例中,所述積體電路晶片101可以以與所述印製電路板層202的長度方向垂直的方向設置。
本發明的一個實施例中,印製電路板層202和石墨層106分別在以膜形態捲繞輥的狀態下,兩面被兩個軋輥301施壓,並可以藉由卷對卷(roll to roll)/(reel to reel)技術進行第一次層壓。此時,軋輥的壓力可以是3kg至30kg。並且,在石墨層106的一面上,承載膜(carrier film)可以藉由卷對卷供應並層疊,第一次層壓膜可以印製電路板層202/石墨層106/承載膜層(未示出)或印製電路板層202/黏合層104/石墨層106/承載膜層(未示出)的順序層疊。
本發明的一個實施例中,所述第一次層壓膜和黏合層104、107分別在以膜的形態捲繞輥的狀態下,兩面被兩個軋輥301施壓,並可以藉由卷
對卷(roll to roll)/(reel to reel)技術進行第二次層壓。此時,軋輥的壓力可以是3kg至20kg。並且,在石墨層106的一面上,離型膜(release film)可以藉由卷對卷供應並層疊,第二次層壓膜可以印製電路板層202/黏合層104/石墨層106/黏合層107/離型膜層(未示出)或印製電路板層202/黏合層107/石墨層106/離型膜層(未示出)的順序層疊。
本發明的一個實施例中,所述第二次層壓膜和保護膜層105、108分別在以膜形態捲繞輥的狀態下,兩面被兩個軋輥301施壓,並可以藉由卷對卷(roll to roll)/(reel to reel)技術進行第二次層壓。此時,軋輥301的壓力可以是3kg至20kg,軋輥301的溫度可以是70℃至90℃。並且,第三次層壓膜可以印製電路板層202/黏合層104/石墨層106/黏合層107/保護膜層108或印製電路板層202/黏合層107/石墨層106/保護膜層108的順序層疊。
下面,對包括所述膜上晶片型半導體封裝、基板及顯示器面板的顯示設備進行說明。
本發明的一個實施例中,所述基板可以與所述膜上晶片型半導體封裝的外引腳接合墊204電性連接。
本發明的一個實施例中,所述基板進一步包括外引腳接合墊(未示出),並可以與所述膜上晶片型半導體封裝的外引腳接合墊204電性連接。
本發明的一個實施例中,所述基板進一步包括外引腳接合墊(未示出),並且可以與所述膜上晶片型半導體封裝的外引腳接合墊204電性連接。此時,在所述基板的外引腳接合墊(未示出)與所述膜上晶片型半導體封裝的外引腳接合墊204之間還可以包括異方性導電膠膜(Anisotropic Conductive Film,ACF)層。所述基板的外引腳接合墊(未示出)/所述各向異性導電膜/所述膜上晶片
型半導體封裝的外引腳接合墊204可以依次設置後藉由外引腳接合技術(OLB process)層疊。
本發明的一個實施例中,顯示器面板可以是液晶顯示器或發光元件顯示器,其結構模組可以包括通常使用的顯示器面板的模組。
所述膜上晶片型半導體封裝與所述基板及所述顯示器面板電性連接,可以根據積體電路晶片的驅動訊號,藉由電訊號驅動並控制顯示器面板的相應像素。
以上說明應被理解為較佳實施例的示例,而不是限定發明的範圍。因此本發明應該由申請專利範圍和其等同物來確定而不是由以上說明的內容來確定。
101:積體電路晶片
102:電路圖案層
103:基材部
106:石墨層
109:貼裝元件
110:填料
202:印製電路板層
Claims (8)
- 一種膜上晶片型半導體封裝,其包括:積體電路晶片;印製電路板層;石墨層;以及外引線鍵合墊,位於該印製電路板層的一面,其中,該積體電路晶片直接或藉由貼裝元件連接到該印製電路板層的一面上,該石墨層層壓在該印製電路板層的相反一面上,該外引線鍵合墊以與該積體電路晶片的長度方向垂直的方向設置,該石墨層層壓在除了設置有該外引線鍵合墊的該印製電路板層面積的相反一面的面積上,該積體電路晶片為顯示器驅動積體電路晶片。
- 如請求項1所述之膜上晶片型半導體封裝,其中該石墨層與該印製電路板層之間進一步包括黏合層。
- 如請求項1所述之膜上晶片型半導體封裝,其中該石墨層的一面上進一步包括保護薄膜層。
- 如請求項1所述之膜上晶片型半導體封裝,其中該石墨層的厚度為5μm至40μm。
- 如請求項1所述之膜上晶片型半導體封裝,其中該石墨層為碳化的高分子膜或由石墨粉末形成的膜。
- 如請求項1所述之膜上晶片型半導體封裝,其中該石墨層層壓在該印製電路板層的兩面上。
- 如請求項1所述之膜上晶片型半導體封裝,其中該積體電路晶片以與該印製電路板層的長度方向垂直的方向設置。
- 一種顯示設備,其包括:如請求項1-7中的任一項所述之膜上晶片型半導體封裝;基板;以及顯示器面板。
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WO2019039848A1 (ko) * | 2017-08-21 | 2019-02-28 | 김학모 | 시인성 및 작업성이 개선된 그라파이트 라미네이트 칩온필름형 반도체 패키지 |
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US20200355958A1 (en) | 2020-11-12 |
TW201917843A (zh) | 2019-05-01 |
TWI803509B (zh) | 2023-06-01 |
CN109844944A (zh) | 2019-06-04 |
KR20190020636A (ko) | 2019-03-04 |
WO2019039847A1 (ko) | 2019-02-28 |
KR20190020637A (ko) | 2019-03-04 |
US11355687B2 (en) | 2022-06-07 |
TW201921621A (zh) | 2019-06-01 |
CN109844943A (zh) | 2019-06-04 |
CN109844944B (zh) | 2024-02-02 |
US20210074625A1 (en) | 2021-03-11 |
WO2019039848A1 (ko) | 2019-02-28 |
KR102198698B1 (ko) | 2021-01-05 |
KR102198697B1 (ko) | 2021-01-05 |
CN109844943B (zh) | 2024-01-30 |
US11437556B2 (en) | 2022-09-06 |
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